1240993 玖、發明說明： 【發明所屬技糊^員域^ 發明領域 本發明係有關於一種具有輸出緩衝電路或輸入輸出缓 5衝電路之半導體裝置，尤其係有關於一種有高於自己的供 電電壓之電壓之信號施加於輸出端子或輸入端子之半導體 裝置。 發明背景 10 近年來，藉以cM〇s構成之半導體積體電路（以下，稱 為LSI)為中心，微細化等之進展，LSI之驅動電源電壓漸趨 低電壓化。然而，由於往低電壓化之轉換狀況係依LSI之製 品領域而異，因此在構成系統時，產生必須組合構成電源 電壓不同之多數LSI之情況。因此，將以相異之電源電壓作 b動之LSI之端子串聯則將較佳。在該情況下，亦必須考慮到 與輸出信號之電壓振幅不同之電壓振幅之信號施加於端子 的情況。因此，即使由外部施加具有電源電壓以上之電壓 振幅之信號，不需要之漏電流不會流通於電源電壓之間= 是必要的，而迄今則有電路方法之提案。 20 驾知技術在專利文獻1中所揭示之驅動電路中，則有由 外部施加高於電源電壓VDD之電M時，冑電流亦不會流兩 如第11圖所示，驅動電路100中，輸出資料信號〇〇价 輸入至NAND閘極MNOR閘極12，同時輸出賦能信衆咖 1240993 係直接地輸入至NAND閘極11，並且透過反相器閘16〇而反 轉輸入至NOR閘極12。各個輸出端子係連接於電源電壓 VDD側之PMOS電晶體P1之閘極端子gi，及連接於源極端 子連接於接地電壓之NMOS電晶體N1之閘極端子。 5 pMOS電晶體P1之源極端子係經由pm〇s電晶體P2而 輸入電源電壓VDD，而NMOS電晶體N1之汲極端子係經由 閘極端子連接於電源電壓源VDD之NMOS電晶體N2而連接 於PMOS電晶體P1之沒極端子。且該連接點係端子BUS。 又，PMOS電晶體P2之閘極端子G2係經由NMQS電晶體 10 N4而連接於NMOS電晶體N6。NMOS電晶體N6之源極端子 係連接於接地電壓，並且有輸出賦能信號£^^輸入至閘極端 子。又，NMOS電晶體N4之閘極端子有電源電壓VDd輸入。 再者，PMOS電晶體P2之閘極端子G2與汲極端子之 間’有輸出賦能信號EN輸入至閘極端子之PMOS電晶體 15 P100連接。又，雖未圖示，但亦有將PMOS電晶體P100之閘 極端子連接於電源電壓VDD之構造。PMOS電晶體PI、P2、 P100之N井NW係連接於由PMOS電晶體構成之N井電壓控 制電路130。 驅動電路100中，當由電源電壓VDD將PMOS電晶體之 20閾值電壓以上之電壓施加於端子BUS時，PMOS電晶體P2 係維持非導通狀態，且不會有由端子BUS經由PMOS電晶體 P1、P2而於電源電壓VDD洩漏之漏電流流動。 再者’參照上述說明之先行技術文獻係如下所述。 專利文獻1 1240993 曰本專利公開公報特開昭64-72618號公報 第12圖係顯示第丨課題。於上述之驅動電路1〇〇追加輸 入緩衝電路4〇〇而構成有高於自己的電源電壓VDD之電壓 之輸入信號經由端子BUS輸入之輸出緩衝電路11〇時，工作 5模式則由輸出緩衝模式切換成輸入緩衝模式，並且在輸入 高於電源電壓VDD之電壓之輸入信號時可能會產生問題。 輸出緩衝模式時，係藉為低位階之輸出賦能信號ENs 換成低位階而開始輸入緩衝模式。當輸出賦能信號en切換 成低位階時，NMOS電晶體N6為非導通。該結果是沒有用 1〇以驅動PMOS電晶體P2之閘極端子G2之電晶體，而端子〇2 成為非接地狀態。該情況下，由於在此之前的閘極端子電 壓VG2為低位階，因此切換成輸入緩衝模式後，端子^二亦 維持低電壓位階。又，PMOS電晶體P100之閘極端子電壓成 為接地電壓，而PMOS電晶體P1之閘極端子VG1成為電源電 15壓VDD。又，亦有PMOS電晶體P100之閘極端子連接於電 源電壓VDD之型態。 在該狀態下，當藉端子BUS由電源電壓VDD輸入大於 PMOS電晶體之閾值電壓之高電壓信號VDDEx時，pMOS電 晶體則導通。在此，若PMOS電晶體Pioo之閘極端子為接地 20電壓，PM〇S電晶體P100則維持導通狀態，又，PMOS電晶 體P100之閘極端子連接於電源電壓VDD時，由於pM〇s電 晶體P100亦導通，因此端子G2之電壓位階VG2則由外部通 電至輸入之電壓位階，但因為電晶體或配線之寄生電阻或 寄生電容所致之時間常數而不能進行快速的充電。 1240993 因此，在端子G2之電壓位階VG2之充電過渡期間（Τ)， 則有PMOS電晶體Ρ2維持在導通狀態之情況。該情況下，會 產生由端子BUS往電源電壓VDD之漏電流I I Ν。由於該漏 電流I I N會由連接於連接端子BUS之介面電路IF之高電壓 5位階VDDex流入，因此藉介面電路IF之輸出電阻與PM〇S 電晶體PI、P2之導通電阻而被分壓，且匯流排線路Bus之 電壓位階VBUS會下降。若下降電壓低於緩衝電路Buf之輸 入閾值電壓，亦會有輸出電壓VX無法輸出之問題產生。 又，第13圖係顯示第2課題。由於係發生高於電源電壓 10 VDD之電壓VDDex來作為輸出信號，因此將驅動電路1〇〇 輸出構造當作類似NMOS電晶體之開汲極構造來使用時可 能會產生問題。 驅動電路100係將接地電壓供給至可輸入輸出資料信 號DOUT之端子，同時將輸出資料信號DOUT輸入至可輸入 15 輸出賦能信號EN之端子。 相對於高位階之輸出資料信號DOUT，驅動電路1〇〇係 成為可輸出狀態，並且輸出固定於接地電壓之低位階信 號。此時，由於PMOS電晶體P1維持在導通狀態，因此閘極 端子G2之電壓位階VG2為接地電壓。 20 當輸出資料信號DOUT遷移至低位階時，驅動電路100 成為不可輸出狀態，而PMOS電晶體PI、NMOS電晶體N1 則同時成為非導通。同時，NMOS電晶體亦成為非導通狀 態，而端子G2則成為維持在低電壓位階之未接地狀態。1240993 发明 Description of the invention: [Technical field to which the invention belongs] Field of the invention The present invention relates to a semiconductor device having an output buffer circuit or an input-output buffer circuit, and more particularly to a semiconductor device having a power supply voltage higher than its own The voltage signal is applied to the semiconductor device of the output terminal or the input terminal. Background of the Invention 10 In recent years, with the progress of miniaturization, centered on semiconductor integrated circuits (hereinafter referred to as LSIs) composed of cMOS, the driving power supply voltage of LSIs has gradually become lower. However, the transition status to lower voltages varies depending on the product area of the LSI. Therefore, when a system is configured, it is necessary to combine many LSIs with different power supply voltages. Therefore, it is better to connect the terminals of LSIs that operate at different power supply voltages in series. In this case, it is also necessary to consider a case where a signal having a voltage amplitude different from that of the output signal is applied to the terminal. Therefore, even if a signal having a voltage amplitude higher than the power supply voltage is applied from the outside, it is necessary that unnecessary leakage current does not flow between the power supply voltages. However, there have been proposals of a circuit method so far. 20 Driving Technology In the driving circuit disclosed in Patent Document 1, when an electric voltage M higher than the power supply voltage VDD is applied from the outside, the current does not flow. As shown in FIG. 11, in the driving circuit 100, The output data signal 00 is input to the NAND gate MNOR gate 12, and the output enabling signal is 1240993, which is directly input to the NAND gate 11, and is reversely input to the NOR gate through the inverter gate 160. 12. Each output terminal is connected to the gate terminal gi of the PMOS transistor P1 connected to the power supply voltage VDD side, and to the gate terminal of the NMOS transistor N1 connected to the source terminal connected to the ground voltage. 5 The source terminal of the pMOS transistor P1 is connected to the power supply voltage VDD via the pMOS transistor P2, and the drain terminal of the NMOS transistor N1 is connected to the NMOS transistor N2 connected to the power supply voltage source VDD via the gate terminal. The terminal of the PMOS transistor P1. And this connection point is the terminal BUS. The gate terminal G2 of the PMOS transistor P2 is connected to the NMOS transistor N6 via the NMQS transistor 10 N4. The source terminal of the NMOS transistor N6 is connected to the ground voltage and an output enable signal is input to the gate terminal. The gate terminal of the NMOS transistor N4 has a power supply voltage VDd input. Furthermore, between the gate terminal G2 and the drain terminal of the PMOS transistor P2, an output enabling signal EN is input to the PMOS transistor 15 P100 connected to the gate terminal. Although not shown, a structure in which a gate terminal of the PMOS transistor P100 is connected to a power supply voltage VDD is also available. The N-well NW of the PMOS transistors PI, P2, and P100 is connected to the N-well voltage control circuit 130 composed of a PMOS transistor. In the driving circuit 100, when a voltage equal to or more than 20 threshold voltages of the PMOS transistor is applied to the terminal BUS by the power supply voltage VDD, the PMOS transistor P2 maintains a non-conducting state, and no terminal BUS passes the PMOS transistor P1, P2 causes a leakage current to leak from the power supply voltage VDD. Furthermore, the prior art documents referred to above are as follows. Patent Document 1 1240993 Japanese Patent Laid-Open Publication No. Sho 64-72618 The figure 12 shows the first problem. When the input buffer circuit 400 is added to the drive circuit 100 described above and an input signal having a voltage higher than its own power supply voltage VDD is formed through the output buffer circuit 11 of the terminal BUS input, the operation 5 mode is changed from the output buffer mode. Switching to the input buffer mode may cause problems when inputting an input signal having a voltage higher than the power supply voltage VDD. In the output buffer mode, the input buffer mode is started by replacing the low-level output enable signal ENs with a low level. When the output enable signal en is switched to a low level, the NMOS transistor N6 is non-conductive. As a result, no transistor 10 was used to drive the gate electrode G2 of the PMOS transistor P2, and the terminal 02 became non-grounded. In this case, since the previous gate terminal voltage VG2 is at a low level, after switching to the input buffer mode, the terminal ^ 2 also maintains a low voltage level. In addition, the gate terminal voltage of the PMOS transistor P100 becomes a ground voltage, and the gate terminal VG1 of the PMOS transistor P1 becomes a power supply voltage 15 VDD. There is also a type in which the gate terminal of the PMOS transistor P100 is connected to the power supply voltage VDD. In this state, when a high-voltage signal VDDEx greater than the threshold voltage of the PMOS transistor is input from the power supply voltage VDD through the terminal BUS, the pMOS transistor is turned on. Here, if the gate terminal of the PMOS transistor Pioo is 20 volts to ground, the PMOS transistor P100 remains on, and when the gate terminal of the PMOS transistor P100 is connected to the power supply voltage VDD, due to the pM0s voltage The crystal P100 is also turned on, so the voltage level VG2 of the terminal G2 is externally energized to the input voltage level, but it cannot be charged quickly because of the time constant caused by the parasitic resistance or capacitance of the transistor or wiring. 1240993 Therefore, during the charging transition period (T) of the voltage level VG2 of the terminal G2, the PMOS transistor P2 may be maintained in the on state. In this case, a leakage current I I N is generated from the terminal BUS to the power supply voltage VDD. Since the leakage current IIN flows from the high-voltage 5-level VDDex of the interface circuit IF connected to the connection terminal BUS, it is divided by the output resistance of the interface circuit IF and the on-resistance of the PMMOS transistor PI and P2, and The voltage level VBUS of the bus line Bus will decrease. If the falling voltage is lower than the input threshold voltage of the buffer circuit Buf, there may be a problem that the output voltage VX cannot be output. Fig. 13 shows the second problem. Since a voltage VDDex higher than the power supply voltage of 10 VDD is generated as an output signal, using the output structure of the driving circuit 100 as an open-drain structure similar to an NMOS transistor may cause problems. The driving circuit 100 supplies a ground voltage to a terminal capable of inputting and outputting the data signal DOUT, and simultaneously inputs an output data signal DOUT to a terminal capable of inputting 15 outputting an enabling signal EN. With respect to the high-level output data signal DOUT, the driving circuit 100 becomes an output-enabled state, and outputs a low-level signal fixed to the ground voltage. At this time, since the PMOS transistor P1 is maintained in the on state, the voltage level VG2 of the gate terminal G2 is a ground voltage. 20 When the output data signal DOUT transitions to a low level, the driving circuit 100 becomes a non-output state, while the PMOS transistor PI and the NMOS transistor N1 become non-conductive at the same time. At the same time, the NMOS transistor also becomes non-conducting, and the terminal G2 becomes an ungrounded state maintained at a low voltage level.
無法進行來自驅動電路1〇〇之驅動之匯流排線路BUS 8 1240993 係藉外部提昇電阻Rup而充電至外部電壓VDDex，但因為寄 生笔阻與寄生電容而使充電無法快速進行。 當施加於端子BUS之電壓VBUS由電源電壓VDD成為 高於PMOS電晶體之閾值電壓之電壓時，PM〇S電晶體會導 5通且將端子G2充電，但是由於該充電亦無法快速進行，因 此在電壓位階VG2之充電過渡期間（T)，則有PMOS電晶體 P2維持在導通狀態。該情況下，會發生由端子bus往電源 電壓VDD之漏電流I I n。該漏電流I I N所致之匯流排線路 BUS之電壓下降，若低於緩衝電路Buf之輸入閾值電壓，則 10亦會由輸出電壓VX無法輸出之問題。 本發明係為解決前述習知技術之至少一種課題而作成 者’其目的在於提供一種具有輸出緩衝電路或輸入輸出緩 衝電路之半導體裝置，係即使有高於自己的電源電壓之電 壓k號施加於輸出端子或輸入輸出端子時，亦可透過端子 15 而不會有不要之漏電流漏洩，而可正確維持端子電壓者。 C發明内容 發明之揭示 為達成上述目的，第1態樣之半導體裝置係有高於自己 的電源電壓之電壓信號施加於輸出端子或輸入輸出端子 2〇者，其特徵在於包含有：一電源電壓源，及在輸出端子或 輪入輸出端子之間串聯之第1PMOS電晶體與第2pM〇s電 晶體，且第1PMOS電晶體之閘極端子係在非輪出狀態時， 保持於電源電壓，並且在輸出狀態時，因應輪出信號而驅 動。又，第2PMOS電晶體之閘極端子在非輪出狀態時，係 1240993 在施加於輸出端子或輸入輸出端子之施加電壓為電壓在電 源電壓加上預定電壓之電壓以上之第1領域中設定為施加 電壓，並在前述施加電壓為電壓小於電源電壓加上預定電 壓之電壓之第2領域中設定為電源電壓。 5 第1態樣之半導體裝置在輸出狀態時，則驅動控制第 1PMOS電晶體，且將輸出信號輸出至輸出端子或輸入輸出 ^子。在非輸出狀態時，若施加電壓為第2領域，則將電源 電壓供給至第1提第2PMOS電晶體之閘極端子且維持在非 導通狀態’及若施加電壓壓為第丨領域，則將施加電壓供給 10至第2PMOS電晶體之閘極端子且維持非導通狀態。 在此’所謂電源電壓加上預定電壓之電壓，係指閘極 端子設定為電源電壓時，第2PMOS電晶體由輸出端子或輸 入輸出端子向電源電壓源開始導通時之施加電壓者。 又’預定電壓係閘極端子設定為電源電壓時，相當於 15第2PM0S電晶體由輸出端子或輸入輸出端子向電源電壓源 開始導通時之第2PMOS電晶體之閾值電壓之電壓。 藉此，在非輸出狀態時，第2PMOS電晶體之閘極端子 不會成為非接地狀態，而至少可設定為電源電壓。由輸出 狀態轉換成非輸出狀態時，若施加於輸出端子或輸入輸出 2〇 端子之施加電壓在電源電壓加上預定電壓之電壓以上，第 2PMOS電晶體之閘極端子則由電源電壓設定為施加電壓， 但該時間很短，且因為第2PMOS電晶體之導通，不必要之 漏電流不會由輸出端子或輸入輸出端子流向電源電壓源。 又’有關第4態樣之半導體裝置係第1態樣之半導體裝 10 1240993 置，更包含：一閘極驅動部，係用以在非輸出狀態時供給 電源電壓，並在輸出狀態時供給接地電壓者；及一第丨閘極 電壓控制部，係用以在閘極驅動部與第2PMOS電晶體之閘 極端子之間，於第丨領域中阻止施加電壓由第2pM〇s電晶體 5之閘極端子往閘極驅動部施加，並在第2領域及輸出狀態 中，將來自閘極驅動部之供給電壓供給至第2pM〇S電晶體 之閘極端子者。 第4態樣之半導體裝置中，第2pm〇s電晶體之閘極端子 係經由第1閘極電壓控制部且藉閘極驅動部而供給電壓。且 在輸出狀/¾時供給接地電壓，在非輸出狀態時之第2領域中 仏給電源電壓。又，非輸出狀態時之第1領域中係藉第^閑 極電壓控制㈣可阻止施加於第2PM〇s電晶狀閘極端子 之施加電壓施加於閘極驅動部。 藉此，在非輸出狀態時，第2PMOS電晶體係藉閘極驅 15動部將閘極端子設定為電源電壓，且在第·域中維持在非 導通狀態。此外，在第丨領域中，閘極端子亦設定為施加電 壓且維持在非導通狀態。該情況下，施加電壓不會當作過 電壓而施加於閘極驅動部。又，不必要之電流不會由閘極 端子經由閘極驅動部而流動至電源電壓，可防止來自閑極 20端子之不必要的電流流入。 ° 此外，由於不必要之電流不會流動，因此可將輸出端 子或輸入輸出端子設定為預定之電壓位階。 又，有關第5態樣之半導體裝置係第4態樣之半導體裝 置，其中第1閘極電壓控制部係具有一用以連接閘極驅動部 1240993 與第2PMOS電晶體之閘極端子之第3PMOS電晶體，且第 3PMOS電晶體在第2領域中係導通的。 第5態樣之半導體裝置中，藉第丨閘極電壓控制部所具 備之第3PMOS電晶體，可連接控制閘極驅動部與第2pM〇s 5 電晶體之閘極端子，並且在弟2領域中係導通的，且將電源 電堡供給至弟2PMOS電晶體之閘極端子。 在此，第1閘極電壓控制部以具備包含第3PMOS電晶體 之第1傳輸閘為佳。 又，有關第7態樣之半導體裝置係第5態樣之半導體裝 10 置，更包含有一第2閘極電壓控制部，該第2閘極電壓控制 部可將第3PMOS電晶體之閘極端子在第1領域中設定為施 加電壓，並在第2領域中設定為由電源電壓開始導通第 3PMOS電晶體之電壓以下之電壓。 第7態樣之半導體裝置中，第3PMOS電晶體之導通控制 15 係藉第2閘極電壓控制部進行，且在第1領域中設定為施加 電壓而為非導通，並在第2領域中由電源電壓設定為第 3PMOS電晶體開始導通之電壓以下之電壓且導通。 在此，所謂開始導通之電壓係相當於第3PMOS電晶體 之閾值電壓之電壓。 20 v藉此，第3PMOS電晶體在第1領域中成為非導通並可阻 止往施加電壓之閘極驅動部之施加，同時在第2領域中成為 導通狀態並可藉閘極驅動部來驅動第2PMOS電晶體之閘極 端子。 又，有關第9態樣之半導體裝置係第7態樣之半導體裝 1240993 置，其中第2閘極電壓控制部具有一第4pM〇s電晶體，該第 4PMOS電晶體可連接輸出端子或輸入輸出端子與第 3PMOS電晶體之閘極端子，並將電源電壓源連接至閘極端 子。 ° 5 帛9態*之半導體裝置係藉第2閘極電壓控制部所具備 之第4PMOS電晶體，而可在第丨領域中將施加電壓供給至第 3PMOS電晶體之閘極端子。藉此，在第【領域中可使第 3PMOS電晶體為非導通。 又，有關第10態樣之半導體裝置在第7態樣之半導體裝 10置中，第2閘極電壓控制部更具有一可連接輸出端子或輸入 輸出端子與第3PMOS電晶體之閘極端子之第1NM〇s電晶 體，且第1NMOS電晶體之閘極端子在非輸出狀態時係設定 為電源電壓’並在輸出狀態時設定為接地電壓。 第10態樣之半導體裝置係藉第2閘極電壓控制部所具 15備之第iNMOS電晶體而連接控制第3pm〇S電晶體之閘極 端子與輸出端子或輸入輸出端子。在非輸出狀態時係可導 通且將電源電壓減去閾值電壓之電壓供給至第3PMOS電晶 體之閘極端子。 藉此’由於施加於第3PMOS電晶體之閘極端子之電壓 20係限制在電源電壓減去第1NMOS電晶體之閾值電壓之電 壓，因此在第2領域中可使第3PMOS電晶體導通。 又，有關第Π態樣之半導體裝置係第1〇態樣之半導體 裝置，其中在非輸出狀態時，於第1NMOS電晶體之閘極端 子設定有取代電源電壓且業經降壓之電壓。 13 1240993 藉此，施加於第3PMOS電晶體之閘極端子之電壓係限 制在電源電壓減去第1NMOS電晶體之閾值電壓之電壓，因 此可確實地使第3PMOS電晶體導通，並可在第2領域中將第 2PMOS電晶體之閘極端子設定為電源電壓。 5 又，有關第14態樣之半導體裝置係第9或第1〇態樣之半 導體裝置，其中第2閘極電壓控制部以具有一包含第4PMOS 電晶體或第1NMOS電晶體之第2傳輸閘為佳。 又，有關第15態樣之半導體裝置係第5態樣之半導體裝 置，其中第3PMOS電晶體在輸出狀態時係維持在導通狀 10態。該情況下，宜具備一可連接第3PMOS電晶體之閘極端 子與接地電壓之第2NMOS電晶體，且該第2NMOS電晶體在 輸出狀態時係導通的。藉此，在輸出狀態時，可將第2pms〇 電晶體之閘極端子設定為接地電壓。 圖式簡單說明 15 第1圖係顯示有關第1實施型態之半導體裝置之電路 圖。 第2圖係顯示N井電壓控制電路之第1具體例之電路圖。 第3圖係顯示N井電壓控制電路之第2具體例之電路圖。 第4圖係顯示>^井電壓控制電路之第3具體例之電路圖。 2〇 第5圖係顯示實施型態中之Ρ Μ Ο S電晶體P 4之閘極端子 電壓(VG4)之特性之特性圖。 第6圖係顯示實施型態中之PMOS電晶體Ρ2之閘極端子 電壓(VG2)之特性之特性圖。 第7圖係顯示有關第2實施型態之半導體裝置之電路 14 1240993The bus line BUS 8 1240993 which cannot be driven by the driving circuit 100 is charged to the external voltage VDDex by an external boost resistor Rup, but the charging cannot be performed quickly due to the stray pen resistance and parasitic capacitance. When the voltage VBUS applied to the terminal BUS changes from the power supply voltage VDD to a voltage higher than the threshold voltage of the PMOS transistor, the PMOS transistor will conduct 5 times and charge the terminal G2, but this charging cannot be performed quickly, so During the charge transition period (T) of the voltage level VG2, the PMOS transistor P2 is maintained in the on state. In this case, a leakage current I I n from the terminal bus to the power supply voltage VDD occurs. If the voltage of the bus line BUS caused by the leakage current I I N drops, if it is lower than the input threshold voltage of the buffer circuit Buf, the problem that the output voltage VX cannot be output will also occur. The present invention has been made to solve at least one of the problems of the conventional technology, and its object is to provide a semiconductor device having an output buffer circuit or an input-output buffer circuit. When the output terminal or input / output terminal is used, it is also possible to pass terminal 15 without unnecessary leakage current leakage, and to maintain the terminal voltage correctly. C. DISCLOSURE OF THE INVENTION In order to achieve the above object, the first aspect of the semiconductor device has a voltage signal higher than its own power supply voltage applied to the output terminal or the input / output terminal 20, which is characterized by including: a power supply voltage Source, and the first PMOS transistor and the second pMOS transistor connected in series between the output terminal or the wheel-in output terminal, and the gate terminal of the first PMOS transistor is maintained at the power supply voltage when it is in a non-wheel-out state, and In the output state, it is driven according to the turn-out signal. In addition, when the gate terminal of the second PMOS transistor is in a non-rotating state, the 1240993 is set in the first area where the voltage applied to the output terminal or the input / output terminal is equal to or higher than the power supply voltage plus a predetermined voltage. The applied voltage is set as the power supply voltage in the second area where the applied voltage is a voltage lower than the power supply voltage plus a predetermined voltage. 5 When the semiconductor device of the first aspect is in the output state, the first PMOS transistor is driven and controlled, and the output signal is output to an output terminal or an input / output terminal. In the non-output state, if the applied voltage is in the second field, the power supply voltage is supplied to the gate terminal of the first 2nd PMOS transistor and maintained in a non-conducting state 'and if the applied voltage is in the second field, the The applied voltage is supplied to the gate terminal of the second PMOS transistor and is maintained in a non-conducting state. Here, the voltage of the power supply voltage plus the predetermined voltage refers to the voltage applied when the second PMOS transistor is turned on from the output terminal or input / output terminal to the power supply voltage source when the gate terminal is set to the power supply voltage. When the predetermined voltage system gate terminal is set to the power supply voltage, it is equivalent to the voltage of the threshold voltage of the second PMOS transistor when the second PMMOS transistor starts to turn on from the output terminal or input / output terminal to the power supply voltage source. Therefore, in the non-output state, the gate terminal of the second PMOS transistor does not become the non-ground state, but at least it can be set to the power supply voltage. When switching from the output state to the non-output state, if the voltage applied to the output terminal or input / output 20 terminal is higher than the power supply voltage plus a predetermined voltage, the gate terminal of the second PMOS transistor is set to the applied voltage. Voltage, but this time is very short, and because the second PMOS transistor is turned on, unnecessary leakage current does not flow from the output terminal or input / output terminal to the power supply voltage source. Also, the fourth aspect of the semiconductor device is the first aspect of the semiconductor device 10 1240993, and further includes: a gate driving section for supplying a power supply voltage in a non-output state and a ground in the output state Voltage; and a first gate voltage control section, which is used to prevent the application of voltage from the second pM0s transistor 5 in the first field between the gate driving section and the gate terminal of the second PMOS transistor. The gate terminal is applied to the gate driving section, and in the second area and the output state, the supply voltage from the gate driving section is supplied to the gate terminal of the 2pMOS transistor. In the fourth aspect of the semiconductor device, the gate terminal of the 2pm transistor is supplied with voltage via the first gate voltage control section and the gate driving section. In addition, the ground voltage is supplied in the output state, and the power supply voltage is supplied in the second field in the non-output state. In the non-output state, the first field voltage control is used to prevent the voltage applied to the 2PM transistor gate from being applied to the gate driver. Therefore, in the non-output state, the second PMOS transistor system sets the gate terminal to the power supply voltage by the gate driver 15 and maintains the non-conducting state in the first region. In addition, in the first field, the gate terminal is also set to apply a voltage and maintain a non-conducting state. In this case, the applied voltage is not applied to the gate driving section as an overvoltage. In addition, unnecessary current does not flow from the gate terminal to the power supply voltage through the gate driving section, and unnecessary current from the idler 20 terminal can be prevented from flowing in. ° In addition, since unnecessary current does not flow, the output terminal or input / output terminal can be set to a predetermined voltage level. In addition, the semiconductor device of the fifth aspect is the semiconductor device of the fourth aspect, wherein the first gate voltage control section has a third PMOS for connecting the gate driving section 1240993 and the gate terminal of the second PMOS transistor. The transistor and the third PMOS transistor are turned on in the second field. In the fifth aspect of the semiconductor device, the gate terminal of the second pMOS transistor can be connected and controlled by the third PMOS transistor provided in the fifth gate voltage control section, and in the second field The middle system is on and supplies power to the gate terminal of the 2PMOS transistor. Here, it is preferable that the first gate voltage control unit includes a first transmission gate including a third PMOS transistor. In addition, the semiconductor device according to the seventh aspect is the semiconductor device 10 according to the fifth aspect, and further includes a second gate voltage control unit that can switch the gate terminal of the third PMOS transistor. In the first area, the voltage is set to be applied, and in the second area, it is set to a voltage equal to or lower than the voltage at which the third PMOS transistor is turned on from the power supply voltage. In the seventh aspect of the semiconductor device, the conduction control of the third PMOS transistor 15 is performed by the second gate voltage control unit, and it is set to be non-conducting by applying a voltage in the first area, and is controlled by the second area. The power supply voltage is set to a voltage lower than the voltage at which the third PMOS transistor starts to conduct, and is turned on. Here, the voltage at which the conduction is started is a voltage corresponding to the threshold voltage of the third PMOS transistor. 20v As a result, the third PMOS transistor becomes non-conducting in the first area and prevents the application of a voltage to the gate driving part, and becomes conductive in the second area and can be driven by the gate driving part. 2PMOS transistor gate terminal. In addition, the ninth aspect of the semiconductor device is the seventh aspect of the semiconductor device 1240993, in which the second gate voltage control section has a 4pM0s transistor, and the 4PMOS transistor can be connected to an output terminal or an input / output. The terminal and the gate terminal of the third PMOS transistor, and the power voltage source is connected to the gate terminal. ° 5 装置 9 states * semiconductor devices use the 4th PMOS transistor provided in the 2nd gate voltage control unit to supply the applied voltage to the 3rd PMOS transistor's gate terminal in the 3rd field. Thereby, the third PMOS transistor can be made non-conductive in the [field]. In the semiconductor device of the tenth aspect, in the tenth aspect of the semiconductor device of the seventh aspect, the second gate voltage control section further has a gate terminal that can be connected to the output terminal or input / output terminal and the gate terminal of the third PMOS transistor. The first NMOS transistor and the gate terminal of the first NMOS transistor are set to the power supply voltage when not in the output state and to the ground voltage when in the output state. The semiconductor device in the tenth aspect is connected to control the gate terminal of the 3pmMOS transistor and the output terminal or the input / output terminal by using the 15th iNMOS transistor provided in the second gate voltage control unit. In the non-output state, it can be turned on and the voltage of the power supply voltage minus the threshold voltage is supplied to the gate terminal of the third PMOS transistor. Therefore, since the voltage 20 applied to the gate terminal of the third PMOS transistor is limited to the voltage of the power source voltage minus the threshold voltage of the first NMOS transistor, the third PMOS transistor can be turned on in the second field. In addition, the semiconductor device of the ninth aspect is the semiconductor device of the tenth aspect, in which, in a non-output state, a voltage that is substituted for the power supply voltage and is stepped down is set at the gate terminal of the first NMOS transistor. 13 1240993 In this way, the voltage applied to the gate terminal of the third PMOS transistor is limited to the voltage of the power supply voltage minus the threshold voltage of the first NMOS transistor. Therefore, the third PMOS transistor can be reliably turned on, and the second PMOS transistor can be turned on. In the field, the gate terminal of the second PMOS transistor is set to the power supply voltage. 5. The semiconductor device according to the fourteenth aspect is the semiconductor device of the ninth or tenth aspect, wherein the second gate voltage control unit includes a second transmission gate including a fourth PMOS transistor or a first NMOS transistor. Better. The semiconductor device according to the fifteenth aspect is the semiconductor device according to the fifth aspect, in which the third PMOS transistor is maintained in the on state in the output state. In this case, a second NMOS transistor that can connect the gate terminal of the third PMOS transistor and the ground voltage should be provided, and the second NMOS transistor is turned on in the output state. Therefore, in the output state, the gate terminal of the 2pms0 transistor can be set to the ground voltage. Brief Description of Drawings 15 FIG. 1 is a circuit diagram showing a semiconductor device according to the first embodiment. Fig. 2 is a circuit diagram showing a first specific example of the N-well voltage control circuit. Fig. 3 is a circuit diagram showing a second specific example of the N-well voltage control circuit. Fig. 4 is a circuit diagram showing a third specific example of a well voltage control circuit. 2 Figure 5 is a characteristic diagram showing the characteristics of the gate voltage (VG4) of the P MOS transistor P 4 in the implementation mode. Fig. 6 is a characteristic diagram showing the characteristics of the gate terminal voltage (VG2) of the PMOS transistor P2 in the implementation form. FIG. 7 shows a circuit of a semiconductor device related to the second embodiment 14 1240993
第8圖係顯示位階轉換電路之電路圖。 第9圖係顯示實施型態中之第1作動狀態之說明圖。 第10圖係顯示實施型態中之第2作動狀態之說明圖。 5 第11圖係顯示有關習知技術之半導體裝置之電路圖。 第12圖係顯示習知技術中之第1課題之說明圖。 第13圖係顯示習知技術中之第2課題之說明圖。 【實施方式】 發明實施之最佳型態 10 以下，就本發明之半導體裝置，根據第1圖至第10圖並 參照圖示詳細說明具體化之實施型態。 第1圖所示之第1實施型態之半導體裝置中，輸入輸出 緩衝電路1除了輸出緩衝部之外，還具有一輸入緩衝電路 Μ，及一作為其耐壓保護用且將電源電壓源VDD連接於閘 15 極端子之NMOS電晶體Ν3。 又，設置PMOS電晶體Ρ3及Ν井電壓控制電路13以代替 習知技術之輸入輸出緩衝電路110中之PMOS電晶體Ρ100及 Ν井電壓控制電路130。PMOS電晶體Ρ3之源極端子及汲極 端子係分別連接於作為第2PMOS電晶體之機能之PMOS電 20晶體P2之閘極端子G2及輸入輸出端子BUS，而閘極端子則 連接電源電壓源VDD。又，輸入低位階表示輸出狀態之輸 入輸出模式切換信號CNT以取代輸出賦能信號EN。由於輸 入輸出柄式切換信號CNT與輪出賦能信號EN係以逆邏輯來 表示輸出狀恕，因此設有用以配合邏輯位階之反相器閘 15 1240993 16、17來取代反相器閘160。 且，除了 一輸入輸出緩衝電路11〇中之NM〇s電晶體N6 之外’還設置一用以連接電源電壓VDD與NM〇s電晶體N6 之PMOS電晶體P6而構成閘極驅動部8。pm〇s/NMOS電晶 5體P 6 /N 6之閘極端子係連接輸入輸入輸出模式切換信號 CNT之反相器閘π之輸出端子。 閘極驅動部8之輸出端子係經由第丨傳輸閘6與？厘〇8電 晶體P2之閘極端子G2連接，而第丨傳輸閘6係在其與輸入輸 出緩衝電路110中之NMOS電晶體N4之間，設置連接源極· 10及極端子之PMOS電晶體P4而構成。在此，pM〇s電晶體P4 係作為第3PMOS電晶體之機能，而第}傳輸閘6係作為第1 閘極電壓控制部之機能。 PMOS電晶體P4之閘極端子係經由源極·汲極端子連接 之PMOS/NMOS電晶體P5/N5所構成之第2傳輸閘7而連接 15於輸入輸出端子BUS。而且，閘極端子係經由連接於反相 器閘18之NMOS電晶體N7而連接於接地電壓。在此，PM〇s 電晶體P5係作為第4PMOS電晶體之機能，而NMOS電晶體 N5係作為第1NMOS電晶體之機能。又，第2傳輸閘7係作為 第2閘極電壓控制部之機能。 20 PMOS電晶體P5之閘極端子係連接於電源電壓源 VDD，同時NMOS電晶體N5之閘極端子係連接於緩衝電路 15，且輸入輸出模式切換信號cnt係輸入至緩衝電路15。 又’輸入輸出模式切換信號CNT亦輸入反相器閘18。 詳細情形則於後述，N井電壓控制電路13係因應施加於 16 1240993 輸入輸出端子BUS之施加電壓，在電源電壓VDD與施加電 壓VBUS之間，連續偏壓PM〇S電晶體P1至p5之N井NW之電 位的電路。不管施加電壓VBUS之電壓位階，皆可痛實地設 定NMOS電晶體井NW之電位，且NMOS電晶體井NW不會 5 成為未接地狀態。 輸入輸出緩衝電路1在輸入輸出模式切換信號CNT之 電壓位階為低位階時為輸出狀態。經由反相器閘17而由閘 極驅動部8輸出之低位階信號係一起導通構成第丨傳輸閘6 之PMOS/NMOS電晶體P4/N4，且將低位階供給至pM〇s電 1〇晶體P2之閘極端子G2(VG2 = Lo)。藉此PMOS電晶體P2則會 維持導通狀態。 在此’低位階之輸入輸出模式切換信號CNT在NAND 閘極11中係當作業經邏輯反轉之高位階信號，而在NOR閘 極12中則仍然為低位階信號，且分別輸入至一方之輸入端 15子。因此，此時之NAND閘極11及NOR閘極12係作為邏輯 反轉閘之機能。因此，輸入至輸入輸出緩衝電路之輸出資 料信號DOUT經由NAND閘極11及NOR閘極12而進行邏輯 反轉後’則驅動PMOS電晶體P1與NMOS電晶體N1，並經由 位於導通狀態之PMOS電晶體P2與NMOS電晶體N2而將資 20料輸出至輸入輸出端子BUS。 又’構成第1傳輸閘6之PMOS電晶體P4之導通係如下進 行。由於電源電壓VDD施加於閘極端子之PMOS電晶體 p5 ’及經由緩衝電路15而於閘極端子施加與輸入輸出模式 切換信號CNT同相之低位階信號之nm〇S電晶體N5，因此 17 1240993 第2傳輸閘7為非導通，且閘極端子G4切斷來自輸入輸出端 子BUS之路徑。相對於此，低位階之輸入輸出模式切換俨 號CNT業經反轉後供給至閘極端子，藉此，由於可導通 NMOS電晶體N7,故可供給接地電壓。因此，PM〇s電晶體 5 p4為導通狀態。 輸入輸出緩衝電路1在輸入輸出模式切換信號CNTi 電壓位階為南位階時為非輸出狀態，並經由輸入緩衝電路 14接受來自輸入輸出端子bus之輸入信號而進行受理輸入 資料信號DIN之輸入緩衝動作。 10 非輸出狀態時，高位階之輸入輸出模式切換信號cnt 在NAND閘極11係當作業經邏輯反轉之低位階信號，在 NOR閘極12中係仍為高位階信號，並且分別輸入至一方之 輸入端子，然後NAND閘極11及NOR閘極12則共同成為非 活性狀態。即，由NAND閘極11輸出高位階之信號，由n〇r 15閘極12輸出低位階之信號。PMOS電晶體P1之閘極端子固定 於電源電壓VDD，而NMOS電晶體N1之閘極端子固定於接 地電壓，則輸出緩衝之機能則成為非活性。 又，雖然係經由反相器閘17而由閘極驅動部§係輸出電 源電壓VDD之高位階信號，但藉因應輸入至輸入輸出端子 20 BUS之施加電壓VBUS來控制第1傳輸閘6,可作成即使在輸 入電壓高於電源電壓VDD之施加電壓VBUS的情況下，在輸 入輸出端子BUS與電源電壓VDD之間不會有不必要之漏電 流流動之構造。第1傳輸閘6之控制係指PM〇s電晶體P4之導 通控制。因高位階之輸入輸出模式切換信號而NMOS電晶 1240993 體N7為非導通，而藉第2傳輸閘7可控制閘極端子G4之電壓 位階VG4且進行PMOS電晶體η之導通控制。 第2傳輸閘中，係經由緩衝電路15而於NMOS電晶體N5 之閘極端子施加電源電壓VDD或如後述業經降壓之電壓位 5階。NM0S電晶體N5則具有對應輸入至輸入輸出端子BUS 之施加電壓VBUS之電壓位階而藉非飽和特性或飽和特性 進行作動’並且將閘極端子G4施加施加電壓VBUS、或電 源電壓VDDC或降壓電壓減去NMOS電晶體之閾值電壓 Vthn之電壓之特性。 10 又，pM〇S電晶體P5之閘極端子係固定於電源電壓 VDD。因此，施加電壓VBUS若為電源電壓VDD加上PMOS 電晶體之閾值電壓Vthp之電壓以上之高電壓則導通，並具 有將閘極端子G4施加施加電壓VBUS之特性。 以下，根據第5圖詳細說明閘極端子電壓VG4對施加電 15壓VBUS之特性。在此，係以在NMQS電晶體N5之閘極端子 施加電源電壓VDD之情況為例來作說明（第5圖中、（I))。 又，以下的說明中，係無視於PMOS/NMOS電晶體之導通 電阻或配線電阻等電壓下降成分來作說明。 若施加電壓VBUS小於電源電壓VDD減去閾值電壓 20 Vthn之電壓（0$ VBUS <VDD-Vthn)，NMOS 電晶體N5 則 在非飽和領域導通，而閘極端子電壓VG4則成為施加電壓 VBUS(VG4 = VBUS)。在此，在NMOS/PMOS之兩閾值電壓 為大略相等之條件下，PMOS電晶體P4會進行偏壓成在閾值 電壓Vthp值以上，並且在非輸出狀態時，由閘極驅動部8輸 19 1240993 出之電源電壓VDD則供給至閘極端子G2(VG2 = VDD)。因 此，VG2>VBUS，而PMOS電晶體p2維持在非導通狀態， 並且於輸入輸出端子BUS與電源電壓VDD之間不會有漏電 流流動。 5 若施加電壓VBUS在電源電壓VDd減去閾值電壓vthn 之電壓以上，且小於電源電壓VDD減去閾值電壓vthp之電 壓（VDD — Vthn S VBUS < VDD — Vthp)，NMOS 電晶體N5 則在飽和領域導通，並於閘極端子電壓VG4施加電源電壓 VDD減去閾值電壓vthn之電壓（VG4 = VDD — Vthn)，在 10此，在NMOS/PMOS之兩閾值電壓為大略相等之條件下， PMOS電晶體P4會進行偏壓成在閾值電壓Vthp以上，並在非 輸出狀態時，電源電壓VDD之高位階信號則供給至閘極端 子G2(GD2 = VDD)。因此，由於VG2>VBUS，故PMOS電 晶體P2則維持在非導通狀態，而在輸入輸出端子bus與電 15 源電壓VDD之間不會有漏電流流動。 若施加電壓VBUS在電源電壓VDD加上閾值電壓Vthp 之電壓以上’（VDD + Vthp$VBUS)，PMOS電晶體P5在非 飽和領域則導通，並於閘極端子電壓VG4供給施加電壓 VBUS(VG4 = VBUS)。因此，PMOS電晶體P4為非導通。然 20而，在該狀態下，由於PMOS電晶體P3為導通，因此閘極端 子電壓VG2施加於施加電壓VBUS(VG2 = VBUS)。由於為 VG2 = VBUS，PMOS電晶體P2維持在非導通狀態，不會有 漏電流流動於輸入輸出端子BUS與電源電壓VDD之間。 又’由於NMOS電晶體N4之閘極端子為電源電壓 20 1240993 VDD，因此施加電壓VbuS不會由閘極端子G2向閘極驅動 部8施加，且閘極驅動部8不會施加過電壓。再者，此時的 閘極驅動部8之PMOS電晶體P6係導通的，且輸出電源電壓 VDD。因此NMOS電晶體N4不會導通，且沒有不必要之漏 5電流由閘極端子G2朝閘極驅動部8流動。 第ό圖係顯示PMOS電晶體P2之閘極端子電壓VG2之特 性。施加電壓若小於電源電壓VDD加上閾值電壓Vthp之電 壓則供給電源電壓，施加電壓VBUS若在電源電壓VDD加上 閾值電壓Vthp之電壓以上則供給施加電壓VBUS。無論施加 10電壓VBUS之電壓位階如何，PM〇s電晶體p2不會導通，且 沒有漏電流在輸入輸出端子BUS與電源電壓之間流動。 在此，雖已以施加於NMOS電晶體N5之閘極端子之電 壓為電源電壓VDD來作說明，但緩衝電路15若具備後述之 電壓降壓機能，則可供給降壓電壓VDDL於閘極端子。藉 15 NMOS電晶體N5之飽和特性而供給至閘極端子G4之電壓 VG4則成為第5圖中所示之VDDL — Vthn，且PMOS電晶體 P4更確實地偏壓成導通狀態。 其次，以第2圖至第4圖說明N井電壓控制電路13之具體 例。 20 第2圖所示之第1具體例之N井電壓控制電路13A具有 一源極端子連接於電源電壓VDD，汲極端子及後閘極端子 連接於N井NWiPMOS電晶體P31A,;及一源極端子連接 於輸入輸出端子BUS，汲極端子及後閘極端子連接於^^井 NW，且閘極端子連接於電源電壓VDD之pM〇s電晶體 21 1240993 P32A。 PMOS電晶體P31A係藉連接於閘極端子G3丨AiPM〇s 電晶體控制部來控制導通·非導通。PM〇s電晶體控制部係 具有NMOS電晶體N31A、PMOS電晶體P33A，且視需要設 5置第1電壓降壓部。NMOS電晶體N31A係汲極端子連接於輪 入輸出端子BUS，源極端子經由第1電壓降壓部3丨而連接於 PMOS電晶體P31A之閘極端子G31A，閘極端子則連接於電 源電壓VDD。PMOS電晶體P33A係源極端子連接於輸入輸 出端子BUS，後閘極端子連接於n井NW，而閘極端子連接 10 於電源電壓VDD。 第1電壓降壓部31係將來自NMOS電晶體N31A之源極 端子之電壓降壓後，供給至PMOS電晶體P31A之閘極端子 G31A 〇 第2圖係對照顯示第1電壓降壓部31之具體例。具體例 15 (A)係串聯預定數之二極體且進行降壓。藉適當地設定二極 體之預疋數’在導通PMOS電晶體P31A時，可將電源電壓 VDD減去閾值電壓vthp之電壓以下之電壓供給至1>]^〇§電 晶體P31A之閘極端子G31A。具體例（B)係藉電阻元件將 NMOS電晶體N31A之源極端子之電壓進行分壓。若適當地 20設定分壓比，則可將電源電壓VDD減去閾值電壓Vthp之電 壓以下之電壓供給至PMOS電晶體P31A之閘極端子G31A。 第3圖所示之第2具體例之N井電壓控制電路1 3b係有 關於PMOS電晶體控制部，且設有第2電壓降壓部μ以代替 第1具體例之N井電壓控制電路13A(第2圖）之第【電壓降壓 22 1240993 部3卜 PMOS電晶體控制部中，NM〇s電晶體^^⑴係源極端 子直接連接PMOS電晶體P31B之閘極端子G31B，閘極端子 並經由第2電壓降壓部32而連接於電源電壓vDd。 5 第2電壓降壓部32係將電源電壓降壓後，將NMOS電晶 體N31B之閘極端子進行偏壓。藉此，可輸出業經kNM〇s 電晶體N31B之源極端子降壓之電壓，並供給至閘極端子 G31B 〇 v第3圖所示之第2電壓降壓部32之具體例係與第丨電壓 10降壓部31(第2圖）之具體例相同。將預定數之二極體（具體例 (A) )串聯，或由電阻元件將電源電壓vDd分壓（具體例 (B) )，藉此可得到業經降壓之電壓。 第1、第2具體例之N井電壓控制電路13A、13B中，若 施加電壓VBUS在電源電壓VDD加上閾值電壓Vthp之電壓 15 以上(VBUS^VDD + Vthp)，PMOS電晶體P33A、P33B則導 通’並將閘極端子G31A、G31B偏壓成電壓VBUS後，PMOS 電晶體P31A、P31B則成為非導通。另一方面，PMOS電晶 體P32A、P32B為導通而N井NW之電位為施加電壓VBUS。 當施加電壓VBUS降壓成小於電源電壓VDD加上閾值 20 電壓Vthp之電壓時(VBUS < VDD + Vthp)，PMOS電晶體 P32A、P33A、P32B、P33B為非導通。另一方面，NMOS 電晶體N31A、N31B為導通。 施加電壓VBUS降壓成NMOS電晶體N31A、N31B之閘 極端子之電壓減去閾值電壓Vthn之電壓後，由於NMOS電 23 1240993 晶體N31A、N31B進行飽和動作，因此閘極端子之電壓大略 固定為閘極端子的電壓減去閾值電壓Vthn之電壓。若如± 降壓，NMOS電晶體N31A、N31B則進行線性動作而導通， 並且施加電壓VBUS則持續輸出至NMOS電晶體N31A、 5 N31B之源極端子。 在此，供給至NMOS電晶體N31A、N31B之閘極端子之 電壓係電源電壓VDD(第2圖）或業經由電源電壓VDD降壓 之電壓（第3圖）。该電壓係直接地（第3圖）或降壓後（第2圖） 供給至PMOS電晶體P31A、P31B之閘極端子G31A、G31B。 10若沒有第1及第2電壓降壓部31、32,則以成為電源電壓VDD 減去NMOS電晶體N31A、N31B之閾值電壓Vthn之電壓為上 限來設定施加電壓VBUS。FIG. 8 is a circuit diagram showing a level conversion circuit. Fig. 9 is an explanatory diagram showing a first operating state in the implementation mode. Fig. 10 is an explanatory diagram showing a second operating state in the implementation mode. 5 FIG. 11 is a circuit diagram showing a conventional semiconductor device. Fig. 12 is an explanatory diagram showing a first problem in the conventional technology. Fig. 13 is an explanatory diagram showing a second problem in the conventional technology. [Embodiment Mode] Best Mode for Implementing the Invention 10 Hereinafter, a specific implementation mode of the semiconductor device of the present invention will be described in detail with reference to FIGS. 1 to 10 and with reference to the drawings. In the semiconductor device of the first embodiment shown in FIG. 1, the input-output buffer circuit 1 has an input buffer circuit M in addition to the output buffer section, and a power supply voltage source VDD for its withstand voltage protection. NMOS transistor N3 connected to gate 15 terminal. In addition, a PMOS transistor P3 and an N-well voltage control circuit 13 are provided instead of the PMOS transistor P100 and the N-well voltage control circuit 130 in the input-output buffer circuit 110 of the conventional technology. The source terminal and drain terminal of the PMOS transistor P3 are connected to the gate terminal G2 and the input / output terminal BUS of the PMOS transistor 20 P2, which functions as the second PMOS transistor, and the gate terminal is connected to the power supply voltage source VDD. . In addition, an input-output mode switching signal CNT indicating an output state at a low level is input instead of the output enable signal EN. Since the input-output handle switching signal CNT and the wheel-out enable signal EN are expressed by inverse logic, inverter gates 15 1240993 16, 17 are provided to match the logic level to replace the inverter gate 160. In addition to the NMOS transistor N6 in the input / output buffer circuit 110, a PMOS transistor P6 for connecting the power supply voltage VDD and the NMOS transistor N6 is provided to form the gate driving section 8. The gate terminal of pm〇s / NMOS transistor 5 body P 6 / N 6 is connected to the output terminal of the input gate of the inverter gate of the input / output mode switching signal CNT. The output terminal of the gate driving section 8 is transmitted via the first transmission gate 6 and? The gate terminal G2 of transistor P2 is connected, and the transmission gate 6 is connected between NMOS transistor N4 in input / output buffer circuit 110 and a PMOS transistor connected to source 10 and the terminal. P4. Here, the pMOS transistor P4 functions as a third PMOS transistor, and the} transmission gate 6 functions as a function of a first gate voltage control section. The gate terminal of the PMOS transistor P4 is connected to the input / output terminal BUS via a second transmission gate 7 composed of PMOS / NMOS transistors P5 / N5 connected to the source and drain terminals. The gate terminal is connected to the ground voltage via the NMOS transistor N7 connected to the inverter gate 18. Here, the PMOS transistor P5 functions as a fourth PMOS transistor, and the NMOS transistor N5 functions as a first NMOS transistor. The second transmission gate 7 functions as a second gate voltage control unit. 20 The gate terminal of the PMOS transistor P5 is connected to the power supply voltage source VDD, and the gate terminal of the NMOS transistor N5 is connected to the buffer circuit 15, and the input-output mode switching signal cnt is input to the buffer circuit 15. The input / output mode switching signal CNT is also input to the inverter gate 18. The details will be described later. The N-well voltage control circuit 13 responds to the voltage applied to the input / output terminal BUS of 16 1240993. The power supply voltage VDD and the applied voltage VBUS continuously bias N of the PM transistors P1 to p5 Well NW potential circuit. Regardless of the voltage level of the applied voltage VBUS, the potential of the NMOS transistor well NW can be set painfully, and the NMOS transistor well NW 5 will not become ungrounded. The input / output buffer circuit 1 is in an output state when the voltage level of the input / output mode switching signal CNT is a low level. The low-order signals output by the gate driving section 8 through the inverter gate 17 are turned on together to form the PMOS / NMOS transistor P4 / N4 of the transmission gate 6, and the low-order steps are supplied to the pM0s electric 10 crystal. Gate terminal G2 of P2 (VG2 = Lo). This keeps the PMOS transistor P2 on. Here, the low-level input-output mode switching signal CNT is a high-level signal that has been logically reversed when operating in NAND gate 11, while it is still a low-level signal in NOR gate 12, and is input to one of them respectively. 15 inputs. Therefore, the NAND gate 11 and the NOR gate 12 at this time function as logic inversion gates. Therefore, after the output data signal DOUT input to the input-output buffer circuit is logically inverted through the NAND gate 11 and the NOR gate 12, 'the PMOS transistor P1 and the NMOS transistor N1 are driven, and the PMOS transistor is in the conducting state. The crystal P2 and the NMOS transistor N2 output materials to the input / output terminal BUS. The conduction of the PMOS transistor P4 constituting the first transmission gate 6 is performed as follows. Since the power supply voltage VDD is applied to the PMOS transistor p5 'of the gate terminal and the low-level signal Nm transistor N5, which is in phase with the input-output mode switching signal CNT, is applied to the gate terminal via the buffer circuit 15, therefore 17 1240993 2 The transmission gate 7 is non-conductive, and the gate terminal G4 cuts off the path from the input / output terminal BUS. In contrast, the low-order input-output mode switching signal No. CNT is supplied to the gate terminal after being reversed, whereby the NMOS transistor N7 can be turned on, so that a ground voltage can be supplied. Therefore, the PMOS transistor 5 p4 is turned on. The input / output buffer circuit 1 is in the non-output state when the voltage level of the input / output mode switching signal CNTi is in the south level, and receives an input signal from the input / output terminal bus via the input buffer circuit 14 to perform an input buffer operation of an input data signal DIN. 10 In the non-output state, the high-level input-output mode switching signal cnt is a low-level signal that is logically inverted when the operation is in NAND gate 11, and is still a high-level signal in NOR gate 12, and is input to one side respectively. Input terminal, and then the NAND gate 11 and the NOR gate 12 become inactive. In other words, the NAND gate 11 outputs a high-level signal, and the nor 15 gate 12 outputs a low-level signal. The gate terminal of the PMOS transistor P1 is fixed to the power supply voltage VDD, while the gate terminal of the NMOS transistor N1 is fixed to the ground voltage, the output buffer function becomes inactive. In addition, although the gate drive section § outputs a high-order signal of the power supply voltage VDD via the inverter gate 17, the first transmission gate 6 can be controlled by the applied voltage VBUS input to the input / output terminal 20 BUS. Even when the input voltage is higher than the applied voltage VBUS of the power supply voltage VDD, there is a structure in which no unnecessary leakage current flows between the input / output terminal BUS and the power supply voltage VDD. The control of the first transmission gate 6 refers to the conduction control of the PMOS transistor P4. The NMOS transistor 1240993 body N7 is non-conducting due to the high-level input-output mode switching signal, and the second transmission gate 7 can control the voltage of the gate terminal G4 level VG4 and conduct conduction control of the PMOS transistor η. In the second transmission gate, a power supply voltage VDD or a stepped-down voltage level of the fifth stage is applied to the gate terminal of the NMOS transistor N5 via the buffer circuit 15. The NM0S transistor N5 has a voltage level corresponding to the applied voltage VBUS input to the input and output terminals BUS, and operates by using an unsaturated characteristic or a saturation characteristic. The characteristic of the voltage minus the threshold voltage Vthn of the NMOS transistor. 10 Moreover, the gate terminal of the pMOS transistor P5 is fixed to the power supply voltage VDD. Therefore, if the applied voltage VBUS is higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp of the PMOS transistor, it is turned on and has a characteristic of applying the applied voltage VBUS to the gate terminal G4. Hereinafter, the characteristics of the gate terminal voltage VG4 to the applied voltage VBUS will be described in detail with reference to FIG. 5. Here, the case where the power supply voltage VDD is applied to the gate terminal of the NMQS transistor N5 will be described as an example (Fig. 5, (I)). In the following description, the voltage drop components such as the on-resistance and wiring resistance of the PMOS / NMOS transistor will be ignored. If the applied voltage VBUS is less than the power supply voltage VDD minus the threshold voltage 20 Vthn (0 $ VBUS < VDD-Vthn), the NMOS transistor N5 is turned on in the unsaturated area, and the gate terminal voltage VG4 becomes the applied voltage VBUS ( VG4 = VBUS). Here, under the condition that the two threshold voltages of NMOS / PMOS are almost equal, the PMOS transistor P4 will be biased to be above the threshold voltage Vthp, and in the non-output state, the gate driver 8 will lose 19 1240993. The output power voltage VDD is supplied to the gate terminal G2 (VG2 = VDD). Therefore, VG2> VBUS, and the PMOS transistor p2 is maintained in a non-conducting state, and no leakage current flows between the input / output terminal BUS and the power supply voltage VDD. 5 If the applied voltage VBUS is higher than the voltage of the power supply voltage VDd minus the threshold voltage vthn and less than the voltage of the power supply voltage VDD minus the threshold voltage vthp (VDD — Vthn S VBUS < VDD — Vthp), the NMOS transistor N5 is saturated. The field is turned on, and the voltage of the power supply voltage VDD minus the threshold voltage vthn is applied to the gate terminal voltage VG4 (VG4 = VDD — Vthn). Here, under the condition that the two threshold voltages of NMOS / PMOS are approximately equal, the PMOS circuit The crystal P4 is biased to be above the threshold voltage Vthp, and in the non-output state, the high-level signal of the power supply voltage VDD is supplied to the gate terminal G2 (GD2 = VDD). Therefore, because VG2> VBUS, the PMOS transistor P2 is maintained in a non-conducting state, and no leakage current flows between the input / output terminal bus and the power source voltage VDD. If the applied voltage VBUS is higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp '(VDD + Vthp $ VBUS), the PMOS transistor P5 is turned on in the unsaturated region, and the applied voltage VBUS is supplied to the gate terminal voltage VG4 (VG4 = VBUS). Therefore, the PMOS transistor P4 is non-conductive. However, in this state, since the PMOS transistor P3 is on, the gate terminal voltage VG2 is applied to the applied voltage VBUS (VG2 = VBUS). Since it is VG2 = VBUS, the PMOS transistor P2 is maintained in a non-conducting state, and no leakage current flows between the input / output terminal BUS and the power supply voltage VDD. Since the gate terminal of the NMOS transistor N4 is the power supply voltage 20 1240993 VDD, the applied voltage VbuS is not applied to the gate driving section 8 by the gate terminal G2, and the gate driving section 8 does not apply an overvoltage. Furthermore, the PMOS transistor P6 of the gate driving section 8 at this time is turned on and outputs the power supply voltage VDD. Therefore, the NMOS transistor N4 is not turned on, and there is no unnecessary leakage. The current flows from the gate terminal G2 toward the gate driving section 8. Figure 6 shows the characteristics of the gate terminal voltage VG2 of the PMOS transistor P2. If the applied voltage is less than the power supply voltage VDD plus the threshold voltage Vthp, the power supply voltage is supplied, and if the applied voltage VBUS is greater than the power supply voltage VDD plus the threshold voltage Vthp, the applied voltage VBUS is supplied. Regardless of the voltage level of 10 VBUS applied, the PM0 transistor p2 will not conduct and no leakage current flows between the input and output terminals BUS and the power supply voltage. Here, although the voltage applied to the gate terminal of the NMOS transistor N5 has been described as the power supply voltage VDD, if the buffer circuit 15 has a voltage step-down function described later, the step-down voltage VDDL can be supplied to the gate terminal. . Based on the saturation characteristics of the 15 NMOS transistor N5, the voltage VG4 supplied to the gate terminal G4 becomes VDDL-Vthn shown in FIG. 5, and the PMOS transistor P4 is more surely biased into the on state. Next, specific examples of the N-well voltage control circuit 13 will be described with reference to Figs. 2 to 4. 20 The N-well voltage control circuit 13A of the first specific example shown in FIG. 2 has a source terminal connected to the power supply voltage VDD, a drain terminal and a rear gate terminal connected to the N-well NWiPMOS transistor P31A, and a source The terminal is connected to the input and output terminal BUS, the drain terminal and the rear gate terminal are connected to the NW well, and the gate terminal is connected to the pMOS transistor 21 1240993 P32A of the power supply voltage VDD. The PMOS transistor P31A is connected to the gate terminal G3 丨 AiPM0s transistor control unit to control conduction and non-conduction. The PM0s transistor control unit has an NMOS transistor N31A and a PMOS transistor P33A, and a first voltage step-down unit is provided as necessary. The NMOS transistor N31A series drain terminal is connected to the wheel-in output terminal BUS. The source terminal is connected to the gate terminal G31A of the PMOS transistor P31A through the first voltage step-down section 3 丨, and the gate terminal is connected to the power supply voltage VDD . The source terminal of the PMOS transistor P33A is connected to the input and output terminals BUS, the rear gate terminal is connected to the n-well NW, and the gate terminal is connected to the power supply voltage VDD. The first voltage step-down section 31 is a step-down voltage supplied from the source terminal of the NMOS transistor N31A and then supplied to the gate terminal G31A of the PMOS transistor P31A. Specific examples. Specific Example 15 (A) A predetermined number of diodes are connected in series and the voltage is reduced. By properly setting the pre-number of the diode ', when the PMOS transistor P31A is turned on, a voltage lower than the threshold voltage vthp of the power supply voltage VDD can be supplied to 1 >] ^^ §The gate terminal of the transistor P31A G31A. Specific example (B) is the voltage division of the source terminal of the NMOS transistor N31A by a resistance element. If the voltage division ratio is set appropriately, a voltage equal to or lower than the threshold voltage Vthp of the power supply voltage VDD can be supplied to the gate terminal G31A of the PMOS transistor P31A. The N-well voltage control circuit 1 3b of the second specific example shown in FIG. 3 is a PMOS transistor control section, and a second voltage step-down section μ is provided instead of the N-well voltage control circuit 13A of the first specific example. (Figure 2) In the [Voltage Buck 22 1240993 3 PMOS transistor control section, the NMOS transistor ^^ source terminal is directly connected to the gate terminal G31B and gate terminal of the PMOS transistor P31B. It is connected to the power supply voltage vDd via the second voltage step-down section 32. 5 The second voltage step-down section 32 is to reduce the power supply voltage and then bias the gate terminal of the NMOS transistor N31B. As a result, the voltage stepped down from the source terminal of the kNM0s transistor N31B can be output and supplied to the gate terminal G31B 0v. The specific example of the second voltage step-down section 32 shown in FIG. A specific example of the voltage 10 step-down section 31 (FIG. 2) is the same. A predetermined number of diodes (specific example (A)) are connected in series, or the power supply voltage vDd is divided by a resistive element (specific example (B)), thereby obtaining a step-down voltage. In the N-well voltage control circuits 13A and 13B of the first and second specific examples, if the applied voltage VBUS is more than 15 (VBUS ^ VDD + Vthp) at the power supply voltage VDD plus the threshold voltage Vthp, the PMOS transistors P33A and P33B are After turning on and biasing the gate terminals G31A and G31B to a voltage VBUS, the PMOS transistors P31A and P31B become non-conducting. On the other hand, the PMOS transistors P32A and P32B are turned on and the potential of the N well NW is the applied voltage VBUS. When the applied voltage VBUS is stepped down to a voltage smaller than the power supply voltage VDD plus the threshold 20 voltage Vthp (VBUS < VDD + Vthp), the PMOS transistors P32A, P33A, P32B, and P33B are non-conductive. On the other hand, the NMOS transistors N31A and N31B are turned on. The applied voltage VBUS is reduced to the voltage of the gate terminals of the NMOS transistors N31A and N31B minus the voltage of the threshold voltage Vthn. Since the NMOS 23 1240993 crystals N31A and N31B perform the saturation operation, the voltage of the gate terminals is almost fixed as the gate The voltage of the terminal minus the threshold voltage Vthn. If the voltage is reduced by ±, the NMOS transistors N31A and N31B conduct linear operation and turn on, and the applied voltage VBUS is continuously output to the source terminals of the NMOS transistors N31A and 5 N31B. Here, the voltage supplied to the gate terminals of the NMOS transistors N31A and N31B is the power supply voltage VDD (Fig. 2) or a voltage stepped down by the power supply voltage VDD (Fig. 3). This voltage is supplied to the gate terminals G31A and G31B of the PMOS transistors P31A and P31B directly (Figure 3) or after voltage reduction (Figure 2). 10. If the first and second voltage step-down sections 31 and 32 are not provided, the applied voltage VBUS is set with a voltage equal to the power supply voltage VDD minus the threshold voltage Vthn of the NMOS transistors N31A and N31B as the upper limit.
NMOS 電晶體N31A、N31B與PMOS 電晶體P31A、P31B 之間的閾值電壓為大略相等時，PMOS電晶體P31A、P31B 15之閘極·源極之間的電位差會施加成在閾值電壓Vthp以 上，並且導通而將電源電壓VDD供給至N井NW。 又’即使NMOS電晶體N31A、N31B與PMOS電晶體 P31A、P31B之間的閾值電壓相異時，由於具備第}或第2電 壓降壓部31、32至少一方，因此可將施加電壓VBUS充分地 20 降壓，且使PMOS電晶體P31A、P31B導通。 第4圖所示之第3具體例之N井電壓控制電路丨3(：係使 第1、第2具體例之N井電壓控制電路13八、13B(第2圖、第3 圖）藉PMOS電晶體控制部控制PMOS電晶體P31A、P31B， 並將PMOS電晶體P32A、P32B之閘極端子連接於電源電壓 24 1240993 VDD之連接關係逆轉之構造。即，在pM〇s電晶體p32Ci 閘極端子G32C與電源電壓VDD之間，設置NM〇s電晶體 N31C及PMOS電晶體P33C，並將NMOS電晶體N31C之閘極 端子連接於輸入輸出端子BUS。又，PMOS電晶體P31C、 5 P33C之閘極端子連接至輸入輸出端子BUS。該情況下，第1 電壓降壓部31、第2電壓降壓部32可作成與第1、第2具體例 之N井電壓控制電路13A、13B相同之連接。即，第1電壓降 壓部31可設置在NMOS電晶體N31C與閘極端子G32C之 間’而第2電壓降壓部32可連接NMOS電晶體N31C之閘極端 10 子與輸入輸出端子BUS之間。 第3具體例之N井電壓控制電路13C若未設置第1、第2 電壓降壓部31、32，由於施加電壓小於電源電壓VDD加上 閾值電壓Vthn之電壓，因此NMOS電晶體N31C進行飽和動 作。施加電壓VBUS減去閾值電壓vthn之電壓係供給至 15 PMOS電晶體P32C之閘極端子G32C。在NMOS/PMOS電晶 體之兩閾值電壓為大略相等之條件下，PMOS電晶體P32C 導通且將N井電位VNW當作施加電壓VBUS。 當施加電壓VBUS在電源電壓VDD加上閾值電壓Vthn 之電壓以上時，NMOS電晶體N31C會進行線性動作。而電 20 源電壓VDD則供給至PMOS電晶體P32C之閘極端子 G32C。然後PMOS電晶體P32C則導通，且將施加電壓VBUS 供給至N井。 、.再者，由於有關設有第1、第2電壓降壓部31、32之情 況的作用·效果與第1、第2具體例之N井電壓控制電路 25 1240993 13A、13B的情況相同，故在此省略說明。其中，若根據第 1電Μ降壓部31之電塵下降之效果，施加電壓vbus為電源 電壓VDD加上閾值電壓vthn之電壓以上之電壓時，由電源 電壓VDD業經由第丨電壓降壓部_壓之電壓位階設定為 5閘極i^G32C，若根據第2電壓降壓部32之電壓下降之效 果，閘極端子G32C則設定為施加電壓VBUS減去由幻電壓 降壓部32之電壓位階且減去閾值電壓Vthn之電壓位階。 —第L圖所示之第2實施型態之輸入輸出緩衝電路碘扪 實施型態之輸入輸出緩衝電路冰心有關作為與外部介面 10用之輸出緩衝部分，與内部電路所使用之電源電壓侧作 比較，係使用冑電壓之電源電Mvddh。此外，在電源電 壓VDD作動之電路部分與在高電源電壓vddh作動之電路 部分之間的介面則是設有位階轉換電路19、2〇、Μ。又， NMOS電晶體N5之閘極端子中施加電源電壓vdd。 15 第2實施型態之輸入輸出緩衝電路2係可達到與第斤 施型態之輸入輸出緩衝電路丨相同之作用效果者。於 NMOS電晶體N5之閘極端子施加電源電壓vdd而起之作 用·效果在輸入輸出緩衝電路丨中，係與緩衝電路15具有電 壓降壓機能之情況相同。即，閘極端子電"Μ成為較高 20電源電壓VDDH更為降壓之電源電壓VDD減去閾值電壓 Vthn之電壓(VG4 = VDD-Vthn)，並可更確實地將刚㈨電 晶體P4偏壓成導通狀態。 以下，藉第8圖（A)來表示第！實施型態之緩衝電路15 中，輸出電壓進行位階轉換成業經由電源電壓vdd降壓之 26 1240993 電壓VDDL時之具體例15A，及表示第2實施型態之位階轉 換電路19至21中，輸出電壓進行位階轉換成高於電源電壓 VDD之電壓之電源電壓VDDH時之具體例（19A至21A)。 輸入信號IN係輸入至由PMOS電晶體P52及NMOS電晶 5 體N52所構成之反相器閘及NMOS電晶體N51之閘極端子。 反相器閘之輸出端子係連接於NMOS電晶體N53之閘極端 子。NMOS電晶體N51、N53係源極端子連接於接地電壓， 同時汲極端子則分別連接於PMOS電晶體P51、P53之沒極端 子。PMOS電晶體P5卜P53之閘極端子係互相連接於其他電 10 晶體之汲極端子，而源極端子係共同連接於業經降壓之 VDDL(15A之型態），或高電源電壓VDDH(19A至21A之型 態）。When the threshold voltages between the NMOS transistors N31A, N31B and PMOS transistors P31A, P31B are approximately equal, the potential difference between the gate and source of the PMOS transistors P31A, P31B 15 will be applied above the threshold voltage Vthp, and It is turned on to supply the power supply voltage VDD to the N-well NW. Also, even when the threshold voltages between the NMOS transistors N31A and N31B and the PMOS transistors P31A and P31B are different, at least one of the second and third voltage step-down sections 31 and 32 is provided, so the applied voltage VBUS can be sufficiently 20 Step down and turn on the PMOS transistors P31A and P31B. The N-well voltage control circuit of the third specific example shown in FIG. 4 (3: The N-well voltage control circuit of the first and second specific examples 13 and 13B (Figures 2 and 3) are borrowed from PMOS The transistor control unit controls the structure of the PMOS transistors P31A and P31B, and connects the gate terminals of the PMOS transistors P32A and P32B to the power supply voltage 24 1240993 VDD. In other words, the p32Ci gate terminal of the pMOS transistor Between G32C and power supply voltage VDD, NMOS transistor N31C and PMOS transistor P33C are set, and the gate terminal of NMOS transistor N31C is connected to the input and output terminal BUS. In addition, the gate terminals of PMOS transistor P31C, 5 P33C It is connected to the input / output terminal BUS. In this case, the first voltage step-down section 31 and the second voltage step-down section 32 can be connected in the same way as the N-well voltage control circuits 13A and 13B of the first and second specific examples. That is, the first voltage step-down section 31 may be provided between the NMOS transistor N31C and the gate terminal G32C, and the second voltage step-down section 32 may be connected between the gate terminal 10 of the NMOS transistor N31C and the input / output terminal BUS. If the N-well voltage control circuit 13C of the third specific example is not provided with the first and second power The step-down sections 31 and 32 are saturated because the applied voltage is smaller than the power supply voltage VDD plus the threshold voltage Vthn, so the NMOS transistor N31C performs a saturation operation. The voltage applied to the VBUS minus the threshold voltage vthn is supplied to the 15 PMOS transistor P32C. Gate terminal G32C. Under the condition that the two threshold voltages of the NMOS / PMOS transistor are approximately equal, the PMOS transistor P32C is turned on and the N-well potential VNW is regarded as the applied voltage VBUS. When the applied voltage VBUS is at the power supply voltage VDD plus the threshold When the voltage is higher than the voltage Vthn, the NMOS transistor N31C performs a linear operation. The power source voltage VDD is supplied to the gate terminal G32C of the PMOS transistor P32C. Then the PMOS transistor P32C is turned on and the applied voltage VBUS is supplied to Well N. .. Furthermore, due to the functions and effects of the case where the first and second voltage step-down sections 31 and 32 are provided, and the N-well voltage control circuit 25 of the first and second specific examples 25 1240993 13A and 13B The situation is the same, so the description is omitted here. In accordance with the effect of the electric dust reduction of the first electric voltage step-down section 31, the applied voltage vbus is a voltage equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage vthn. At the time, the voltage level of the power supply voltage VDD via the first voltage step-down section is set to 5 gates i ^ G32C. If the voltage drop effect of the second voltage step-down section 32 is used, the gate terminal G32C is set to The applied voltage VBUS is subtracted from the voltage level of the magic voltage step-down section 32 and the voltage level of the threshold voltage Vthn is subtracted. —I / O buffer circuit of the second embodiment shown in Figure L. The I / O buffer circuit of the implementation mode is related to the output buffer part for the external interface 10 and the power supply voltage side for the internal circuit. For comparison, the Mvddh is a power supply using a high voltage. In addition, the interface between the circuit portion operated by the power supply voltage VDD and the circuit portion operated by the high power supply voltage vddh is provided with a level conversion circuit 19, 20, M. A power supply voltage vdd is applied to a gate terminal of the NMOS transistor N5. 15 The input / output buffer circuit 2 of the second embodiment can achieve the same effect as the input / output buffer circuit of the second embodiment. The effect and effect of applying the power supply voltage vdd to the gate terminal of the NMOS transistor N5 is the same as in the case where the buffer circuit 15 has a voltage step-down function in the input / output buffer circuit. That is, the gate electrode voltage " M becomes a voltage higher than the power supply voltage VDD which is higher than 20 volts and the voltage VDD minus the threshold voltage Vthn (VG4 = VDD-Vthn), and the rigid transistor P4 can be more reliably Biased to a conducting state. In the following, the eighth figure (A) is used to show the number one! In the buffer circuit 15 of the implementation type, the output voltage is level-converted to a specific example 15A when the voltage VDDL is stepped down by the power supply voltage vdd 26 1240993, and in the level conversion circuits 19 to 21 showing the second implementation type, the output A specific example (19A to 21A) when the voltage is level-converted to a power supply voltage VDDH that is higher than the power supply voltage VDD. The input signal IN is input to an inverter gate formed by a PMOS transistor P52 and an NMOS transistor 5 body N52 and a gate terminal of the NMOS transistor N51. The output terminal of the inverter gate is connected to the gate terminal of the NMOS transistor N53. The NMOS transistor N51 and N53 series source terminals are connected to the ground voltage, while the drain terminals are connected to the PMOS transistor P51 and P53 terminals. The gate terminals of PMOS transistors P5 and P53 are connected to the drain terminals of other transistors, and the source terminals are connected to the step-down VDDL (type 15A), or the high supply voltage VDDH (19A To 21A).
若輸入高位階之輸入信號IN，NMOS電晶體N51則導 通，並將PMOS電晶體P53之閘極端子電壓決定為接地電 15壓，藉此PM〇S電晶體P53則導通。又，業經由反相器閘反 轉之低位階之信號則輸入NMOS電晶體N53之閘極端子 後，NMOS電晶體N53則為非導通。因此，輸出之信號〇UT 則經由PMOS電晶體P53而成為降壓電壓VDDL或高電源電 壓VDDH。 20 在此’輸出之信號OUT輸入至PMOS電晶體P51之閘極 端子，並令PMOS電晶體P51為非導通。 輸入信號IN則係輸入接地電壓之低位階信號。該情況 下’ NMOS電晶體N51為非導通，且切斷由PMOS電晶體P53 之閘極端子往接地電壓之路徑。另一方面，由於業經由反 27 1240993 相态閘反轉之高位階之信號輸入至]^1^〇8電晶體N53之閘 極端子，因此NMOS電晶體N53則導通。因此，輸出之信號 〇UT則經由NMOS電晶體N53而成為接地電壓。輸出之信號 out係輸入電晶體P51之閘極端子，而pM〇s電晶 5體1"51則導通且PMOS電晶體P53維持在非導通。 又’如第8(B)圖所示，亦可藉有輸入信號IN •輸出信 號OUT分別輸入輸出至源極·汲極端子，電源電壓並 連接於閘極端子之NMOS電晶體N54來形成降壓電路。該情 況是，當輸入電源電壓VDD位階之高位階信號作為輸入信 10號IN時，則輸出電源電壓VDD減去閾值電壓Vthn之電壓。 第9圖、第1〇圖係顯示使用第丨、第2實施型態之輸入輸 出緩衝電路1、2，且經由輸入輸出端子BUS施加高於自己 的電源電壓之電壓位階之施加電壓VBUS時之作動狀態。 第9圖所示之第丨作動狀態係由輸出狀態切換成非輸出 15 狀態時，在習知技術中由於漏電流I I N會從由介面電路吓 供給之電壓VDDex經由輸入輸出端子BUS而朝電源電壓 VDD流動，因此有緩衝電路Buf無法正確辨識輸入輸出端子 BUS之電壓位階VBUS的缺點之情形（第12圖之第1課題），而 在輸入輸出緩衝電路1、2中，顯示由輸出狀態切換成非輸 20出狀態時，也沒有不必要之電流流動，且緩衝電路Buf可正 確地辨識輸入輸出端子BUS之電源位階VBUS，又輸出電壓 VX可正確地輸出。 第10圖所示之第2作動狀態係NMOS電晶體之開汲極 構造中匯流排線路BUS在充電時，在習知技術中由於因外 28 1240993 部提昇電阻Rup而充電需要預定時間，漏電流nN會由電壓 VDDex朝電源電壓VDD流動，因此有緩衝電路Buf無法正確 辨識輸入輸出端子BUS之電壓位階VBUS的缺點之情形（第 13圖之第2課題），而在輸入輸出緩衝電路1、2中，顯示即 5使在充電途中也沒有不必要之電流流動，且緩衝電路Buf 可正確地辨識輸入輸出端子BUS之電源位階VBUS，又輸出 電壓VX可正確地輸出。 如上述詳細地說明，有關第1、第2實施型態之輸入輸 出緩衝電路1、2在為非輸出狀態之輸入狀態時，PM〇s電晶 10體P2之閘極端子G2不會成為未接地狀態，而至少設定為電 源電壓VDD。由輸出狀態轉換成輸入狀態時，施加於輸入 輸出端子BUS之施加電壓VBUS若在電源電壓VDD加上 PMOS電晶體之閾值電壓Vthp之電壓以上時，閘極端子G會 在短時間内由電源電壓VDD設定為施加電壓VBUS。因此， 15藉1^“08電晶體P2之導通，不必要之漏電流不會由輸入輸出 端子BUS朝電源電壓流動，並可防止不必要之漏電流流入 於輸入輸出端子BUS。又，由於沒有不必要之漏電流，故 靶加電壓bus之電壓位階不會變動，而可維持在預定之電 壓位階。 2〇 又，在輸入狀態時，PMOS電晶體P2係藉閘極驅動部8 而將閘極端子G2設定為電源電壓VDD(VG2 = VDD)，且在 電壓小於電源電壓VDD加上閾值電壓Vthp之電壓時維持在 非導通狀態。此外，電壓在電源電壓VDD加上閾值電壓Vthp 之電壓以上時，閘極端子G2係設定為施加電壓VBUS且維 29 1240993 持在非導通狀態。且在該情況下，過電壓亦不會施加在閘 極驅動部8。又，不必要之漏電流不會由閘極端子g2經由閘 極驅動部8而朝電源電壓VDD流動，並可防止不必要之漏電 流。此外，由於沒有不必要之漏電流，因此可將輸入輸出 5端子BUS設定在預定之電壓位階。 又，由於施加在PMOS電晶體P4之閘極端子G4之電壓 係限制在電源電壓VDD或業經降壓之電壓vdDL減去 NMOS電晶體N5之閾值電壓vthn之電壓，因此電壓小於電 ι源電壓VDD加上閾值電壓VthP2電壓時，可使PMOS電晶體 10 P4確實地導通，並可將pM〇s電晶體p2之閘極端子㈤設定 為電源電壓VDD。 又，本發明並非限定於前述實施型態者，在不脫離本 發明宗旨之範圍内皆可作種種改良、變化。 產業上之可利用性 15 根據本發明，即使在高於自己的電源電壓之電壓信號 施加在輸出端子或輸入輸出端子的情況下，不必要之漏電 流不會經由端子流動。因此，外部電路連接於輸出端子或 輸入輸出端子時，可以不管施加於輪出端子或輪入輸出端 子之電壓位階，而可正確地設定端子電壓之電壓位階，並 '可安定地進行往端子BUS之信號輸出或輸入輸出。 30 1240993 【圖式簡單說明】 第1圖係顯示有關第1實施型態之半導體裝置之電路 圖。 第2圖係顯不n井電壓控制電路之第1具體例之電路圖。 5 第3圖係顯井電壓控制電路之第2具體例之電路圖。 第4圖係顯示n井電壓控制電路之第3具體例之電路圖。 第5圖係顯示實施型態中之PMOS電晶體P4之閘極端子 電壓(VG4)之特性之特性圖。 第6圖係顯示實施型態中之PMOS電晶體P2之閘極端子 10電壓(VG2)之特性之特性圖。 第7圖係顯示有關第2實施型態之半導體裝置之電路 圖。 第8圖係顯示位階轉換電路之電路圖。 第9圖係顯示實施型態中之第1作動狀態之說明圖。 15 第10圖係顯示實施型態中之第2作動狀態之說明圖。 第11圖係顯示有關習知技術之半導體裝置之電路圖。 第12圖係顯示習知技術中之第丨課題之說明圖。 第13圖係顯示習知技術中之第2課題之說明圖。 【圖式之主要元件代表符號表】 1，2, 110···輸入輸出緩衝電路 6.. .第1傳輸閘 7.. .第2傳輸閘 8···閘極驅動部 11...NAND 閘極 1240993 12, ·.NOR 閘極 13, 13A〜13C，130...N井電壓控制電路 14, 100...輸入緩衝電路 15…緩衝電路 16〜18, 160…反相器閘 19〜21...位階轉換電路 31.. .第1電壓降壓部 32.. .第2電壓降壓部 100.. .驅動電路 Buf...緩衝電路 BUS...輸入輸出端子/匯流排線路 CNT...輸入輸出模式切換信號 DIN···輸入資料信號 DOUT...輸出資料信號 EN...輸出賦能信號 G1 〜G2, G4, G31A，G31B，G32C···閘極端子 IF.··介面電路 11N...漏電流 IN...輸入信號 N1 〜N7，N31A〜N31C，N51 〜N54...NMOS 電晶體 NW...N 井 32 1240993 OUT...輸出信號 P1 〜P6， P31A〜P31C， P32A 〜P32C， P33 A〜P33C， P51 〜P53, P100，...PMOS 電晶體If a high-level input signal IN is input, the NMOS transistor N51 is turned on, and the gate terminal voltage of the PMOS transistor P53 is determined as the ground voltage, thereby the PMOS transistor P53 is turned on. In addition, the low-level signal reversed through the inverter gate is input to the gate terminal of the NMOS transistor N53, and the NMOS transistor N53 is non-conducting. Therefore, the output signal OUT becomes the step-down voltage VDDL or the high power supply voltage VDDH via the PMOS transistor P53. 20 The signal OUT output here is input to the gate terminal of the PMOS transistor P51, and the PMOS transistor P51 is made non-conductive. The input signal IN is a low-order signal of the input ground voltage. In this case, the NMOS transistor N51 is non-conducting and cuts off the path from the gate terminal of the PMOS transistor P53 to the ground voltage. On the other hand, since the high-level signal of the inverse 27 1240993 phase-state inversion is input to the gate terminal of the transistor N53, the NMOS transistor N53 is turned on. Therefore, the output signal OUT becomes a ground voltage via the NMOS transistor N53. The output signal out is the gate terminal of the input transistor P51, while the pMOS transistor 5 body 1 " 51 is turned on and the PMOS transistor P53 is kept non-conducting. As shown in Figure 8 (B), the input signal IN and output signal OUT can be input and output to the source and drain terminals respectively. The power supply voltage is connected to the NMOS transistor N54 connected to the gate terminal to form a drop.压 电路。 Voltage circuit. In this case, when the high-level signal of the input power voltage VDD level is used as the input signal No. 10 IN, the voltage of the power supply voltage VDD minus the threshold voltage Vthn is output. Fig. 9 and Fig. 10 show the case where the input and output buffer circuits 1 and 2 of the first and second implementation types are used, and an applied voltage VBUS higher than the voltage level of the power supply voltage is applied through the input and output terminals BUS. Active state. When the operation state shown in FIG. 9 is switched from the output state to the non-output 15 state, in the conventional technology, the leakage current IIN will change from the voltage VDDex supplied from the interface circuit to the power supply voltage through the input and output terminals BUS due to the leakage current. VDD flows, so the buffer circuit Buf cannot correctly identify the shortcoming of the voltage level VBUS of the input and output terminal BUS (the first problem of FIG. 12), and in the input and output buffer circuits 1, 2, the display is switched from the output state to In the non-output 20-output state, no unnecessary current flows, and the buffer circuit Buf can correctly identify the power level VBUS of the input and output terminals BUS, and the output voltage VX can be output correctly. The second operating state shown in FIG. 10 is the open-drain structure of the NMOS transistor. When the bus line BUS is being charged, in the conventional technology, it takes a predetermined time to charge due to the external 28 1240993 boost resistor Rup, and the leakage current nN will flow from the voltage VDDex to the power supply voltage VDD. Therefore, the buffer circuit Buf cannot correctly identify the disadvantage of the voltage level VBUS of the input and output terminal BUS (second problem in FIG. 13). In the display, 5 is displayed so that no unnecessary current flows during charging, and the buffer circuit Buf can correctly identify the power level VBUS of the input and output terminals BUS, and the output voltage VX can be output correctly. As explained in detail above, when the input and output buffer circuits 1 and 2 of the first and second implementation modes are in an input state other than the output state, the gate terminal G2 of the PM10 transistor 10 body P2 will not become unused. The ground state is at least set to the power supply voltage VDD. When switching from the output state to the input state, if the applied voltage VBUS applied to the input and output terminals BUS is higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp of the PMOS transistor, the gate terminal G will be changed by the power supply voltage in a short time. VDD is set to the applied voltage VBUS. Therefore, 15 by 1 ^ "08 transistor P2 is turned on, unnecessary leakage current does not flow from the input and output terminal BUS to the power supply voltage, and unnecessary leakage current can be prevented from flowing into the input and output terminal BUS. Also, since there is no Unnecessary leakage current, so the voltage level of the target plus voltage bus does not change, and can be maintained at a predetermined voltage level. 20 Also, in the input state, the PMOS transistor P2 is gated by the gate driver 8 The terminal G2 is set to the power supply voltage VDD (VG2 = VDD), and is maintained in a non-conducting state when the voltage is less than the voltage of the power supply voltage VDD plus the threshold voltage Vthp. In addition, the voltage is higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp At this time, the gate terminal G2 is set to apply a voltage VBUS and the dimension 29 1240993 is kept in a non-conducting state. In this case, an overvoltage is not applied to the gate driving section 8. Also, an unnecessary leakage current is not caused. The gate terminal g2 flows to the power supply voltage VDD through the gate driving section 8 and prevents unnecessary leakage current. In addition, since there is no unnecessary leakage current, the input-output 5-terminal BUS can be set The predetermined voltage level. Because the voltage applied to the gate terminal G4 of the PMOS transistor P4 is limited to the voltage of the power supply voltage VDD or the step-down voltage vdDL minus the threshold voltage vthn of the NMOS transistor N5, the voltage is less than When the source voltage VDD is added to the threshold voltage VthP2, the PMOS transistor 10 P4 can be reliably turned on, and the gate terminal ㈤ of the pM0s transistor p2 can be set to the power supply voltage VDD. The present invention is not limited. In the aforementioned implementation mode, various improvements and changes can be made without departing from the scope of the present invention. Industrial Applicability 15 According to the present invention, even if a voltage signal higher than its own power supply voltage is applied to the output terminal In the case of input or output terminals, unnecessary leakage current does not flow through the terminals. Therefore, when an external circuit is connected to the output terminal or input / output terminal, the voltage level applied to the wheel out terminal or the wheel in and output terminal can be ignored, and The voltage level of the terminal voltage can be set correctly, and the signal output or input and output to the terminal BUS can be performed stably. 30 1240993 [Schematic Brief description] Figure 1 shows the circuit diagram of the semiconductor device of the first implementation type. Figure 2 shows the circuit diagram of the first specific example of the n-well voltage control circuit. 5 Figure 3 shows the The circuit diagram of the second specific example. The fourth diagram is a circuit diagram showing the third specific example of the n-well voltage control circuit. The fifth diagram is the characteristic of the gate voltage (VG4) of the PMOS transistor P4 in the implementation mode. Characteristic diagram. Fig. 6 is a characteristic diagram showing the characteristics of the voltage at the gate terminal 10 (VG2) of the PMOS transistor P2 in the implementation mode. Fig. 7 is a circuit diagram showing the semiconductor device of the second implementation mode. FIG. 8 is a circuit diagram showing a level conversion circuit. Fig. 9 is an explanatory diagram showing a first operating state in the implementation mode. 15 Fig. 10 is an explanatory diagram showing the second operating state in the implementation form. FIG. 11 is a circuit diagram showing a conventional semiconductor device. FIG. 12 is an explanatory diagram showing the first problem in the conventional technology. Fig. 13 is an explanatory diagram showing a second problem in the conventional technology. [Representative symbol table of the main components of the figure] 1,2,110 ·· I / O buffer circuit 6 .. 1st transmission gate 7... 2nd transmission gate 8 ··· gate driver 11 ... NAND gate 1240993 12, · .NOR gate 13, 13A ~ 13C, 130 ... N well voltage control circuit 14, 100 ... input buffer circuit 15 ... buffer circuit 16 ~ 18, 160 ... inverter gate 19 ~ 21 ... level conversion circuit 31 .. 1st voltage step-down section 32 .. 2nd voltage step-down section 100 ... drive circuit Buf ... buffer circuit BUS ... input / output terminal / busbar Circuit CNT ... I / O mode switching signal DIN ... Input data signal DOUT ... Output data signal EN ... Output enable signals G1 to G2, G4, G31A, G31B, G32C ... Gate IF ··· Interface circuit 11N ... Leakage current IN ... Input signals N1 ~ N7, N31A ~ N31C, N51 ~ N54 ... NMOS transistor NW ... N well 32 1240993 OUT ... Output signal P1 ~ P6, P31A ~ P31C, P32A ~ P32C, P33 A ~ P33C, P51 ~ P53, P100, ... PMOS transistors
Rup...外部提昇電阻 VBUS...施加電壓 VDD...電源電壓 VDDH...高電源電壓 VDDex … VG1〜VG2，VG4…閘極端子電壓 Vthn...NMOS電晶體之閾值電壓 Vthp...PMOS電晶體之閾值電壓 VX...輸出電壓 33Rup ... external boost resistor VBUS ... applied voltage VDD ... supply voltage VDDH ... high supply voltage VDDex ... VG1 ~ VG2, VG4 ... gate terminal voltage Vthn ... threshold voltage Vthp of NMOS transistor. .. PMOS transistor threshold voltage VX ... output voltage 33