TWI240859B - Error forwarding in an enhanced general input/output architecture and related methods - Google Patents

Abstract

A point-to-point interconnection and communication architecture, protocol and related methods is presented.

Description

1240859 发明 发明, description of invention (fabrication month, stress month, technical field, prior art, content, implementation, and drawings of the invention briefly explain the priority w This application explicitly proposes a 60 / No. 3,708, entitled "A speedy point-to-point interconnection and communication framework, agreement, and related priority claims. This provisional application was filed by Ajancmc and others in 2001. The application was filed on August 26, 2011, and is attributed to the assignee of this application. Technical Example _ The invention is generally related to the general input-output bus structure, and it is more clear that the invention is a Γ% speed point-to-point The interconnections are related to communication architectures, protocols, and related methods. BACKGROUND OF THE INVENTION Computer equipment, such as computer systems, servers, network switches and routers, wireless communication devices, and the like are generally composed of different components. Components typically include a processor, microcontroller or other control logic, a memory system, input and output interfaces, and the like. To help this For communication between components, computer equipment has long relied on a general-purpose input-output (GIO) bus so that different components of the computer system can be connected to each other to support the myriad applications provided by such equipment. This type of traditional GI Ο One of the most common types in the bus architecture may be the interconnection of peripheral components, or the PCI bus architecture. This pc 〖bus standard (peripheral components interconnect (pc I) issued on December 18, 1998, local bus) Revised manual 2 · 2) Define a multi-station connection in parallel for connecting chips, expansion boards, and processor / memory subsystems in a computer device in any form 1240859 Bus architecture. The content of this PCI local bus standard has been explicitly incorporated by reference and used in this article. Although traditional PCI bus implementations have a data flow of 1 3 3 megabits per second (ie every 3 3 MHz 32 bits), but the PCI 2.2 standard allows each pin connected in parallel to reach 64 bits per 133 MHz, resulting in a theoretical data flow of just over 1 billion bits per second. In this regard, the data traffic provided by this traditional multi-drop PCI bus architecture has so far provided sufficient bandwidth to cope with even the most advanced computer equipment (such as micro processor servers, networks Equipment, etc.) internal communication needs. However, the increase in processing power at the current processing speed exceeding the 1 GHz threshold, combined with the extensive scheduling of multi-frequency Internet access, has enabled traditional GIOs such as the PCI bus architecture. Architecture becomes a bottleneck in this kind of computer equipment. Another limitation related to traditional GIO architecture is that it is generally not suitable for operating / processing isochronous (or time-dependent) data strings. One happens to be such isochronous data An example of a string is a multimedia data string, which requires an isochronous transmission device to ensure that the data is consumed as quickly as it receives the data, and that the audio portion and the video portion are synchronized. Traditional GIO architectures process data asynchronously, or at random intervals as bandwidth allows. Asynchronous processing of such isochronous data can lead to inaccurate audio and video, and as a result, specific providers of isochronous multimedia have the habit of processing specific data in priority order on other data, such as on video data Handle audio data in order of priority, so that at least the last user receives a fairly stable audio signal string (that is, not interrupted), so that they can enjoy songs that have been passed, understand stories, and so on. 1240859 Talk about it? Continued (3) Brief description of the drawings The present invention is illustrated by examples, but not necessarily limited to additional drawings in which similar elements reference the same reference numerals. FIG. 1 is a block diagram of an electronic device as described in the present invention. The electronic device includes one or more aspects of the present invention to facilitate communication between one or more components including the device. A schematic illustration of an exemplary communication stack of an exemplary embodiment of the invention. One or more components of the electronic device use the exemplary communication stack to facilitate communication between such components. FIG. 3 is a description of the present invention. Illustrative illustration of an example transaction descriptor; FIG. 4 is a schematic illustration of an exemplary communication link including one or more inter-component communication facilitating electronic devices according to an aspect of the present invention Figure 5 is a block diagram of an exemplary communication medium according to an exemplary embodiment of the present invention, which implements one or more aspects of the present invention; Figure 6 is a transaction layer of the present invention A block diagram of various packet header formats used in FIG. 7 is an example memory for implementing one or more viewpoints of the present invention according to an exemplary embodiment of the present invention. Block diagram of the architecture; FIG. 8 is a state diagram of an example link state mechanical diagram according to an aspect of the present invention; and FIG. 9 is a diagram containing one or 1240859 implementation of the present invention when accessed by an electronic device. Say Marriage Continuation Page (4) A block diagram of an accessible medium for more perspective content. DETAILED DESCRIPTION The present invention is generally described as an innovative point-to-point interconnection architecture, communication protocol and related methods, providing a scalable / extensible general input / output (I / O) communication platform for use in an electronic device. In this regard, an innovative enhanced general input-output (EGIO) interconnect architecture and related EGIO communication protocols are introduced. According to an exemplary embodiment, different elements of an EGIO architecture include one or more of a host bridge, a switch, or an endpoint, each of which includes at least one set of EGIO features to support this. EGIO communication between class components. By using an innovative EGIO communication protocol that uses a series of communication channels to perform communication between EGIO devices of this type, the innovative EGIO communication protocol supports one or more innovative features as described in more detail below. Including (but not limited to) virtual communication channels, tail end application error pre-transmissions, supported P CI application devices, multiple request response types, flow control and / or data integration management functions. According to an aspect of the present invention, this communication protocol is supported in each component of a computer device having a EGIO communication protocol stack, which includes a physical layer, a data link layer, and a transaction layer. In accordance with an alternative implementation, a communication medium containing an EGIO actuator including at least one set of the above features is cited. It will be apparent from the later discussion that the legacy components of an electronic device can appropriately use this communication medium to connect to other non-EGIO interconnect architectures that allow the protocol requirements of the present invention to be invoked. Familiarize yourself with the above and subsequent instructions 1240859

The artist should understand that one or more of the elements of the present invention may be suitably included in hardware, software, a transmitted signal, or a combination thereof. All descriptions of `` one embodiment '' or `` an embodiment '' in this specification indicate that a particular feature, structure, or characteristic described with this embodiment is included in at least one embodiment of the present invention. Therefore, The terms "one embodiment" or "pi-embodiment" appearing in different places in this specification are not necessarily related to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Special Terms Before delving into the details of the innovative EGIO interconnect architecture and communication protocol, it is helpful to introduce the components of the vocabulary that will be used in this detailed description: • Notification: Use the content of EGIO process control to refer to the use of this EGIO One of the agreements is a receiver of process control update information to transmit information about the validity of its process control credits; • completer • a logical device addressed by a request; • completer identification (ID): —of the completer A combination of one or more of a bus identifier (such as a number), a device identifier, and a functional identifier that uniquely identifies the finisher for this requirement; • complete: use one for termination, or part Terminate a sequence of packet references as a completion. According to an example implementation, one meets a previous requirement, and in some cases the completion includes data; • Configuration space: one of the four address spaces within the EGIO architecture. A device is installed using a packet with a configuration space address; • Component: a physical device (that is, located in a single package); -10- 1240859 (6) Posting _ achievement page • Data link layer: located at the transaction layer The middle layer of the EGIO architecture between (upper) and the physical layer (lower); • DLLP: Data link layer packet is a packet generated in the data link layer to support the link management function; • Drop string: refer to the relevant position of a component , Or the flow of information leaving the host bridge; • Endpoint: an EGIO device with a 00h-type configuration space file header; • Flow control: One is used to pass receive buffer information from a receiver to a transmitter to prevent Receive buffer overflows and transmitter promises that allow orderly rules; • Process Control Packet (FCP): —Used to transfer process control information from the transaction layer in one component to a transaction in a transaction layer in another component Layer Packet (TLP); • Function: A unique part of a multifunction device is identified by a unique function identifier (eg, a function number) in the configuration space; • Layer: Fixed EGIO architecture implemented in this I / O connection structure to each other. The feature of a layer is a single host bridge that matches the connection of the closest counting device (such as the host CPU); • Hierarchical area: Use a host bridge that obtains more than one EGIO interface to divide an EGIO layer into multiple partitions Among them, this type of partition is referred to as a first-level area; • Host bridge: connects a host CPU complex to one or more EGIO links; • 10 space: one of the four address spaces of this EGIO architecture ; 1240859 _ (η \ I Send code description continued page • Line: A set of physically connected differential signal pairs, one pair for transmission and one pair for reception. N interfaces at a time are composed of N lines; Link: a pair of simplex communication paths between two components; a collection of two ports (one transmit and one receive) and their interconnected lines; • logical bus: devices with the same number of buses in the configuration space One of the logical connections in the collection; • logical device: an EGIO-based component that responds to a unique device identifier in the configuration space; • memory space: the four address blanks of this EGIO structure One of them: • Information: a packet with an information space type; • Information space: one of the four address spaces of this EGIO architecture. It includes a special cycle as defined in the PCI as a collection of information spaces Therefore, provide an interface with a legacy device; • Legacy software model: A software model of a legacy device must be initialized, discovered, installed, and used (for example, a PCI software model in a legacy bridge machine such as EGIO to help interact with legacy devices Inclusions); 0 • physical layer: a layer of the EGIO architecture that directly interfaces with the communication medium between two components; • port: an interface that combines a component and is located between the component and an EGIO link_ p;- Cao • Receiver: The element that receives packet information through a link is the receiver / (sometimes a reference is a target); • Requirement: A packet used to start a sequence is referred to as a request. A request includes some opcodes , And sometimes include address and length, information -12-1240859 ⑻ I tweet _continued page or other information; • Requester: introduce a sequence into this EGIO for the first time A logical device in a domain; • requirement identification (ID): uniquely identifies one or more of a bus identifier (such as a bus number), a device identifier, and a function identifier of one of the requestors In most cases, an EGIO bridge or switch will pass a request from one interface to another without modifying the requester identification. In addition to an EGIO bus, When a bridge establishes a completion for the request, the requester identification should generally be stored for use; • Sequence: a single request and zero or more completions related to a single logical conversion performed by a requester; • sequence identification (ID):-The claimant identifies a combination with one or more of a tag, where the combination uniquely identifies the request and completion as part of a common sequence; • Separation transaction: one contains an initial A single logical transformation of transactions (separation requirements), where this token (completer or bridge) initiates one or more transactions (separation completion) ), It terminates with a separate response to transmit the read data (if it is readable) or a completion message to the requester; • Symbol: Generates a 10-bit quantity as 8-bit / The result of a 10-bit encoding; • Symbol time: the time period required to place a symbol on a line; • Mark: a number assigned to a known sequence by the requester to identify a part of the sequence Differentiate it in other sequences (ID); -13-1240859

• Transaction layer packet: TLP is a packet generated in the transaction layer to transmit a request or completion; • Transaction layer: The outermost (topmost) layer of this EGIO architecture, which operates on transactions (such as reading, writing Etc.); • Transaction Descriptor: a component of a packet header that describes the characteristics of a transaction in addition to its address, length, and type; and an example electronic device. A block diagram of a simplified electronic device 100 that includes one of the enhanced general input-output (EGIO) bus architectures, protocols, and related methods. According to the example shown in FIG. 1, it is depicted that the electronic device 100 includes one or more of the processor 102, a host bridge 104, a switch 108 and an endpoint 110, each connected together as shown. According to the description of the present invention, at least the host bridge 104, the switch 108, and the endpoint 1 10 have one or more of an EGIO communication interface 106. Examples are to help one or more of the present invention or More points. "As mentioned," each element 102, 104, 108 and 110 is communicatively connected to at least one other element via a communication link 1 12 through the EGIO interface 106 to support one or more EGIO communication channels. As mentioned above, the electronic device 100 is intended to represent various traditional and non-traditional computer systems, servers, network switches, network routers, wireless communication user units, wireless communication phone construction components, personal digital assistance, fixed The top box, or one or more of any electrical devices, can benefit from the communication resources introduced through the EGIO interconnect architecture, communication protocols, or related methods described herein. According to the example described in FIG. 1, the electronic device 100 has one or more processors 142- 1240859 (i0) Ig. As used herein, the processor 2 controls one or more aspects of the functionality of this electronic device 100. In this regard, the processor 102 typically represents any control logic including, but not limited to, a microprocessor, a programmable logic device (PLD), a programmable logic array (PLA), an application One or more of a special integrated circuit (ASIC), a microcontroller, and the like. The host bridge 104 provides a communication interface between the processor 102 and / or a processor / memory complex and one or more other elements 108, 110 of the EGIO architecture of the electronic device. Language is also the foundation of this egio architecture hierarchy. As used herein, a host bridge 104 refers to a logical entity of an EGIO hierarchy, which is closest to a host controller, a memory controller hub, a I 0 control hub, or any of the above. A combination, or some combination of chipset / CPU components (ie, located in a computer system environment). In this regard, although it is described as a single unit as shown in FIG. 1, the host bridge 104 can be appropriately regarded as a single logical entity that can appropriately have multiple physical elements. According to the example implementation shown in FIG. 1, the host bridge 104 is placed together with one or more EGIO interfaces 106 to facilitate communication with other peripheral devices, such as switches 丨 〇8, endpoints 1 10, and Clearly stated legacy bridges 1 i 4 or 1 丨 6. According to an implementation ', each EGIO interface 106 represents a different EGIO hierarchy area. In this regard, the implementation described in FIG. 1 represents a host bridge 104 having three (3) hierarchical areas. It should be noted that although described as containing multiple separated EGIO interfaces 106, it is expected that a single interface 106 having multiple ports may provide alternate implementations of communication with multiple devices. -15-1240859

According to the description of the present invention, the switch 108 has at least one upper port (that is, points to the bridge bridge 104) and at least one lower port. According to a real bar, —,, and D, a switch 1 0 8 identifies the host bridge closest to this host as the upper serial port, and all other ports are a bee of the lower serial port (that is, a port of an interface or interface i 〇6 itself). According to an implementation, the switch 108 appears to be configuration software (such as legacy configuration software) as a PCI-to-PCI bridge, as well as using PCI to capture and set up for routing transactions. In the content of the switch 108, the transactions that the receiving port and the transmitting port of the same counterparty are used as the transmitting port are defined. According to an implementation, the switch 108 supports all types of routing of the transaction layer packet (TLP) except for a locked transaction sequence between any port and other ports. In this regard, all broadcast messages should generally be routed from the receiving port to all other ports on switch 108. Generally, transaction layer packets that cannot be routed to a port should be terminated as TLPs not supported by switch 108. Unless it needs to be modified to comply with a different protocol that requires a transmission port (for example, combined with a transmission bridge of a legacy bridge 114, 116), the switch:-generally does not switch the transaction layer packet (TLP) from the receiving port to the transmission bee Some modifications. It should be understood that the switch 108 represents other devices, and in this regard, the type and type of traffic is not known in advance. According to an implementation which will be described in detail below, the process control and data integration viewpoint of the present invention is performed according to a link 'rather than end-to-end. Therefore, according to this type of implementation :: Add a switch 108 to the agreement on process control and data integration. In order to add a flow control 'switch 108, a separate flow control is maintained for each rod to improve the performance of this switch 108. Similarly, by following the detailed description of -16-1240859, the performance page (12) uses the TLP error detection device to input each TLP of this switch. Switch 108 supports data integration based on a link basis. deal with. According to one implementation, the lower serial port of a switch 108 is allowed to form a new EGIO hierarchy area. Next, referring to FIG. 1, an end point 1 1 0 is defined as any device having a type hexadecimal (0h) configuration space head. The endpoint device 110 may be a requestor or an EGI0 semantic transaction completer, either on its own behalf or on behalf of another non-EGI0 device. Examples of such endpoints 1 10 include (but are not limited to) EGI0 compliant graphics devices, EGIO compliant memory controllers, and / or implementations between EGI0 and some such as a universal continuous bus (USB), Ethernet , A device connected to one of the other interfaces similar to it. Unlike a legacy bridge 114, 116, which will be described in more detail below, as an endpoint for non-EGI0 compliant devices 1 1 0 may not be able to properly provide complete software for such non-EGI0 compliant devices. Although a device connected to a host processor complex 102 to an EGI0 architecture is considered as a host bridge 104, it may happen to be the same device type as other endpoints 1 1 0, this endpoint 1 1 0 is It is set in the EGI0 architecture which can be recognized only by the position of its associated processor complex 102. According to the description of the present invention, the endpoint 110 can be merged into one or more of the three types, (1) legacy and EGI0 promise endpoints, (2) legacy endpoints, and (3) EGI0 promise endpoints. Points, each of which has different rules operating in the EGI0 architecture. As mentioned above, the EGI0 promised endpoint 1 1 0 is identified from the legacy endpoints (eg, 118, 120), of which an EGIO endpoint 1 1 0 will have a type 0 0 h configuration space 1240859

The file is the time required for the request and is set to the body bridge containing the support medium, and the configuration requirements for a complete configuration. This type of endpoint is allowed to generate configuration requirements and can be classified as a reserved endpoint or as an EGIO-approved endpoint, but this kind of separation can be appropriately adhered to the following additional rules. Allow legacy endpoints (such as Π 8, 12 0) as a completer, support I 0 requirements ′ and allow 10 requirements to be generated. If its legacy software support has two requirements, the legacy endpoints (118, 120) are allowed to be used as a finisher to generate A2, ‘beijing semantics. The retention point does not generally issue a * locking request.

The EGIO promised endpoint 110 is generally not used as a finisher to support the peasant farmer and does not generate 10 requests. The EGIO endpoint no does not support a locked request as a completer, and does not act as a requestor to generate a locked request.

The EGIO-to-legacy bridges 114, 116 define endpoints i 10, which include important software support with legacy devices (118, 120), such as full software support, which interfaces to this EGIO architecture. In this regard, a legacy connector 114, 116 generally has an upper serial port (but there can be many), and it includes many lower serial ports (but it can also have only one). Follow the locking requirements of this legacy software model. The upper serial ports of a legacy bridge 114, 116 should be linked according to the application to support process control, and support the process control and data integration rules of the EGIO architecture. This will be explained in more detail below. As used herein, the purpose of link 1 12 is to represent any type of communication medium, including (but not limited to) copper wires, optical wires, wireless communication channels, infrared communication links, and the like. According to an example implementation, the EGIO link n 2 is a serial line of different pairs, and each pair supports transmitting and receiving communication, so as to provide support for full duplex communication function. Gen -18-1240859 Announcement (continued) (14) According to implementation, this link provides a scaled continuous time frequency with an initial (base) operating frequency of 2.5 GHz. The interface width in each direction can be scaled from xl, x2, x4, x8, xl2, xl6, x32 physical lines. As mentioned above and described in more detail below, the EGIO link 1 1 2 can appropriately support multiple virtual channels between devices, thereby providing access to using one or more virtual channels, such as one channel for audio and one channel for Video, non-disruptive communication support for isochronous traffic between such devices. Example EGI0 Interface Architecture FIG. 2 is a diagram illustrating an example EGI0 interface 106 architecture used by one or more components of an electronic device to facilitate communication between such components in accordance with an exemplary embodiment of the present invention. Implemented according to the example described in FIG. 2, the EGI0 interface 106 can be appropriately represented as a communication protocol stack including a transaction layer 202, a data link layer 204, and a physical layer 208. As shown, it is explained that the physical link layer interface includes a logical sub-block 210 and a physical sub-block, and as shown, each part thereof will be explained in more detail below.

Transaction Layer According to the description of the present invention, the transaction layer 202 provides an interface between the EGI0 architecture and a device core. In this regard, one of the primary responsibilities of transaction layer 202 is to gather and disassemble packets (ie, transaction layer packets or TLPs) for one or more logical devices within a host device (or medium). Address space, transaction layer type, and use Transaction forms the basis for information transfer between an initial medium and a target medium. According to an example embodiment, four address 2 rooms are defined in the innovative EGI0 architecture, which include, for example, a configuration address space, a memory address space-19-1240859 The input / output address space and two information addresses each have their own specific uses. The memory space (706) transaction includes one or more of a read request and a write request to convert data to or from a corresponding location of a memory. Memory space transactions can use two different address forms, such as a short address form (such as a 32-bit address) or a long address form (such as a 64-bit long). According to an example embodiment, the EGIO architecture uses a lock protocol semantics (i.e., one of the media can be properly locked to access the modified memory space) to provide traditional read, modify, and embed sequences. More specifically, support for down-locking is allowed in accordance with specific device rules (bridges, switches, endpoints, legacy bridges). As mentioned above, this type of lock semantics is supported in the support of demobilized devices. The 10-space (7 04) transaction is used to access the input and output corresponding memory registers in a 10-address space (for example, a 16-bit 100-bit address space). For example, Intel-specific processor 102 and other processor-based settings include n 10-space definitions. Therefore, a 10 space transaction includes a read request and a nesting request to convert data to or from a 10 corresponding address. The configuration space (702) transaction is a configuration space for accessing this EGI0 device. Transactions for this configuration space include read requirements and write requirements. Traditional processors like this generally do not include an original configuration space, which corresponds to a device compatible with traditional PCI configuration space access device software (for example, using a CFC / CFC8 PCI configuration device 1). Alternatively, a memory distortion device may be used appropriately to access the configuration space. 1240859

Faimao_continued Defines the information space (708) transaction (or only information) to support in-band communication between EGIO media through the interface 106. Since the traditional processor does not include support for the original information space, it can be started through the EGIO medium between the EGIO interfaces 106. According to an example implementation, traditional "sideband" signals such as interruption and power management requirements are implemented as information to reduce the number of pins required to support such legacy signals. Some processors and PCI buses contain the concept of "special cycles", which also correspond to the information in the EGIO interface 106. According to an embodiment, the information is generally divided into two types: standard information and sales restriction information. _ According to the illustrated exemplary embodiment, the standard information includes a general purpose information group and a system management information group. The general purpose information can be a single target message or a broadcast / multicast message. The system management information group may be appropriately composed of one or more of interrupt control information, power management information, sequence control primitives, and error signals, and examples thereof will be described below. In accordance with an example, the general purpose information includes information for support of locked transactions. It is implemented in accordance with this example, which describes an unlocked message. Φ Among the switches (such as 108), the unlocked message should be transmitted through any port participating in a locked transaction. Endpoint devices (such as 110, 118, 120) that receive an unlocked message while unlocked will ignore this message. Otherwise, the locked device will be unlocked according to the receipt of an unlocked message. Following an example, the system management information group contains special information for ordering. &Quot; columns and synchronizing information. This type of information is a protection message used to apply strict ordering rules to transactions generated using components that receive the EGIO architecture. According to a practice, this kind of protection information can only use the selected sub-set of network -21-1240859 G7) components, such as endpoints, responses. In addition to the foregoing, information that represents a correctable error, an uncorrectable error, and an irreparable error is also considered in this article, such as through the use of a tail error preamble. According to an aspect of the present invention, as described above, the system management information group provides the use of the information in the frequency band to signal the interruption. According to an implementation, the ASSERT_INTx / DEASSERT_INTx information is passed in, and the positive interrupt information is transmitted to the processor complex through the host bridge 104. Following the illustrated example, the usage rules for the ASSERT_INTx / DEASSERT_INTx information pair reflect the ASSERTJNTx / DEASSERTJNTx information for the PCI INTx # signal found in the PCI specification above. From any device, each transmission of ASSERTJNTx should generally have a corresponding transmission of DEASSERT_INTx. For a specific "X " (A, B, C or D), a transmission of DEASSERT_INTx should generally have an ASSERT_IN.Tx transmission. The switch should generally route ASSERTJNTx / DEASSERT_INTx information to the host bridge 104, where the host bridge Generally, the ASSERT_INTx / DEASSERT_INTx information should be tracked to generate virtual interrupt signals and correspond to these signals to the system interrupt sources. In addition to the general purpose and system management information groups, the EGIO architecture also establishes a standard architecture in which the core logic (such as the chipset) Vendors can define vendor-specific information that fits their specific operational requirements for their platform. This architecture is established through a common information header, where the code defining the vendor-specific information is defined as "reserved" Transaction Descriptor-Transaction Descriptor is a device used to transfer transaction information from the starting point to the point of service and back. It provides an extensible device for providing a 1240859 _ nR, I code. Continued pages provided The general interconnection of new types of emerging applications. In this regard, this transaction descriptor supports The combination of the identification of transactions within the system, the modification of the order of internal value transactions, and the transactions with virtual channels using a virtual channel ID device. A schematic description of a transaction descriptor is related to Figure 3. Please turn to Figure 3, which is in accordance with the present invention The description describes a graphical illustration of a telegram containing an example transaction descriptor. According to the description of the present invention, the description contains a global identifier field 3 0 2, an attribute field 3 06 and a virtual channel identifier field 3 0 6 transaction descriptor 3 00. In the example implementation described, this is a global identifier field 3 0 2 containing a local transaction identifier field 3 0 8 and a source identifier field 3 1 0. • Global transaction identification 302 As used herein, the global transaction identifier is unique to all major requirements. Implemented according to the example described in Figure 3, this global transaction identifier 3 0 2 is composed of two sub-fields: local transaction identification Symbol field 3 0 8 and a source identifier field 3 1 0. According to an implementation, this local transaction identifier field 3 0 8 is an octet field generated by each requester, and a request is completed for the requester. all of Significant requirements are unique. This source identifier uniquely identifies an EGIO medium with an EGIO hierarchy. Therefore, this local transaction identifier field provides a global identification and source ID of a transaction within a hierarchical region. According to an implementation, this local transaction identification The character 3 0 8 allows a request / completion from a single source of a request to be reversible in order to be processed (the order rules are explained in more detail below). For example, a source of a read request can generate reads A1 and A2. The target medium serving these read requests is first returned with one completed as the request A2 transaction ID, and second with one completed as -23-1240859 (19) A 1. In the completed packet header, local transaction ID information will be traded. This type of device requires special attention to support for such out-of-order read completion because devices that allow it to be obtained in a more efficient manner. The device that takes the request will ensure that it is used to complete it. As mentioned above, since the EGIO switch 108 is not an endpoint (that is, only a proper endpoint is passed), it does not need to reserve a buffer space. A single read request can result in many completions. Reachable completion of a single read request. It can be supported by the original migration that is partially completed in the header of the provided package (ie, the completion header). According to an example implementation, the source identifier field 3 1 0 contains a value that is unique to each logical EGIO device. EGIO devices can include multiple logic devices as appropriate. Score from system penetration to standard P CI bus alignment lift. This kind of bus number information is generated by EGIO internally and independently, using information and instructions such as a device number and a rate internally available EGIO device when accessing the device in the initial configuration. The configuration cycle is similar to the one generated during the device used by the PCI configuration. As for the latest switching devices, such devices will need to re-record the bus number information on this bit cycle access to begin to be transparent to SHPC. According to the implementation of one of the EGIO architectures, a physical component can be sent and touched to turn pages. The redundant processing and reading are important. Please assume that reads are issued before allocation. If the request is complete, return the information about the 16-bit address flattened by the completion of the integration. Note a single system configuration with the number of bus IDs that can be assigned the number of source IDs. According to a real-time use of one phase, the latest connection and the wearing of the body stack appropriately include -24-1240859 (20) Invention [譌. 明 Continued page One or more logic devices (or media). Each logical device is assigned to conform to a configuration cycle aligned with its specific number of devices, that is, the concept of the number of devices is combined in this logical device. According to one implementation, up to sixteen logic devices are allowed within a single physical element. Each of these logic devices may suitably contain one or more string actuators, e.g., up to a few tens of six. Therefore, a single solid element may suitably include up to 256 string actuators. Transactions marked by different source identifiers belong to the EGIO input / output (10) source, so the ideas that can be arranged in order are processed completely independently of each other. As for three-party, equal-to-equivalent transactions, if necessary, a protection order control primitive can be used to force the order. As used herein, the global descriptor field 3 of the transaction descriptor 300 supports at least one set of the following rules: (a) Marking each required requirement with a global transaction ID (GTID) (B)-Generally, a unique GTID should be assigned to each major mandatory requirement initiated by a medium; (c) Non-mandatory requirements do not use this GTID's local transaction ID field 3 0 8 and The local transaction ID field is deemed to be reserved; (d) The target does not modify the requirement GTID under any circumstances, and only repeats it in the header of all completed one completed packets related to this requirement, where the initial The router uses this GTID to match this completion to the original requirements. • Attribute Field 304 As used in this article, Attribute Field 304 describes the characteristics and relationships of the transaction. -25-1240859 Invention _ Continue to Buy (21). In this regard, this property field 304 is used to provide additional information that allows modification of the fixed value processing within the transaction. These changes apply to different perspectives on transaction processing within this system, such as hardware continuity management (such as reconnaissance attributes) and priorities. An example form of this attribute field 3 0 4 is represented by the secondary fields 3 1 2 to 3 1 8. As shown, the attribute field 3 0 4 includes a priority sub-field 3 1 2. An initiator can be used to modify this priority subfield to assign a priority to a transaction. In an example implementation, for example, the type or quality of the service characteristics of a transaction or a medium can be combined in this priority order field 3 1 2 to influence the processing of other system components. The reserved attribute fields 3 1 4 are reserved for future, or restricted use. This reserved attribute field can be used to implement a possible use model of priority or confidentiality attributes. The use order attribute field 3 1 6 provides any information that conveys the type of order that can modify the default order rules in the same order plane (where this order plane contains Traffic initiated by the host processor (102) and 10 devices with their corresponding source IDs). According to an example implementation, an order attribute of "0" indicates an applicable default value order rule, and an order attribute of "1 π" indicates an arbitrary order, in which writes can be passed in the same direction and read The writing can be passed in the same direction. The device using the random order semantics is mainly used to remove the data and transactions with a predetermined value order for reading / writing status information. Use the reconnaissance attribute field 3 1 8 to provide transmission can be modified The fast buffer storage area of the internal value fast buffer storage area in the same order plane. The fast buffer storage area is -26-1240859. Faton said that the page (22) contains any information about the type of consistency management. One of the sequence planes contains information processed by a host. Device 102 initial traffic and I0 with its corresponding source ID. According to an example implementation, the value of a "reconnaissance attribute field 3 1 8 conforms to a predetermined value of the rapid buffer storage area continuity management structure, in which transactions are under investigation for implementation Hardware-level fast buffer storage coherence. On the other hand, a value "1" in the reconnaissance attribute field 3 1 8 terminates the coherent management structure of the fast buffer storage area of the preset value, and does not reconnaissance transactions. More precisely, the data being accessed is either non-storage or its consistency is managed by software. • Virtual channel ID field 306 As used herein, the virtual channel ID field 306 identifies a separate virtual channel associated with a transaction. According to an embodiment, the virtual channel identifier (VCID) is a four-bit field that allows identification of up to sixteen virtual channels (VCs) based on a pre-transaction. An example of the definition of VC ID is provided in the following Table I: VCID VC name usage model 0000 Internal value channel General purpose traffic 0001 Isochronous channel This channel is used to transport 10 traffic, which has the following requirements: (a) Do not detect 10 traffic To allow limited service timing; and (b) use an X / T contract to control the quality of the service (where X = data volume and τ = time) 0010-1111 reserved future use form I: virtual channel ID code -27 -1240859 fasang_continued (23) Virtual Channels According to one aspect of the present invention, the transaction layer 202 of the EGIO interface 106 can establish one or more virtual channels within the bandwidth of the communication link 112. The virtual channel (VC) view of the present invention described above is used to define an independent and logical communication interface within a single physical EGIO link 1 12. In this regard, the use of independent VC corresponding traffic can benefit from different processing procedures and service prioritization. As an example, a service requiring a limited quality of service can correspond to an isochronous (time-dependent) virtual channel in terms of the amount of X of data that has been converted during the T period of time. Transactions corresponding to different virtual channels may not have any order requirements related to each other. That is, the virtual channel operation is an independent logical interface with different flow control rules and attributes. Regarding the initial traffic by the host processor 102, the virtual channel can be controlled in the required order according to the default order device rules, or the traffic can be completely processed in the reverse order. According to an example, V C includes the following two types of traffic: General purpose 10 traffic and isochronous traffic. That is, according to this example, two types of virtual channels are described: (1) general purpose 10 virtual channels, and (2) isochronous virtual channels. As used herein, the transaction layer 202 maintains independent flow control for each of the one or more channels actively supported by the component. As used herein, all EGIO-compliant elements should generally support general 10 types of virtual channels, such as virtual channel 0, where there is no required order relationship between different virtual channels of this type. By default, VC 0 is used for general purpose 10 traffic, while VC 1 is allocated to handle isochronous traffic. In alternate -28- 1240859 instructions (continued) (24) In practice, any virtual channel can be assigned to handle isochronous traffic. Description 1 Description of the EGIO concept in Figure 4 with multiple, independent and manageable virtual channels.

Please turn to FIG. 4, according to one aspect of the present invention, a diagrammatic illustration of an example EGIO link 1 1 2 containing multiple virtual channels (VC). According to the illustrated example of FIG. 4, an EGIO link 1 1 2 including multiple virtual channels 402 and 404 established between the EGIO interface 106 is described. In accordance with an example, the virtual channel 4 0 2 is explained by traffic from multiple sources 4 6 A to N and at least by its source ID. As mentioned, the virtual channel 402 is established without the ordering requirements between transactions from different sources (such as media, interfaces, etc.). Similarly, a description is given of a virtual channel 404 containing multiple transactions 408 A to N from multiple sources, where each transaction is represented by at least one source ID. According to the example described, transactions from source ID 0 406 A are strongly ordered, otherwise they are modified by the property of the transaction header 埽 3 04, while transactions from source 408N do not describe such order rules.

Order of transactions Although it is easier to force all responses to be processed in order, the transaction layer 202 tries to take advantage of allowing transactions to be reordered to improve results. To simplify this reordering, the transaction layer 202 will "sign" the transactions. That is, according to an embodiment, the transaction layer 202 adds a transaction descriptor to each packet, so that the components in the EGIO architecture can optimize (for example, by reordering) its transmission time without losing the original processing packets. Tracking of related orders. This type of transaction descriptor is used to simplify the routing of requests and complete packets through this EGIO interface hierarchy. -29- 1240859 mmmm (25) Therefore, the innovative view of this EG]: 0 interconnect architecture and communication protocol is that it provides up-to-the-order communication in order to increase data traffic by reducing idling or waiting states. In this regard, the transaction layer 202 uses a set of rules to define the sequence requirements for EGIO transactions. Define transaction order requirements to ensure correct operation in software. The soft system is designed to support the manufacturer and consumer order models, while allowing the application's transaction processing flexibility to be improved based on different order models (such as any order used to illustrate additional applications). . The following describes the order requirements for two different types of models, a single order surface model and a multi-way order surface model. • A basic transaction order-a single "sequence plane" model assumes that two components are connected through an EGIO architecture similar to the EGIO architecture of Figure 1: a memory interface for a host processor and a memory subsystem A hub, and a 10-control hub that provides an interface to a 100-time system. Both hubs contain internal queues that handle inbound and outbound traffic, and all 10 traffic in this simple model correspond to a single "order plane". (Note that the transaction descriptor source ID information provides a Unique identification is used for each medium in an EGIO hierarchy. Please note that the 10 traffic corresponding to this source ID can transmit different transaction order attributes.) Define the order used for this system configuration between the 10 initial traffic and the host's initial traffic. Rules. From this point on, the host processor corresponding to a source ID of perspective 10 traffic and initial traffic represents traffic implemented in a single "sequence plane." The following provides an example of such a transaction sequence rule for Form II. The rules defined in this form are applicable to all transaction types in the EGIO system that contain memory, 10, configuration, and 1240859 hairpin_continued (26) information. In the form Π below, the columns represent two The first 'column' in the transaction represents the second. The table items indicate the order relationship between the two transactions. The table items are defined as follows: • Yes-generally should Allow the second transaction to pass the first transaction to avoid pauses. (In the event of a blockade, the second transaction is required to pass the first. Generally, fairness should be understood to avoid scarcity.) • Yes / No-No requirement. A transaction can freely pass over or be blocked by a second transaction. Lu • No-Generally, a second transaction should not be allowed to pass the first transaction. This is to maintain the same order. Columns crossed columns? WR-Req (No need to complete) (Column 2) RD_Req (Column 3) WR_Req (Requires completion) (Column 4) RD_Comp. (Column 5) WR_Comp. (襕 6) WR_Req No need to complete (Column A) No Yes a. No b. Yes Yes / No Yes / No RD_Req (Column B) No a. No b. Yes / No Yes / No Yes / No Yes / No WR_Req (Requires %%) (Column C) No Yes / No C. No d. Yes / No Yes / No Yes / No RD a Comp. (Column D) No Yes a. No b. Yes / No Yes / No WR_Comp. (Column E) Yes / No Yes Yes Yes / No Yes / No Form II: Use Order of transactions and avoidance of pauses on a single order-31-1240859 (27) _tab_page 歹》 J: 襕 ID Form II Item Description A2 A published memory write request (WR_R £ Q)-generally not Other published memory write requests. A3 should generally allow a published memory write request to bypass read requests to avoid stalls. A4 a.—Generally, a published memory wr_req should not be allowed to exceed a need. Complete the attribute memory WR_REQ. B. Generally, a published memory wr_req should be allowed to exceed 10 and configuration requirements to avoid stalls. A5, A6 do not require a published memory WR-REQ to complete. In order to allow this flexibility while still guaranteeing the pause release operation, the EGIO protocol provides a medium for acceptance of the guarantee completion. B2, C2 These requirements cannot go beyond a published memory-stomach, so as to maintain the consistent writing order of the manufacturer / consumer model. B3 a • In a basic implementation (ie, out of order processing), reading is not allowed to cross each other. b. In an alternate execution, read requests are allowed to cross each other. Transaction identification is necessary for such functions. B4, C3 Different types of requirements block or pass each other. B5, B6, C5, C6 allow blocking of these requests or completion. D2 means that the fetch is not allowed to pass through a published memory (to maintain constant nesting time). D3, D4, E3, E4-Complete the rush at noon to complete the non-publishing request to avoid pauses. D5 a • In a basic implementation, read completion is not allowed to pass over each other; b-j ·-in alternate execution, read completion is allowed to pass over each other. In addition, the need for consistent transaction identification can be accommodated. E6 allows these completions to cross each other. It is important to maintain tracking transactions using, for example, a transaction ID device. D6, E5 ^^ Kings can cross each other. E2 The published memory WJ ^ REQ blocks the completion of writing or allows writing ^ to pass the published memory WR_REQ. This type of write transaction is actually moving, so there is no order relationship. Table: Transaction Times Description 1240859 (28) Zhai Ma Ming Ming Continued • Advanced Transaction Order-The previous part of the multi-faceted "transaction order model" defines the order rules within a single "order face". As mentioned above, the EGIO interconnect structure And communication protocols use a unique transaction descriptor device to correlate additional information with a transaction to support more complex order relationships. The fields within the transaction descriptor allow the creation of multi-way "sequence planes", which are a sequence of 100 traffic Are independent of each other. Each "order plane" is composed of queue / buffer logic that conforms to a particular 10 devices (specified by a unique source ID) and queue / buffer logic of the host processor that transmits the initial traffic. Generally only these two Define the order within this "face." The rules supporting the manufacturer / consumer usage model and the prevention of pauses defined in the previous section are implemented for each of the 'order planes' independent of the other 'order planes 11'. By way of example, the read completion required for the initial request by the "face" N may be sufficient to allocate the read completion required for the initial request by the "face" M. However, the read completion for the face N and the read completion for the face The reading completion of Μ is not enough to allocate the initial published memory from the host. Although the use of the corresponding device surface allows for multiple sequential surfaces, some or all of the sequential surfaces can be " removed " together to simplify this Implementation (that is, combining a number of independently controlled buffers / FIFOs into a single entity). When all faces are disassembled together, the transaction descriptor source ID device is only used to help route transactions, not to relax the 10-traffic independent string. Order. In addition to the foregoing, this transaction description device provides modification of a default order within a single order plane using an order attribute. Therefore, it can control the order modification based on the advance transaction. Transaction layer agreement packet form -33 · 1240859 ( 29) As explained above, this innovative EGIO architecture uses a packet-based protocol to change the information between the transaction layers of two communicating devices. This EGI0 rack General support memory, 1〇, configuration information and transaction type. General requirements or complete packet to pass this type of transaction, in which only complete packets on demand, data that is sent back or received approval of a transaction.

With reference to Figure 6, a diagrammatic illustration of an exemplary transaction layer agreement is described in accordance with the description of the present invention. The TLP header 600 including a form field, a type field, an extended type / extended length (ET / EL) field, and a length field is implemented in accordance with the illustrative example of FIG. 6. Please note that some TLPs contain information behind the slot headers as determined by the formal venue in the building header. None of T L p should contain more than the limit set by MAX_PAYLOAD_SIZE. According to an example, the T L P data is a naturally arranged four-bit double-byte (DW) incremented by one four-bit. As used herein, according to the following definitions, the form (FMT) field describes the form of TLP ...

• 000-2DW file header, no data • 001-3DW file header, no data • 0 10-4DW file header, no data • 10 1-3DW file header, with data • 1 10-4DW file header, with data • Reserved All other encoding TYPE fields are used to indicate the type encoding used within this TLP. According to the implementation, the format [2: 0] and type [3: 0] should be decoded to determine the TLP format. According to the first implementation, the value in the class split [3: 0] is used to determine whether to use the extension -34. 1240859 Faimao_continued (30) Type / Extended Length Field to extend the type field or length field. ^ / Team fields are generally only used to extend length fields with memory type read requirements.

The length field provides an indication of the length of the payload, also in increments of DW: 0000 0000-1DW 0000 0001 = 2DW

111 1 1 1 1 1 = 256DW A summary of at least one sub-set of an example TLP transaction type. The corresponding header format and a description are provided in Table IV below: TLP type FMT [2: 0] type [3: 0] Extension type [1: 0] Description Initial process control information (FCP) 000 0000 00 Initial process control information Update process control information (FCP) 000 0001 00 Update process control information Memory read request (MRd) 001 010 1001 E19E18 Memory Read request for extended type of length [9: 8] / extended length field memory read request-locked (MRdLK) 001 010 1011 00 memory read request-locked memory write request-published ( MWR) 101 110 0001 00 Memory Write Request · Published 10 Read Request (IORd) 001 1010 00 10 Read Request 10 Write Request (IOWr) 101 1010 00 10 Write Request Configure Read Type 0 (CfgRdO) 001 1010 01 Configuration read type 0 Configuration write type 0 (CfgWrO) 101 1010 01 Configuration write type 0 Configuration read type l (CfgRdl) 001 1010 11 Configuration read type 1 Configuration write type 1 (CfgWrl) [01 1010 11 Configuration write type 1 1240859

mmmm

Information Request (Msg) 010 011s2 slsO Information Request-The secondary field s [2: 0] describes the information of a group. According to an implementation, this information field is decoded to determine whether it contains a specific period of information required to complete a request (MsgD) 110 011s2 slsO Information request with data-the secondary field s [2: 0] specifies a group of information. According to the implementation, this information field is decoded to determine that it contains the information request (MsgCR) that needs to be completed if a specific cycle is required. 010 llls2 slsO The data request that needs to be completed-the secondary field s [2: 0] describes a group of information. According to one implementation, this information field is decoded to determine a specific period. Information requirement (MsgDCR) with data completion 110 llls2 slsO Information requirement with data completion-secondary field s [2: 0] describes a group of information. According to an implementation, determine this specific cycle field to determine the completion of a specific week without data (CPL) 001 0100 00 without data completion-in addition to successful completion, used for 10 and configuration write completion, some information completion, and with completion The memory of the state is taken to be completed. Completion with data (CplD) 101 0100 00 Completion with data-for memory, 10, and configuration read completion, and some information completion. Completion for locked memory reads (CplDLk) 101 001 01 For locked memory reads-otherwise like CplD

Attachment A provides additional details on requirements and completion, and its description is hereby incorporated by reference. Process Control One of the limitations generally associated with traditional process control structures is that it counteracts the problems that should occur, rather than reducing the chance of such problems occurring proactively in the first place. For example, in a conventional PCI system, a transmitter will transmit information to a receiver before it receives a message that suspends or terminates transmission until further notice. This type of request can then occur after a request to start retransmitting a packet at a known point in the transmission. Those skilled in the art should understand that this reaction method creates wasteful cycles and is inefficient in this regard. To cope with this limitation, the transaction layer 202 of the EGIO interface 106 includes a procedural control device that reduces the chance of excessive states occurring in advance, and also provides a pre-connection sequence rule for the virtual channel established between the initiator and the finisher. support. According to an aspect of the present invention, a concept of flow control "credit" is cited, in which a receiver shares information about (a) the size of the buffer (within the credit), and (b) having a One of the various virtual channels established between the transmitter and receiver (that is, a fully virtual channel) is the currently available buffer space of the transmitter. This enables the transaction layer 202 of the transmitter to maintain an estimate of the available buffer space (such as available credits) allocated to the transmission through the identified virtual channel, and if it decides that the transmission will cause an excess in the receiving buffer In the state, it can adjust its transmission through each virtual channel in advance. According to an aspect of the present invention, the transaction layer 202 refers to process control to prevent an excess of receiver buffers and conforms to the sequence rules described above. According to an implementation, the flow control device of this transaction layer 202 is used by a requester to track the queues or buffer spaces available in a medium accessing the EGIO link 1 12. As used herein, flow control does not imply that a requirement has reached its final finisher. (37) According to the description of the present invention, the flow control is orthogonal to the data integration device for performing reliable information exchange between a transmitter and a receiver. This means that, because the data integration device guarantees retransmission to correct erroneous and lost packets, the flow control can consider the flow of transaction layer packet (T L P) information from receiver to transmitter as perfect. As used herein, this process control includes virtual channels of EGIO links 1 1 2. In this regard 'will be reflected in the process control credit (FCC) notified by a receiver for each virtual channel supported by this receiver. © According to the description of the present invention, flow control is performed by the transaction layer 2 0 2 in cooperation with the data link layer 2 0 4. To easily describe the description of this flow control device, the following types of packet information are distinguished: (a) Published Request Header (PRH) (b) Published Request Information (PRD) (c) Unpublished Request File Head (NPRH) (d) Non-published request data (NPRD) (e) Read, write and information completion file header (CPLH) φ (f) Read and information completion data (CPLD) The unit of measurement within the EGIO implementation of sexual process control is a process control credit (FCC). According to an implementation, a process control letter is used for 16 bytes of data. Regarding the file header, the \ unit of process control credit is a file header. As mentioned above, each virtual channel has independent process control. For each virtual channel, different identifiers are maintained for the aforementioned types of packet information (as shown in (a)-(f) above) as compared to tracking credits. According to the example described, the packet transmission is performed according to the following consumption process control letter -38-1240859? _ Continued (34) Use:-Memory / 10 Configuration read requirements: 1 NPRH unit-Memory write Entry requirements: 1 PRH + nPRD units (where η is the size of the data payload, for example, the length of the data divided by the size of the process control unit (such as 16 bytes))

-10 / Configuration writing requirements: 1 NPRH + 1 NPRD-Information requirements: at least 1 PRH and / or 1 NPRH unit according to the information-Complete with data: 1 CPLH + N CPLD unit (where η is the size of the data divided Control the data unit size by process, for example, 16 bytes)

-Complete without data: 1 CPLH For each type of tracked information, there are three concept registers, each of which is eight bits wide to monitor the used credit (in the transmitter), (in the transmitter) Credit limit and a credit allocated (in the receiver). This credit consumption register contains the total count of process control unit modules 2 5 6 consumed from the beginning. After the initial setting, all credit consumption registers are set to zero (0) and incremented as the transaction layer passes information to the data link layer. The size of the increment is related to the amount of credit consumed by the information delivered. According to an implementation, when the maximum total is reached or exceeded (for example, all ones), the counter is rotated to zero. According to an implementation, this counter is maintained using an unsigned 8-bit module. The credit limit register contains a limit on the maximum number of process control units that can be consumed. After the interface is initialized, the register is set to all zeros, and set to the value indicated in (aforesaid) a process control update message regarding information reception. 1240859 〇5) Description Sheet The credit allocation register maintains the total count of credits granted to the conveyor from the beginning. This count is initially set based on the buffer size and receiver allocation method. This value may be appropriately included in the process control update information. This value is incremented when the receiver transaction layer removes processed information from its receive buffer. The size of the increment is related to the amount of free space. According to one embodiment, the receiver should normally initially set the credit assigned to the value equal to or greater than the following values: -PRH: 1 Process Control Unit (FCU); # -PRD ·· FCU equals the maximum possible size of the device's maximum payload size set up;

-NPRH: 1 FCU-NPRD: FCU is equal to the maximum possible setting of the maximum payload size of the device,-Switching device-CPLH: 1 FCU;-Switching device-CPLD: FCU is the maximum possible setting of the maximum payload size of the device, or The maximum reading φ requirement that this device will always generate, whichever is smaller;-root &amp; endpoint device-CPLH or CPLD: 255 FCU (all 1's), considered by the transmitter as an infinite value, It is therefore never adjusted. · In accordance with this practice, a receiver generally does not set a credit allocation register value larger than 127 FCUs for any credit type. According to an alternate implementation, instead of maintaining a credit allocation register using the above counter method, a transmitter can dynamically calculate credit allocation according to the following equation: -40-1240859 (36) C_A2 (the most recently received credit unit for transmission) Number) ~ (Available Receive Buffer Space) As mentioned above, a transmitter implements this concept register (credit use, credit limit) for each virtual channel that the transmitter will use. Similarly, the receiver implements this concept register (credit allocation) for each virtual channel supported by this receiver. In order to prevent the transmission of excessive information if the transmission of information would result in excessive receiving buffers, if the credit consumption count plus the number of credit units related to the information to be transmitted is less than or equal to the credit limit value, a transmitter is allowed to transmit one Type of information. When a transmitter receives process control information indicating the completion (CPL) of non-infinite credits (ie, <255 FCUs), the transmitter will complete the adjustment based on the available credits. Explain that when credit is used and returned, information from different transactions is not mixed in one credit. Similarly, when explaining the use and return of credit, the header and data information from a transaction is never mixed within a credit. Therefore, when locking some packets from the transmission due to lack of process control credits, the transmitter will follow the ordering rules when deciding which packet types should be allowed to be passed &apos; delay &quot; packets. The return of a transaction's process control credit cannot be interpreted as the completion of the transaction or the realization of system visibility. The use of a memory write requires a semantic information signal interrupt (MSI) as another memory write. If a subsequent F C update (from the receiver) indicates a credit limit value below the originally indicated value, the transmitter shall take into account this new lower limit and may appropriately provide a notification error. According to the flow control device described in this article, if a receiver receives more information than its allocated credit (exceeding the allocated credit), the receiver will instruct a receiver to make an excessive error to the transmitter that is responsible for this, and cause this Excessive packets 1240859 issued _ description continued page 〇 7) The packet is a data link level retry request. • Flow Control Packet (FCP) According to an implementation, communication between devices using Flow Control Packet (FCP) must maintain the flow control information of the register. According to one embodiment, the process control packet includes two DW header forms and transmits information for a specific virtual channel about six credit registers maintained by process control logic for the receiving transaction layer of each VC. According to the description of the present invention, there are two types of F C P: initial F C P and updated F C P, as illustrated in FIG. 6. As mentioned above, an initial FCP 602 is issued after the initial transaction layer. After the initialisation of the transaction layer, the information in the register is updated using update FCP 604. The reception of an initial F C P during normal operation may result in the reset of the local flow control device and the transmission of an initial F C P. The content of an initial F CP includes at least one sub-set of notified credits for each PRH, PRD, NPRH, NPRD, CPH, CPD, and channel ID (such as a virtual channel to which F C information applies). The updated F C P form is similar to the original F C P form. Please note that although the F C header does not include the length field sharing other transaction layer packet header format, but because there is no additional D W data related to this packet, the packet size is clear. Error Preamble Unlike traditional error preamble devices, the EGIO architecture relies on tail information, which is attached to a data telegram identified as incomplete for some of the reasons explained below. According to an example implementation, the transaction layer 202 uses one of several known error detection techniques, such as cyclic residual detection (CRC) error control and the like. -42-1240859 (38) Like 懿. 晒. Continued According to an implementation, in order to promote the feature of false forward, the EGIO architecture uses a "tail", which is attached to the TLP that transmits known bad data. An example of a situation where a tail error forward may be used: Example # 1: A read from main memory encountered an uncorrected ECC error Example # 2 ·· — The same error on PCI is written to main memory Example # 3 : — Data integration error in internal data buffer or cache area. According to an example implementation, error forwarding is only used to read completed data or write data. That is, when an error occurs in the management fee related to the data telegram, such as an error in a file header (such as a request phase, address / command, etc.), the error forward is generally not used. As used in this article, because it is not possible to clearly identify a real target, it is generally impossible to forward the request or completion with a header. Therefore, this type of error forward may appropriately cause a direct or side effect, such as data errors, system Failed etc. According to one embodiment, the error preamble is used to propagate the error of the system diagnosis through the system. Error The front link does not use the data link layer to retry, so only the EGIO link 1 1 2 determined by the TLP error detection device (such as cyclic residual detection (CRC), etc.) will have a trailing TLP termination when a transmission error occurs. Therefore, this tail will eventually cause the requesting initiator to reissue it (at the transaction level above) or take some other action. As used herein, all EGIO receivers (such as those set in the EGIO interface 106) can handle T L P termination with a tail. Support for adding a tail to a transmitter is optional (and therefore compatible with detention). Switch 108 routes one tail with one remaining T L P. Host Bridge 104 with equivalent -43-1240859 send-results (39) routing support will generally route the trailing one with the remaining TLP, but this is not required. An error preamble is generally applied to a write request (published or unpublished) or to a completed read. T L P that the transmitter knows to include bad data should end with this tail. According to an example, a tail is composed of two DWs, where byte [7: 5] is all zeros (for example, 0 0 0), and bit [4: 1] is all one (for example, 1111), and all other bits are reserved. An EGIO receiver will consider all data in a TLP terminated by a tail error. If an incorrect preamble is applied, the receiver will cause all data from the indicated TLP to be marked as bad ("toxic &quot;). Within the transaction layer, an analyzer will generally analyze to the end of the entire TLP and immediately detect it later Data link layer 204 As mentioned above, the data link layer 204 of FIG. 2 is used as an intermediate layer between the transaction layer 202 and the physical layer 206. This data link layer The main responsibility of 2 0 4 is to provide a reliable device for exchanging transaction layer packets (TLP) between two components on an EGIO link 1 12. The transmission plane of the data link layer 204 accepts the TLP combined by the transaction layer 202, Implement a packet sequence identifier (such as an identification number), calculate and implement an error detection code (such as a C RC code), and select or for one of the virtual channels established within the bandwidth of the EGIO link 112 More transmissions have been submitted to modify the TLP to the physical layer 206. The receiving data link layer 204 is responsible for detecting the integration of the received TLP (such as using a CRC device, etc.) and is responsible for presenting the integrated TLP that is detected as positive to the transaction layer 2 0 4 Disassembly before the front pass to the device core. 1240859 发 吗 quad_continued (40) Services provided by the data link layer 2 0 4 generally include data exchange, error detection and retry, initial and power management services, and data link Communication services at each layer. Each service series provided in each of the aforementioned categories is listed below. Data exchange services-receiving TLPs from the transmission transaction layer for transmission-receiving TLPs from the physical layer through the link and transmitting them to the receiving transaction layer for error detection Test & Retry TLP Sequence J J number and CRC generation-Transmitted TLP storage for data link layer retry-Data integration test

-Approval signal and retry DLLP-Error indication for error reporting and recording device-Link approval signal suspension timer initial and power management service φ-Track link status and send active / reset / cut status to transaction layer data link Layer mutual communication service-for link management functions including error detection and retry_-switching between data link layers of two directly connected components \-not exposed to the transaction layer_ as used in the EGIO interface 106, The data link layer 204 is shown as a conduit to the transaction layer 202 with various latent information. All information put into transmitting the link layer will be displayed later on the output of the receiving data link layer -45-1240859 Say _Continue to buy (41). This latency will depend on a number of factors, including the latency of the catheter delivery, the width and operating frequency of the connection, the transmission of communication signals through the medium, and the delay caused by the retry of the data link layer. Due to these delays, the transmitting data link layer can use backward pressure to transmit the transaction layer 202, and the receiving data link layer passes valid or missing valid information to the receiving transaction layer 202. According to an implementation, the data link layer 204 tracks the EGIO link 1 1 2 status. In this regard, the DLL 204 communicates the connection status with the transaction 202 and the entity layer 206, and performs connection management through the entity layer 206. According to an implementation, the data link layer includes a link control and management state machine to perform such management tasks. The status of this machine is described as follows: Example DLL link status: • Link Down (LD)-The physical layer reports that the link is non-operational or the port is not connected. Initialization • Link Active (LA)-standard operation mode • Link ActDefer (LAD)-standard operation is interrupted, and the entity layer attempts to restart the corresponding management rules for each state (refer to Figure 8): The initial state after resetting. After retrying to LD:-Reset all data link layer status information to the default value at -46-1240859 Is it explained on the next page (42) During LD:-Do not include TLP information with transactions or entities Layer exchange • Do not exchange DLLP information with the physical layer-do not generate or accept DLLPs. If you leave to LI:

-Instructions from the transaction layer show that the link is not incomplete by SW • Link Initialization (LI) At LI:-Do not exchange TLP information with the transaction or physical layer-Do not exchange DLLP information with the physical layer-Do not generate or Accept DLLPs If you leave to LA:-Instructions from the physical layer show that the link training is successful. If you leave to LD:-Instructions from the physical layer show. The link training fails. • Link active (LA) When link active:-Link the TLP information with Transaction and physical layer exchange-Exchange DLLP information with the physical layer-Generate and accept DLLPs If you leave the link ActDefer:-Instructions from the data link layer retry management device-47- 1240859 Posting instructions continued (43) Show request link Training, or if the physical layer reports retraining is in progress. • Link ActDefer (LAD) When linking ActDefer:-Do not exchange TLP information with the transaction or entity layer-Do not exchange DLLP information with the entity layer-Do not generate or accept DLLPs If you leave the link initiative:-Instructions from the entity layer are displayed Training has succeeded if left to link down:-Instructions from the physical layer indicate training failure. Data integration management. As used herein, data link layer packets (DLLPs) are used to support the EGIO link data integration architecture. In this regard, according to an implementation, the EGIO architecture provides the following DLLPs to support integrated management of linked data: • Approval signal DLLP: TLP sequence number approval signal _ used to indicate some number of successful TLP receptions • Negative approval signal DLLP: TLP Sequence Number Negative Approval Signal-Used to indicate a data link layer to retry • The acknowledgment signal suspends DLLP: Indicates the number of recently transmitted sequences-Used to detect some forms of TLP loss. The data link layer 204 is caused to cause the DLL 204 to apply the sequence number and cyclic residual detection (CRC) error 1240859 (44) to the TLP. According to an example implementation, the receiving data link layer uses the detected sequence number, C RC and any error indication from the receiving entity layer to validate the received TLP. In the case of an error in a TLP, the data link layer is retried for recovery. • CRC, sequence number, and retry management (transmitter) In terms of conceptual "counters," and "flags," the devices used to determine the TLPC RC and sequence number and support data link layer retry are described below: CRC and Sequence Number Rule (Transmitter) • Uses the following 8-bit counter: 〇TRANS_SEQ-Stores the number of sequences ready for transmission. • Set to all "0" in the link-down state. One increment • When at all 1 ”, the increment results in a repayment to all“ 0 ”• A negative DLLP reception causes the value to be set back to the sequence number indicated in the negative DLLP 0 ACKD_SEQ-Stores the most recently received link The sequence authorization signal is connected to the connection approval signal DLLP. • Set to all '' 1 · in the connection down state. • Allocate an 8-bit sequence number to each τ l P 〇 The counter TRANS_SEQ stores this number 〇 If TRANS —SEQ is equal to (ACKD—SEQ-1) modulo 256, and the transmitter should generally not transmit another TLP until an acknowledged signal DLLP updates ACKD_SEQ to cause the condition (TRANS_SEQ == ACKD-SEQ-1) modulo 256 is no longer true -49- 1240859 (45) Do I post a continuation page • Use TRANS-SEQ for TLP, use: 〇 wait for a single byte value to TLP in advance 〇 wait for a single reserved byte to TLP in advance • calculate 1 3 2-bit CRC for the TLP using the following algorithm and appended to the tail end of the TLP. The polynomial used is 0x04CllDB7-the same CRC-32 used by Ethernet. The procedure used for the calculation is: Call 1) The initial value of the CRC_32 count nose is to wait 24 in advance &quot; 〇 ',

DW formed by the sequence number 2) Use the D W from the byte 0 of the header to the last D W of this τ l P in order from the d W of τ L P in the transaction layer to continue the CRC calculation

3) Supplement the bit sequence from this calculation and the result is tlp CRC 4) CRC DW is appended to the tail end of this TLP • Generally, a copy of the transmitted TLP should be stored in the data link layer retry buffer__ When other devices receive an acknowledgement signal DLLP: 〇 Load ACKD_SEq with the value specified in this DLLP. 〇 Retry buffer eliminates TL p by the number of sequences in the range:. ACKD-SEQ + 1's previous Value w • New value to ACKD-SEQ • When a negative acknowledgement signal DLLp is received by other components on the link: 〇 If a TLP is currently being converted to the physical layer, will this conversion continue to -50-1240859? Is it continued? (46) Until the conversion of this TLP is completed. 〇 Do not remove the additional TLP from the transaction layer before completing the following steps. ○ Retry buffer to eliminate TLP by the number of sequences in the range. The values stated in the DLLP's Negative Acknowledgement Signal Sequence field. All remaining TLPs in the retry buffer are redisplayed to the physical layer for retransmission in the original order. Please note: This will include All TLPs of the sequence number: 〇 The value stated in the negative approval signal sequence number field of the negative approval signal DLLP + 1; TRANS "; the value of EQ-1 • If there is no TLP remaining in the retry buffer, this negative approval The signal DLLP is an error. According to the error tracking and recording items, the error negative acknowledgement signal DLLP should generally be recorded. The transmitter does not require further action. CRC and sequence number. J number (receiver). Same, conceptually In terms of "counters" and "flags", the devices used to detect the TLP CRC and the sequence number and support the data link layer retry are as follows: • Use the following 8-bit counters: oNEXT_RCV_SEQ-store expectations for the next TLP Preface, J number • Set to all “0” in the link-down state • Increment 1 for each TLP that has been accepted, or clear 1240859 by accepting a TLP. Explanation of performance page (47) When the DLLR_IN_PROGRESS flag (explained below) is loaded with a value (transmission sequence number + 1) each time, a connection layer DLLP is received and the DLLR_IN_PR〇GRESS flag is cleared. 〇If NEXT_RCV__SEQ A value different from the value specified by a received TLP or a loss of sequence number synchronization between the transmitter and receiver when a DLLP is suspended by an acknowledged signal; in this case: • If the DLLR_IN_PROGRESS flag is set, 〇 Reset DLLR_IN_PROGRESS Flag 〇 “Transfer bad DLLR DLLP” error to the error log / track by one of the signals. PLEASE NOTE: This indicates that a DLLR DLLP (negative approval signal) is transmitted in an incorrect manner. • If the DLLR_IN_PROGRESS flag is not set,

〇Set the DLLR_IN_PROGRESS flag and initially negate the approval signal DLLP 〇Please note that this instruction has lost a TLP Set to b'000 in the state. • For each negative acknowledgement signal issued by DLLP in increments of 1. • When the count reaches b'100: 〇 Link control state machine actively moves from link to Link ActDefer 〇 Then reset DLLRR COUNT to b '000 1240859 (48) Da Ming [諕 明 绩 页. If DLLRR_COUNT is not equal to b, 000, it will be determined by 1 every 256 symbol times. 0: Saturate at b'000. • Use the following flags:

oDLLR_IN_PROGRESS • The setting / clearing system is described as follows. • When setting DLLR_IN_PROGRESS, all received TLPs are removed (until the TLPs indicated by DLLR DLLP are received).

• When DLLRJN_PROGRESS is cleared, the received TLP is detected as described below. • For a TLP to be accepted, the following conditions should generally be true: 〇Received TLP sequence number 4 is equal to NEXT-RCV-SEQ 〇 Physical layer TLP has not been instructed to receive any errors. TLP CRC detection did not indicate an error. • When accepting a TLP: 〇 Forward the transaction layer portion of this TLP to the receiving transaction layer. 〇 If set, clear the DLLR_IN_PROGRESS flag. 〇 Increment NEXT_RCV_SEQ • Not When accepting a TLP:

〇 Set the DLLRJNJPROGRESS flag. 〇 Send a negative approval signal DLLP. • The approval signal / negative approval signal sequence number field should generally contain a value (NEXT_RCV_SEQ-1). • The negative approval hall number type (NT) field should generally indicate a negative approval signal 1240859. Reasons for saying _continued page (49): 〇b'00-Receiving error identified by the physical layer 〇b'01-TLP CRC detection failed 〇b'10-Sequence number error 〇b '11-Frame error identified by the physical layer • The receiver should generally not allow the transmission time from receiving the CRC for a TLP to the negative acknowledgement signal to exceed 1023 symbols, as measured from the component port. Please note: NEXT_RCV_SEQ is not incremented. • If receiving data If the link layer does not successfully receive a TLP exceeding a negative acknowledgement signal DLLP within the number of 5 1 2 times, the negative acknowledgement signal DLLP is repeated. 〇 If four TLPs are not received after four attempts, the receiver will: • Enter a link that links the Act Defer state and is initially retrained by the physical layer. Indicate the occurrence of a major error for error tracking and recording • Data link layer recognition signal DLLP-generally should be transmitted when the following conditions are true: Data link control and management state machine is in the link active state. TLP has been accepted, but Not yet approved by transmitting a recognition signal DLLP. 5 12 symbols or more have passed since the last recognition signal DLLP. • Data link layer recognition signal DLLP can be transmitted more frequently than required. • Data link layer recognition signal DLLP describes the recognition signal sequence. Values in several fields (NEXT_RCV_SEQ-1) • Recognition signal suspension device -54-1240859 Announcement _ Continued (50) Consider a case where a TLP is mistaken on link 1 12 and the receiver does not detect the presence of TLP. Since the number of T L P sequences will not match the expected number of sequences on the receiver, the lost T L P will be detected when transmitting a subsequent T L P. However, the transmission data link layer 204 cannot generally limit the time to be presented to the next T L P from T L P from the transmission transport layer. The acknowledge signal pause device allows the transmitter to limit the time required for the receiver to detect a lost TLP. Approval signal suspension device rules • If the transmission retry buffer contains a TLP that has not been acknowledged by the DLLP, and if no TLP or link DLLP is transmitted for more than 1024 symbol times, an acknowledgement signal should be used to suspend the DLLP. • After an acknowledgment signal suspends the transmission of DLLP, before receiving an acknowledgment signal DLLP from a component on the other side of the link, the data link layer generally does not pass any TLP to the physical layer for transmission.

〇 If the acknowledgement signal DLLP is not received within a period of more than 1023 symbols, the acknowledgement signal is transmitted again to suspend the DLLP-in the case that an acknowledgement signal DLLP is not received, there are four successful transmissions of an acknowledgement signal to suspend the DLLP. Times • Enter links that link ActDefer status and are initially retrained by the entity layer. • Indicate the occurrence of a major error to error tracking and logging. Physical layer 2 0 6 Please continue to refer to FIG. 2, which describes the physical layer 206. As used herein, this physical layer 206 insulates transaction 202 from data link layer 204 from the signaling technology used to link data exchange. According to the example illustrated in Figure 2, the real -55-1240859 (51) layer is divided into logical 208 and physical 2 10 functional sub-blocks. As used herein, the logical sub-block 208 is responsible for the "digital" functions of this physical layer 206. In this regard, the logical sub-block 208 has two main areas: a transmission section that is ready for output information transmitted by the physical sub-block 210, and a transmission of received information to the link layer 2. 4 Recognize and prepare the receiver part of this received message. The logical sub-block 208 and the physical sub-block 2 10 coordinate the port state and control the temporary crying interface through a state. The logical sub-block 208 directs the control and management functions of this physical layer 206. According to an example implementation, the EGI0 architecture uses an 8-bit / 1 ()-bit transmission code. With this structure, the characteristics of eight bits are three bits and four bits corresponding to a four-bit code group and a six-bit code group, respectively. This code group is chained to form a one-bit symbol. The 8-bit / 10-bit encoding structure used by the EGI0 architecture provides special symbols, which are different from the data symbols used to represent features. These special symbols are used for various connection management devices as follows. Special symbols are also used to design the ^ and TLp, and clear special symbols are used to allow the two types of packets to be distinguished quickly and easily. The physical sub-block 210 includes a transmitter and a receiver. This transmitter is provided by the logical sub-block 208, which is connected in series and transmitted to the link 2. Consecutive symbols from link 112 are provided to the receiver. It converts the received signal into a one-bit string, which is connected and supplied to the logical sub-block 208 together with a symbol clock recovered from the continuous input. It should be understood that, as used herein, the EGIO link 112 may appropriately represent any type of communication 1240859 (52). Instructions for continued pages include an electrical communication link, an optical communication link, an RF communication link, an Infrared communication link, a wireless communication link, and the like. In this regard, each of the transmitter and / or receiver including the physical sub-block 2 1 0 of the physical layer 2 06 is suitable for one or more of the above communication links. Example communication media

FIG. 5 is a block diagram illustrating an exemplary communication medium containing at least one set of features related to the present invention, implemented in accordance with an example of the present invention. According to the example illustrated in FIG. 5, the description of the communication medium 5 0 0 includes control logic 5 02, an EGIO communication initiator 504, a memory space 5 6 for data structure, and any one or more applications 5 0 8. As used herein, the control logic 502 provides a processing source to each of one or more of the EGIO communication actuators 504 to selectively implement one or more aspects of the present invention. In this regard, the control logic 502 is intended to represent a microprocessor, a microcontroller, a finite state device, a programmable logic device, a programmable gate array, or to implement control logic during execution as described above. One or more of the contents of a feature. Description The EGIO communication initiator 504 includes a transaction layer interface 202, a data link layer interface 204, and a physical layer including a logical sub-block 20 8 and a physical sub-block 210 to connect the communication medium 500 with an EGIO link 1 12 One or more of the interfaces 206. As used herein, the components of the EGIO communication actuator 504 perform functions similar to, but not identical to, those described above. According to the example illustrated in FIG. 5, the description of the communication medium 5 0 0 includes the data structure -57- 1240859 Faquan Ming continued (53) Structure 5 0 6. As described in more detail below with respect to FIG. 7, the data structure 506 may appropriately include a memory space, an IO space, a configuration space, and an information space used by the communication engine 504 to facilitate communication between electronic devices. . As used herein, the application 508 is used to represent any of the various applications that are selectively exercised by the communication engine 500, and is used to implement the EGIO communication protocol and related management functions. Example Data Structure Please turn to FIG. 7, which illustrates one or more data structures used by the EGIO interface 10 6 according to an implementation of the present invention. More specifically, regarding the example implementation illustrated in FIG. 7, four (4) address spaces are defined for use in the EGIO architecture: configuration space 7 1 0, I 0 space 7 2 0, memory space 7 3 0 and information Space 74 0. As shown, the configuration space 7 1 0 includes a first file 7 1 2, which defines a type of EGIO to which a host device (such as an endpoint, etc.) belongs. Each of these address spaces performs its individual function as described above. Alternative Embodiment FIG. 9 is a block diagram of a storage medium on which a plurality of commands have been stored, the commands including one or more of an EGIO interconnection structure and a communication protocol according to another embodiment of the present invention Order of opinion. In general, FIG. 9 depicts a mechanically accessible medium / device 900 having content stored thereon, which content includes the innovative EGIO interface that implements the present invention when executed by an accessing machine 10 At least one set of 6. As used herein, mechanically accessible medium 900 is used to represent any of these types of media known to those skilled in the art, such as volatile memory devices, non-volatile memory devices, magnetic storage Media, Optical Storage-58- 1240859 (54) Announcement of continuation pages, media, and similar signals. Similarly, executable commands are used to reflect any of many software languages known in the art, such as C ++, video programming language, Hypertext Markup Language (HTML), Java, Extensible Markup Language (XML) , And similar ones. In addition, it should be understood that the media 9 0 does not need to be set up with any host system. That is, the medium 900 can suitably exist in a communication connection to an execution system or a remote server accessible to the execution system. Therefore, since the alternate storage medium and software embodiments have been considered within the spirit and scope of the present invention, the software of FIG. 9 will be considered for illustrative purposes. Although the present invention has been described in the detailed description and the summary of the invention in language specific to the structural features and / or method steps, it should be understood that the invention within the scope of a patent application is not necessarily limited to the specific features or steps illustrated. Alas. Rather, the disclosure of this particular feature and step is merely an exemplary form of implementation of the proposed invention. However, it will be apparent that various modifications and changes can be made thereto without departing from the expanded spirit and scope of the present invention. Therefore, this manual and drawings should be regarded as illustrative and not restrictive. This description and abstract are not intended to complete or limit the invention to the stereotypes disclosed. The names used in the following patent applications should not be used to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the present invention should be completely determined by the following patent application scope, which will be explained in accordance with the construction principle of the patent application scope explanation. According to the foregoing, the following is the scope of patent application: -59-

Claims (1)

1240859 Pick up and apply for a special fan park 1. A method 'includes detecting an error in a data telegram received through a general-purpose input / output bus; using one to indicate that the data telegram is an incomplete tail to select a location Modify this data telegram; and forward the modified data telegram to its destination. 2. If the method of claim 1 is applied, the detecting an error includes: analyzing the error control content in the received data telegram to identify the error in the data telegram. 3. The method of claim 2 in the scope of patent application, wherein the error control content is the producer of a data telegram carrying a data payload. 4. The method of claim 1 in the patent application, wherein the selective modification includes: determining whether the detected error appears in a data payload or a file header of the data telegram; and if the error appears in the file A tail is not generated in the header for this information telegram. 5. The method of claim 1 in the patent application range, wherein the tail includes two double characters (DW), where bits [7: 5] are both zero (for example, 000) and bits [4: 1] Both are one. 6. If the method of applying for the first item of the patent scope includes: · receiving a data telegram; analyzing to the tail end of a data telegram to identify the tail information; and -60-1240859 defamation: special succession _ continued page. Any received data telegram with an additional tail is considered to contain error. 7. If the method of applying for the scope of patent application item 1, the previous transmission includes: identifying a destination identifier in the received data telegram; and transmitting the modified data telegram to the destination through the general input / output bus. 8. If the method of claim 7 is applied, the previous transmission includes: identifying a destination identifier in the received data telegram; and transmitting the modified data telegram to the destination of the communication connection. 9. A storage medium, including content, which, when executed by an access electronic device, gives the electronic device an enhanced general input / output (EGIO) interface to detect that the device passes a general input / output bus Receive an error in one of the data telegrams, use one to indicate that the data telegram is an incomplete tail to selectively modify the data telegram, and forward the modified data telegram to its destination. 10. If the storage medium of the scope of patent application item 9, the EGIO interface analyzes the error control content in the received data telegram to identify the error in the data telegram. 11. If the storage medium of the scope of patent application item 9, the EGIO interface determines whether the detected error appears in the data payload of one of the data telegrams or in a file header, and if this error appears in the file header However, a tail is not generated for this information telegram. 12. A device, including:-a general input / output bus; and -61-1240859 patent order _ Continued page Two or more components connected through this general input / output bus communication. At least one of them includes an interface that facilitates communication of components on the bus. This interface includes a transaction layer that detects errors in a data telegram received through a general input / output bus, and indicates whether the data telegram is right or wrong. Complete tail to selectively modify this data telegram and forward the modified data telegram to its destination. 13. For the device in the scope of patent application 12, the transaction layer analyzes the error control content in the received data telegram to identify the error in the data telegram. 14. For the device in the scope of patent application No. 13, wherein if the data telegram includes a data load, a transmitter from which the data telegram has been received generates error control content. 15. For a device in the scope of patent application 12, the transaction layer determines whether the detected error appears in a data payload or a file header of this data telegram, and if the error appears in the file header , A tail is not generated for this information telegram. -62-