TWI240361B - Method for fabricating a trench capacitor - Google Patents

Abstract

A method for making a deep trench capacitor is disclosed. A substrate with a deep trench formed therein is provided. The trench is doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower portion of the trench. A node dielectric is formed on interior surface of the trench. Subsequently, the trench is filled with a first conductive layer and then recessed to a first depth. A collar oxide layer is then formed on vertical sidewall of the trench on the first conductive layer. The trench is filled with a second conductive layer and again recessed to a second depth. A pair of symmetric spacers is then formed on the vertical sidewall of the trench. A third conductive layer is deposited on the second conductive layer and on the symmetric spacers, and fills the trench. The trench is recessed to a third depth.

Description

1240361 _ Case number 92125666_ 年月 日 __ V. Description of the invention (1) ^ The technical field to which the invention belongs. The invention relates to a semiconductor process, especially a dynamic random access memory (DRAM) Method for manufacturing trench capacitor. With the development of previous technologies toward the miniaturization of various electronic products, the design of DRAM components must also meet the requirements of high accumulation and high density, and the trench capacitor DRAM device structure is the high density DRAM architecture widely used in the industry First, it etches a deep trench in a semiconductor substrate and makes a trench capacitor in it, so it can effectively reduce the size of the memory cell and properly utilize the chip space. As known to those skilled in the art, the method of manufacturing the trench capacitor dynamic random access memory can be roughly summarized into the following main stages: _ 1 · deep trench etching; 2 · buried p 1 ate Fabrication and capacitor dielectric layer fabrication; 3 · Deep trench first polycrystalline silicon layer deposition and recess etch (rec ess etch); 4 · Neck oxide layer fabrication; ^ 5. Deep trench second polycrystalline silicon layer deposition and recess Etching; 6. wet etching of the neck oxide layer; 7. deep polysilicon layer 3 deep trench deposition and recess etching; and

Page 8 1240361 _ Case No. 92125666 _ Month and Day __ V. Description of the invention (2) 8. STI process. Please refer to Figure 1 and Figure 2. Figure 1 and Figure 2 show the conventional steps for making trench capacitors (before the STI process). As shown in FIG. 1, a substrate 10 is provided, on which a silicon oxide-lined layer 26 and a silicon nitride-lined layer 28 are deposited. The deep trench 11 is carved, the buried N + diffusion electrode (buriedp 1 ate) 1 3 and the capacitor dielectric layer 14 are produced, the first polycrystalline silicon layer of the deep trench is deposited and the recess is etched, the neck oxide layer 15 and deep After the second polycrystalline silicon layer of the trench is deposited and the recess is etched, as shown in FIG. 2, the neck oxide layer 15 not covered by the second polycrystalline silicon layer po 1 y 2 is removed by wet etching, and then a third step is performed. Polycrystalline silicon layer deposition and recess etching. The dopant diffuses through the third polycrystalline silicon layer P01 y3 to the substrate 10 surrounding the trench capacitor to form a ring-shaped doped outer diffusion region 16. Please refer to FIG. 3. FIG. 3 shows a semiconductor wafer after completing the steps in FIG. 2. Rear trench capacitor top view. As shown in FIG. 3, in order to allow the unit area of the chip to accommodate the most memory cells, a plurality of trench capacitor structures 11 are closely arranged, and in the substrate 10 around each trench capacitor structure 11, a ring doped Miscellaneous external diffusion area 1 6. Please refer to Figure 4 to Figure 6. Figure 4 shows the top view of the active area definition and the trench insulation area definition under ideal conditions when there is no misalignment after the photoresist layer defining the active area is formed on the wafer; FIG. 4 is a schematic view of the cross-sectional structure along the tangent line N-N ′ in FIG. 4; FIG. 6 is a schematic view of the cross-sectional structure along the tangent line N-N ′ after the STI process is completed in FIG. 4. Figure four and

Page 9 1240361 _Case No. 92125666_ Year and Month Amendment_ V. Description of the Invention (3) As shown in Figure 5, ideally, the photoresist (AA photoresist) that defines the active area and the depth formed in the substrate 10 There was no overlap between the trench capacitor structure 11 and the annular outer diffusion region 16 around the deep trench capacitor structure. As shown in Figure 5, A A photoresist is defined on a dielectric layer (generally B S G layer). Shallow trench insulation processes are well known to those in the industry. Generally, anisotropic dry etching processes are followed, such as reactive ion etching (reactive ion e tch i ng, RIE), to etch away areas not covered by AA photoresist. The STI trench is formed, and then a silicon-oxygen layer is filled, generally a high-density plasma chemical vapor deposition (HDPCVD) silicon-oxygen layer, and then a chemical mechanical polishing process is performed, using silicon nitride liner The layer 28 is a polishing stop layer and planarizes the surface of the wafer. Finally, the remaining silicon nitride-lined layer 28 and silicon oxide-lined layer 26 are removed to obtain the structure shown in Figure 6. The annular outer diffusion region 16 around the deep trench capacitor structure has been excavated during the ST I process. Therefore, in an ideal state, the annular outer diffusion region 16 around the deep trench capacitor structure will not affect the active region. Please refer to Figure 7 and Figure 8. Figure 7 is a top view of the active area definition and trench insulation area definition when the photoresist layer defining the active area is formed on the wafer. Schematic diagram of the cross-section structure along the tangent line N_N '(after completing the STI process). In the actual manufacturing process, misalignment often occurs between the AA photoresistor and the deep trench capacitor structure 11 as shown in Figure 7. 'AA photoresist is translated in the y direction in the figure', so that the AA photoresistor and the deep trench are electrically connected. The ring-shaped outer diffusion regions 16 surrounding the capacitor structure overlap. As shown in Figure 8, the ring-shaped outer diffusion region 16 around the deep trench capacitor structure affects the active area.

Page 10 1240361 _ Case No. 92125666_ Year Month Date _ Amendment V. Description of the Invention (4) Summary of the Invention According to this, the main purpose of the present invention is to provide a ring-shaped outer diffusion region around a deep trench capacitor structure to avoid affecting the active area. Deep trench capacitor process. According to a preferred embodiment of the present invention, a method for manufacturing a trench capacitor is disclosed, which includes the following steps: providing a substrate in which a deep trench is formed; doping the deep trench, forming a substrate in the bottom of the deep trench; Burying a diffusion electrode; forming a capacitive dielectric layer on the inner wall of the deep trench; depositing a first conductive layer in the deep trench; recessing the first polycrystalline silicon layer to a first depth in the deep trench; A neck oxide layer is formed on the side wall of the deep trench; a second conductive layer is deposited on the first conductive layer and the neck oxide layer in the deep trench; the second conductive layer is recessed and etched to a second depth in the deep trench; A symmetrical sidewall is formed on a side wall of the deep trench; a third conductive layer is deposited on the second conductive layer in the deep trench and a third conductive layer is deposited on the symmetrical sidewall; and the third conductive layer is recessed to etch the third conductive layer to a third depth. (\

I In order to make the content of the art more technical. Attached to the drawing and attached to the Mingming, the detailed explanation of the detailed steps, issued in the near 3 books can be entrusted to consult the reviewers

Page 11 1240361 Case No. 92125666 Θ_ Amendment 5. The description of the invention (5) is not intended to limit the present invention and the drawings are for reference and auxiliary explanation only. Implementation

Please refer to FIGS. 9 to 14. FIGS. 9 to 14 are schematic cross-sectional views showing a method for manufacturing a trench valley according to a preferred embodiment of the present invention. First, as shown in FIG. 9, a semiconductor substrate 10, such as a silicon substrate, is provided with a silicon nitride-lined layer 28 and a silicon oxide-lined layer 26 thereon. Next, the deep trench is etched, the buried N + diffusion electrode 13 (buried plate) 13 and the capacitor dielectric layer 14 are fabricated, the first polycrystalline silicon layer (ρ ο 1 y 1) of the deep trench is deposited, and the etching is performed. The oxide layer 15 is fabricated, and the second polycrystalline silicon layer (p0ly2) is deposited and etched in the bead trench. Among them, the method of forming the buried diffusion electrode may use doped arsenic silicate glass (ASG). The capacitor dielectric layer 14 may be a silicon oxide-silicon nitride (0xide-nitride, ON) dielectric layer or an oxide-nitride-oxide,

) Dielectric layer 'but is not limited thereto. After the second polycrystalline silicon layer of the deep trench is finished and the recess is left, the second polycrystalline silicon layer p0y2 and the neck oxide layer 15 form a recessed hole on the upper part of the deep trench capacitor. Next, on the surface of J in the depression, on the second polycrystalline silicon layer poly2 and the neck oxide layer 5 and on the surface of the lining nitride f layer 28, a thickness of about 0.001% is deposited by chemical vapor deposition. The CVD silicon oxide layer 31 is about 0 angstroms, preferably about 15 angstroms. Subsequently, an ammorphus silicon layer j 'is deposited on the Dshixi gas layer 31 to a thickness of about 50 angstroms. The top view of this deep trench capacitor is shown below Figure 9.

Page 12 1240361 _Case No. 92125666_ 年月 日 _iti_ V. Description of the Invention (6) 'As shown in Figure 10, then proceed with a tilt angle ion implantation process. In the direction of y in the figure, Dopants, such as BF2, are implanted in the amorphous silicon layer 32 on the inner wall of the recess. It should be noted that the oblique angle (ti 1 tang 1 e) ion implantation process only performs symmetrical ion implantation in the y direction in the figure, and the X direction does not perform oblique angle ion implantation, so that the amorphous silicon layer 3 2 No dopants are implanted in the X direction in the figure. As shown in FIG. 11, an anisotropic dry etching process is then performed to etch the amorphous silicon layer 32 and the CVD silicon layer on the silicon nitride-lined layer 28 and the second polycrystalline silicon layer ρ ο 1 y 2. The oxygen layer 31 makes the remaining amorphous silicon layer 32 and the CVD silicon oxide layer 31 remain on the sidewall of the recess. As shown in FIG. 12, a wet etching process is then performed to selectively remove the amorphous silicon layer 32 previously not implanted with BF2 by using a dilute ammonia solution, that is, the amorphous silicon in the X direction in the figure. Layer 32, so that the remaining amorphous silicon layer 32, that is, the amorphous silicon layer 32 in the y direction in the figure, forms an amorphous silicon symmetrical sidewall 33 for protecting the CVD silicon oxide layer 31. Subsequently, the diluted HF solution is used to remove the CVD silicon oxide layer 3 1 which is not covered by the amorphous silicon symmetrical sidewalls 33 to expose the substrate 10. At this time, the amorphous silicon symmetrical sidewall 3 3, the exposed substrate 10 and the second polycrystalline silicon layer form a notch 4 2 above the trench capacitor. As shown in FIG. 13, a third polycrystalline silicon layer po 1 y 3 is filled in the recess 4 2. As shown in FIG. 14, the third polycrystalline silicon layer is etched back

Page 13 1240361 _Case No. 92125666_Year Month and Day _ «_ V. Description of the Invention (7) ρ ο 1 y 3 and the amorphous silicon symmetrical sidewall 3 3 to a predetermined depth below the surface of the substrate 10. Please refer to FIG. 15, which shows a top view of the trench capacitor of the semiconductor wafer after completing the steps in FIG. 13. As shown in Fig. 15, in order to enable the chip unit area to accommodate the most memory cells, a plurality of trench capacitor structures 11 are arranged closely together. Since the present invention utilizes the amorphous silicon symmetrical sidewall 33 and the CVD silicon oxide layer 31 to block the path of dopant diffusion in the y direction in the figure through the third polycrystalline silicon layer ρ ο 1 y 3 to the substrate 10, the formed The outer diffusion region 16 around the deep trench capacitor structure is not ring-shaped, but only in the X direction in the figure, the dopant can diffuse through the area not covered by the CVD silicon oxide layer 31 to the substrate 10. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent of the present invention.

Page 14 1240361 _Case No. 92125666_Year Month and Day_Revised Schematic Description Schematic Description of Process ITS Travel x (v Steps of Rongqugou Manufacturing Knowledge Display 2 pictures and} In the second step of Burong Electric Ditch, the second picture is completed in the crystal guide half. The picture shows the third upper picture of the ditch in the trench, and the main zone of the moving zone of the optical zone of the fixed resistance zone in the rear layer. Master, righteousness is fixed. The love figure is quasi-visual, and the crystal pair is not meaningful. It is shown that the four-shaped edge diagram of the dominant region in the lower region is utterly cut. 1 The ST is completed. The four-four diagram is five. The figure of the six diagrams indicates that the line of the structure plane is cut along the back-end system. The quasi-direction of the structure plane is not right. The main domain of the righteousness is defined by the Qin r / shaped main ascending film into the crystal, as the last. The figure of the seven-shaped figure is cut along the middle of the seventh figure as • ο The figure of eight is the method of completing the construction plane. The example of making Rongqugou Shi Shijia shows forty more than Mingfa } In the later steps from Cheng Jiu to Cheng Jiu ’s drawing of the ditch, the thirty pictures are completed. • On the film. • Crystal. Guide. The half picture shows the five figures in the above figure. Formula

^ 1 Page 15 1240361 Case No. 92125666 Brief description of the revised version 10 Semiconductor substrate 11 Deep trench 13 Embedded N + diffusion electrode 14 Capacitive dielectric layer 15 Neck oxide layer 16 Doped outer diffusion region 26 Layer 28 silicon nitride layer 31 CVD silicon oxide layer 32 amorphous layer 33 symmetrical side wall 42 recess

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Claims (1)

1240361 _Case No. 92125666_ Amendment of the month of the year _ 6. Scope of patent application ^ 1. A method for manufacturing a trench capacitor includes: providing a substrate in which a deep trench is formed; doping the deep trench, below the deep trench A buried diffusion electrode is formed in the substrate; a capacitive dielectric layer is formed on the inner wall of the deep trench; a first conductive layer is deposited in the deep trench; the first polycrystalline silicon layer is recessed and etched into the deep trench A first depth; a neck oxide layer is formed on the side wall of the deep trench; a second conductive layer is deposited on the first conductive layer and the neck oxide layer in the deep trench; the second conductive layer is recessed to the deep trench Inner second depth; + forming a symmetrical sidewall on the deep trench; depositing a third conductive layer on the second conductive layer and the symmetrical sidewall in the deep trench; recessing the third conductive layer To a third depth in the deep trench; and diffusing dopants through the third conductive layer into the substrate not covered by the symmetrical sidewalls to form an outer diffusion doped region, thereby electrically connecting an opening Electrode power of crystals. 2. The method for manufacturing a trench capacitor as described in item 1 of the scope of patent application, wherein the method of forming a symmetrical sidewall on the sidewall of the deep trench includes the following steps: ® On the inner wall of the deep trench and the second conductive layer Depositing a thin dielectric layer on the layer; depositing a thin amorphous stone layer on the dielectric layer; Page 17 1240361 _Case No. 92125666_year month__ Sixth, the scope of the patent application is an oblique angle ion implantation, and a dopant is implanted in the thin amorphous silicon layer symmetrically on a part of the side wall of the deep trench; Etch back the thin amorphous silicon layer and the thin dielectric layer to expose the second conductive layer; selectively remove the thin amorphous silicon layer not implanted with ions; and remove the thin remaining silicon layer The thin dielectric layer covered by the amorphous stone layer exposes the substrate and forms the symmetrical sidewalls. 3. The method for manufacturing a trench capacitor according to item 2 of the scope of the patent application, wherein the oblique-angle ion implantation system is implanted into BF2. 414 The method for manufacturing a trench capacitor according to item 2 of the scope of the patent application, wherein the method for selectively removing the thin amorphous silicon layer not implanted with ions is wet etching using a dilute ammonia solution. 5. The method for manufacturing a trench capacitor as described in item 2 of the scope of the patent application, wherein the thin dielectric layer is a C V D stone oxide layer. 6. The method for manufacturing a trench capacitor according to item 2 of the scope of patent application, wherein the thickness of the thin dielectric layer is between 100 and 200 angstroms. 7. The method for manufacturing a trench capacitor as described in item 2 of the scope of the patent application, wherein the thickness of the thin amorphous silicon layer is about 50 angstroms. Page 18 1240361 Case No. 92125666 Amendment VI. Patent Application Scope 8. The method for manufacturing a trench capacitor as described in item 1 of the patent application scope, wherein the first conductive layer is made of polycrystalline silicon. 9. The method for manufacturing a trench capacitor according to item 1 of the scope of patent application, wherein the second conductive layer is made of polycrystalline silicon. 10. The method for manufacturing a trench capacitor as described in item 1 of the patent scope, wherein the third conductive layer is made of polycrystalline silicon. Page 19