1238488 九、發明說明： 【發明所屬之技術領域】 ^發明係有關於一種利用離子佈植製程以薄化電容表面 =二其應用於一動態隨機存取記憶體(D_之 【先前技術】 動態隨機麵記憶體（D卿ie RandQm Ae⑽Mem町，町摇 係以(咖ry cell)㈣容的帶電荷咖與）狀態來儲 Γ貧二也就疋"兒’電容所能儲存的電荷愈多（電容值愈大），則讀出放大 器在靖取資料㈣獅訊影響的情形（例如峰子所導致的軟錯記1238488 IX. Description of the invention: [Technical field to which the invention belongs] ^ The invention relates to a method of using an ion implantation process to thin the capacitor surface = two, which is applied to a dynamic random access memory (D_ of the [prior art] dynamic Random area memory (Dieie RandQm Ae⑽Mem, the town shakes in a charged cell with a capacity of ry cell) and stores Γ. The poorer it is, the more charge the capacitor can store. (The larger the capacitance value), the situation in which the sense amplifier is affected by the data acquisition (such as the soft misremembering caused by the peak)
Errors)等）將可大幅地降低。換言之，即電容值愈大，記憶體内所储 育料的穩定度就會愈高。 —f積體電路(integrated eireuit，1〇晶片上製作高積集度之半導體 元件寸必須考慮如何縮小母一個記憶單元(^挪。巧^ eg〗）的大小與電力消 耗，以使其操作速度加快。在傳統的平面電晶體設計中，為了獲得一個最 小尺寸之記憶單元，必須盡量將電晶體的閘極長度縮短，以減少記憶單元 的k向面積。但是，這會使閘極無法忍受過大的漏電流而必須相對應地降 低位兀線上的電壓，進而使得電容所儲存的電荷減少。所以，在縮短閘極 的橫向長度同時，還要考量如何製作一個具有較大電容量之電容，例如： 增加電容之面積、減少電容板之間的有效介質厚度等等。目前高密度記憶 體(例如：動態隨機存取記憶體，DRAM)係發展出兩種不同的電容形成技術， 其中一種為堆疊式電容，另一種為渠溝電容。其中，渠溝電容之製作係於 基底内形成一個渠溝，並於渠溝内製作電容儲存區，故不會佔用記憶單元 的額外面積。 而隨著動態隨機存取記憶體(DRAM)之立體化，節點接合介面（node side junction)與埋入式極板之漏電流亦隨之發生，因此引入一領氧化層於動態 隨機存取記憶體(DRAM)之溝槽電容技術中，以做為隔絕層進一步防止該漏 1238488 電μ危告DRAM胞之保留時間（retenti〇n time)。請參閱第1圖，其顯示習 知DRAM胞之渠溝排列的平面圖。應用於折疊位元線（f〇lded bit iine)結 構中母個主動區域中包含有兩條字元線界匕、WL2以及一條位元線见， 其甲符號DT代表-渠溝，符號％代表—位元接觸插塞。 叫翏閱第2圖，其顯示習知DRAM胞之渠溝電容的剖面示意圖。一半導 ，基底1G内製作有—溝槽DT，而溝槽DT之下方區域係製作成為-渠溝電 谷12其乃由一埋入電極板（buried plate)14、一節點介電層（n〇de •electric)16以及一儲存節點（st〇rage n〇de》8所構成。 、请荼閱第3至第5圖，其係顯示完成溝槽電容後之後續習知步驟，第3 圖為利用爐官成長-氧化層3〇，其包含溝槽電容表面氧化層施及溝槽上 部側壁，氧化層鳥，射騎±侧壁魏化層·可提供良好的隔絕效 果二接著’移除健存節點（st〇rage n〇de)18上之溝槽電容表面氧化層咖 如第4圖所不’然後沉積_第二複晶碎層仙如第5圖所示。在此溝槽上部 侧壁，有類健直式的金氧半電晶體，其憎槽上部锻領氧化層施即 為金氧半電晶體之氧化層，而第二複㈣層·彳如關極氧化層，而基底 10金氧半電晶體中之半導體材料。因此，領氧化層愈厚則該垂直式電晶體 $始電壓^(threshQld VQltage)，進而可聽後續形狀節點接合界 六奈面^ Γ^化層3G會造成在後續烟步驟中於第—複晶石夕上之溝槽1 合表=化層％不易去除乾淨，而產生第-、第二複晶韻之斷路。 仲县:電各表面氧化層施不易去除，因此需要較長的個時間 上侧之獅之條__ 【發明内容】 1238488 憶體(DRAM)之溝槽電容之製作上。 再者本發明之另一目的在於利用增加領氧化層（即溝槽上部侧壁之氧 化層）的厚度來產生較高的垂直式電晶體之起始賴，並同時避免複晶 存節點與導電層間之連接斷路。 根據上述之目的，本發明提供—種糊離子佈植餘以薄化第一複晶 石夕上之氧化層的方法，其在溝槽f容職之後，於溝觀容表面上進行二 離子佈植製程(例如:植入N2)，以抑制後續溝槽電容表面之氧化層的成長， ^槽電絲吨化層較溝槽上部罐_，如此可達完全侧移除溝槽 側所造紅_上部 祕層的心角（corner)過度侧。首先，提供一半導體基底，盆含 2溝槽以及—㈣電容，其帽槽式電容包含有-埋藏式電極板、二節 二電1: 一複晶石夕儲存節點。隨後，對該溝槽電容表面進行一離子佈植 ^思者，進行—氧化製程，於該溝槽上部側壁及溝槽電容表面成長- 二曰、，其中該氧化層赠槽上部繼之厚度大於溝槽電容表面之厚度。 側壁上錄縣除該電容表面之氧化層，以在溝槽之上部 ^ 減項氧化層再於溝槽内填入一導電層。 為讓本發明之上述和其他目的、特徵、和優 ;重:下文特舉出較佳實施例，並配合所附圖式，作詳細說= 【實施方式】 、本發明係—種利用離子佈植製程以薄化第-複晶石夕上之氧化層的方 法’其應用於一動態隨機存取記憶體(麵)之溝槽電容之製作上。請參考 :7 9圖，第7—9圖係顯示本發明之溝槽電容的形成方法之實施例示意圖。 月乂考弟7圖’首先，提供一半導體基底5〇 ’其内部包含有一溝槽Μ以及 一溝槽電容52,其中該溝槽電容52包含有一下電極54、_節點介電層脱 以及-複晶石夕儲存節點58。溝槽電容52之製作方式如下：提供一半導體基 1238488 底50,於該半導體絲50上形成一圖案化的塾層（㈣㈣灯所。其中， 該半導體基底50可以是由蟲晶石夕(印itaxial sinc〇n)或絕緣層上有矽 (silicon on insulator)所製作而成，在此為簡化說明，該半導體基底5〇 係以p型基絲例。練_錄層57軸_氧錄層53與—氮化石夕層 55所堆疊組成，其巾該氧化墊層53係以高溫爐麵氧方式成長於半導體基 底50上’而該氮化石夕層55係以低壓化學氣相沉積法（1〇w阶沾脏 chemical vapor d，siti〇n，LPCVD)形成—於墊氧化層53上，在此該墊 層57之厚度範圍約係2000 A。然後以該墊層57為餘刻罩幕進行反應性離 子兹刻⑽)以於基底50中形成-溝槽51。而後，藉由一重度摻雜氧化物(例 如：神玻璃()以及高溫短時間的退火製程，可使㈣離子紐至渠溝 DT下方區域，而形成一 n+型擴散區，用來作為電容之埋入電極板％。然後， 於溝槽DT之内側壁與墊氮化矽層55表面以低壓化學氣相沉積法，形成一 氮化石夕層56 ’而該氮化德56亦可為—氮切復切之複合層，接著於 溝槽DT内沉積-伽參雜之複晶石夕儲存節點58，並將複晶石夕齡節點沾 回侧至-預定深度。如此—來’殘留之複晶補存節點5_來為電容 之健存節點，而纽於伽練區54以及複晶销飾點Μ之間的氮化 石夕層56則係作為電容之節點介電層56a之用。 形成溝槽電容之後，請參考第8圖， rr^^as"(HF)' 區或之氮化矽層56b，接著於複晶矽儲存節點 植製程60，形成-離子佈值區62以抑制後續溝槽= 又一虱化層的成長。因此利用該離子佈植製程可使溝槽電办 面乳化層較溝槽上部側壁的薄，使溝槽電容表面氧化槽 1238488 上部側壁氧化層之厚度比約1/2至1/3，以達增加領氧化層（溝 槽上部側壁之氧化層）的厚度來產生較高的垂直式電晶體之起 始電壓的目的，並同時兼顧避免電容表面氧化層因清除不完全 而造成在複晶矽儲存節點與導電層之連接上的斷路。在此，以 植入N2離子為例，但本發明並非限定僅可以似植入，任何可 減少氧化層成長之離子佈植皆包括於本發明中。其中N2之植 入濃度約2E14至4E14,植入能量約12至i5KeV且其中N2之植入深 度約0至500A。 接著如第9圖所示，以低壓化學氣相沉積法（LpcvD)於攝 氏約890至910度及通以乾燥的氧氣（dry 〇xide)的爐管中成長 氧化層70 ’使溝槽電容表面氧化層7〇a對溝槽上部側壁氧化 層7〇b之厚度比約1/2至1/3,其中，該氧化層包含厚度約 1 00-150A之溝槽電容表面氧化層7〇a及厚度約26〇 —3〇〇a之溝 槽上部側壁領氧化層70b，在此溝槽上部側壁領氧化層_可 提供良好的隔絕效果以避免埋入式極板54與後續形成之節點 接合介面（node side junction)(未顯示）之漏電流。之後對氧 化層進行熱氧化或回火步驟，以使氧化層往半導體基底5〇延 伸，可達到更大面積的阻擋效果。在形成氧化層之步驟中，改 善了過去為避免溝槽上部側壁之垂直式I氧半電晶體產生漏 =流，將氧化層70之成長厚度由26〇 —3〇〇A增加至3〇〇a以上 4，所產生的溝槽電容表面氧化層7〇a(3〇〇A以上）不易蝕刻移 除且須增加反應時間的問題。其中，當溝槽電容表面氧化/夕 厚度為300A以上時，反應性離子钱刻需時約3〇一4〇秒才曰 ，完全，然而當蝕刻時間大於2〇秒以上時，溝槽上部側壁 乳化層70b之稜角（corner)gp會有過度钱刻的現象（6 圖）。因此，本發明達成了增加溝槽上部側壁之領氧化層 厚度且又能同時薄化了溝槽電容表面氧化層恤厚度之功效。 1238488 接著如第10圖所示，對溝槽電容表面氧化層70a進行反 應性離子蝕刻至露出複晶矽儲存節點58的表面為止，以在溝 槽72之上部側壁上形成一領型介電層70b，利用該領氧化層以 避免後續形成之節點接合界面（n〇de side junction)與埋入式 極板54之漏電流，最後於該溝槽51中填入一導電層80。在此， 溝槽電容表面氧化層70a之厚度因受植入N2之抑制由 260-300A降低至100-150A，使得後續反應性離子蝕刻步驟可 控制在15-20秒内完全除去該溝槽電容表面氧化層70a，並避 免因溝槽電容表面因氧化層移除不完全而造成複晶石夕儲存節 點58與導電層8〇間之斷路。 綜合上述，本發明可在成長較厚之溝槽上部側壁領氧化層 70b的同時，成長一較薄的溝槽電容表面氧化層70a，如此， 可輕易地移除該溝槽電容表面氧化層。綜合上述，本發明之優 點在於： 1.具有較厚之溝槽上部側壁領氧化層以避免漏電流。 2·具有較薄之溝槽電容表面氧化層，以避免複晶矽健存節 點與導電層間之連接斷路之問題。 3·具有較薄之溝槽電容表面氧化層，因此所需之蝕刻時間 較短可避免溝槽上部側壁領氧化層的稜角（c〇rner)過度钱刻。 雖然本發明已讀佳實施顯露如上，财並_錄定本發明，任 何熟習此技藝者，在不脫離本發明之精神和範g内，當 珊，因此侧额繼咖之_物麵鱗準更動與 【圖式簡單說明】 千 第1圖顯示習知DRAM胞之溝槽排列的平。 第2圖顯示習知咖胞之溝槽容器 ^ 第3至5圖顯示習知領氧化層製程/立 第6圖顯示習知領氧化層製 =面不意圖。 中弟1日㈣上之氧化層不易除去之剖 10 1238488 面示意圖。 第7至10圖顯示本發明利用離子佈植製程以薄化第一複晶矽上之氧化 層之剖面示意圖。 【主要元件符號說明】 10〜半導體基底；12〜溝槽電容；14〜下電極；16〜節點介電層；18〜儲存 節點；30〜氧化層；30a〜溝槽電容表面氧化層；30b〜溝槽上部侧壁領氧化層； 40〜第二複晶矽層；50〜半導體基底；52〜溝槽電容；53〜氧化墊層；54〜下電 極；55〜氮化矽層；56〜氮化矽層；56a〜節點介電層；56b〜溝槽上方區域之 氮化矽層；57〜圖案化墊層；58〜複晶矽儲存節點；60〜離子佈值製程；62〜 離子佈值區；70〜氧化層；70a〜溝槽電容表面氧化層；70b〜溝槽上部側壁領 氧化層；80〜導電層。Errors), etc.) will be greatly reduced. In other words, the larger the capacitance value, the higher the stability of the nourishment stored in the memory. —F integrated circuit (integrated eireuit, for making semiconductor elements with high integration on a 10-inch chip, you must consider how to reduce the size and power consumption of a memory cell (^ Norway. Qiao ^ eg)) to make it operate faster Speed up. In the traditional planar transistor design, in order to obtain a minimum-size memory cell, the gate length of the transistor must be shortened as much as possible to reduce the k-direction area of the memory cell. However, this will make the gate unbearable. The leakage current must correspondingly reduce the voltage on the bit line, thereby reducing the charge stored in the capacitor. Therefore, while shortening the lateral length of the gate, also consider how to make a capacitor with a large capacitance, such as: Increase the area of capacitors, reduce the effective dielectric thickness between capacitor plates, etc. At present, high-density memory (eg, dynamic random access memory, DRAM) has developed two different capacitor formation technologies, one of which is stacked Capacitor, the other is trench capacitor. Among them, the trench capacitor is made in the substrate to form a trench, and in the trench As a capacitor storage area, it will not occupy the extra area of the memory unit. With the three-dimensionalization of dynamic random access memory (DRAM), the leakage current of the node side junction and the embedded electrode plate also changes. Occurrence, so the introduction of a collar oxide layer in the dynamic random access memory (DRAM) trench capacitor technology as an isolation layer to further prevent the leakage 1238488 electrical μ hazard to the DRAM cell retention time (retention time ). Please refer to FIG. 1, which shows a plan view of a trench arrangement of a conventional DRAM cell. It is applied to a parent bit active area in a folded bit line structure, which contains two word line boundaries. See WL2, and a bit line. The symbol DT stands for-trench, and the symbol% stands for-bit contact plug. Refer to Figure 2, which shows a schematic cross-sectional diagram of a trench capacitor of a conventional DRAM cell. Half In the substrate 1G, a trench DT is fabricated, and the area below the trench DT is fabricated as a trench trench 12. It is composed of a buried electrode plate 14 and a node dielectric layer (n. de • electric) 16 and a storage node (st〇rage n〇 de》 8. Please read the 3rd to 5th figures, which show the subsequent learning steps after the completion of the trench capacitor. The 3rd figure is the use of furnace growth-oxide layer 30, which contains the trench capacitor The surface oxide layer is applied to the upper side wall of the trench, the oxide layer bird, and the shooting side ± the side wall weird layer can provide a good insulation effect. Secondly, 'remove the groove on the stabilizing node (st〇rage n〇de) 18 The oxide layer on the surface of the capacitor is not as shown in Figure 4 and then deposited_ The second complex crystal fragment is shown in Figure 5. In the upper side wall of this trench, there is a similar type of gold-oxygen semi-transistor. The forged collar oxide layer on the upper part of the groove is the oxide layer of the metal oxide semi-transistor, and the second complex layer, such as the gate oxide layer, and the semiconductor material in the base 10 metal oxide semi-transistor. Therefore, the thicker the oxide layer is, the higher the starting voltage of the vertical transistor is ^ (threshQld VQltage), and the subsequent shape node junction boundary hexanene plane ^ Γ ^ 3 layer 3G will result in The groove 1 on the spar eve = the chemical layer% is not easy to remove cleanly, and the first and second complex crystal rhymes are broken. Zhongxian: It is not easy to remove the oxide layer on each surface of the electricity, so it takes a long time. The top of the lion strip __ [Abstract] 1238488 DRAM trench capacitor production. Furthermore, another object of the present invention is to increase the thickness of the collar oxide layer (that is, the oxide layer on the upper side wall of the trench) to generate a higher initial value of the vertical transistor, and at the same time to avoid multiple crystal storage nodes and conduction. The connection between the layers is broken. According to the above object, the present invention provides a method for reducing the oxide layer on the first polycrystalline stone with a paste ion cloth plant residue, which performs a diionic cloth on the surface of the groove surface after the groove f is filled. Implantation process (eg, implanting N2) to suppress the growth of the oxide layer on the surface of the subsequent trench capacitors _ The corner of the upper myocardium is overly lateral. First, a semiconductor substrate is provided. The pot contains two trenches and a ㈣ capacitor. The cap-slot capacitor includes a buried electrode plate, two sections, two powers, and a polycrystalline stone storage node. Subsequently, an ion implantation process is performed on the surface of the trench capacitor, and an oxidation process is performed to grow on the upper side wall of the trench and the surface of the trench capacitor. The thickness of the trench capacitor surface. An oxide layer on the surface of the capacitor is removed on the side wall, so that a minus oxide layer is added to the upper part of the trench, and a conductive layer is filled in the trench. In order to make the above and other objects, features, and advantages of the present invention important: the following exemplifies the preferred embodiments, and describes them in detail with the accompanying drawings = [embodiment], the present invention is a kind of using ion cloth The method of thinning the oxide layer on the poly-sparite in the implantation process' is applied to the manufacture of the trench capacitor of a dynamic random access memory (plane). Please refer to FIGS. 7-9, and FIGS. 7-9 are schematic diagrams showing an embodiment of a method for forming a trench capacitor according to the present invention. Figure 7 of the test case "First, a semiconductor substrate 50" is provided, which contains a trench M and a trench capacitor 52, wherein the trench capacitor 52 includes a lower electrode 54, a _node dielectric layer, and-晶晶 夕夕 node 58. The manufacturing method of the trench capacitor 52 is as follows: a semiconductor substrate 1238488 bottom 50 is provided, and a patterned ytterbium layer is formed on the semiconductor wire 50. The semiconductor substrate 50 may be made of insect crystal itaxial sinc〇n) or silicon on insulator on the insulating layer, to simplify the description here, the semiconductor substrate 50 is an example of a p-type base wire. Practice_Recording layer 57Axis_Oxygen recording layer 53 and-nitride nitride layer 55, the oxide pad layer 53 is grown on the semiconductor substrate 50 by high-temperature furnace surface oxygen method, and the nitride nitride layer 55 is formed by a low pressure chemical vapor deposition method (1 〇w stage contamination (chemical vapor d, siti ON, LPCVD) is formed-on the pad oxide layer 53, where the thickness of the pad layer 57 is about 2000 A. Then, the pad layer 57 is used as a mask The reactive ions are engraved) to form a trench 51 in the substrate 50. Then, through a heavily doped oxide (such as: god glass ()) and high temperature and short-time annealing process, thallium ions can be linked to the area below the trench DT to form an n + type diffusion region, which is used as a capacitor. The electrode plate is embedded. Then, a low-pressure chemical vapor deposition method is formed on the inner side wall of the trench DT and the surface of the silicon nitride layer 55 to form a nitrided layer 56 ′, and the nitrided layer 56 may be nitrogen. The complex layer was cut and re-cut, and then a -Garium-doped polycrystalline stone storage node 58 was deposited in the trench DT, and the polycrystalline stone aged node was dipped back to the side to a predetermined depth. In this way-to 'remaining compound The crystal supplementary storage node 5_ is a healthy storage node of the capacitor, and the nitrided layer 56 between the training area 54 and the multi-crystal pin decoration point M is used as the node dielectric layer 56a of the capacitor. After the trench capacitor, please refer to FIG. 8, the rr ^^ as " (HF) 'region or the silicon nitride layer 56b, and then implant the polycrystalline silicon storage node in a process 60 to form an ion distribution region 62 to suppress subsequent Groove = growth of another lice-forming layer. Therefore, the use of this ion implantation process can make the emulsified layer of the groove electrical surface more than the groove. The thinner sidewalls make the surface of the trench capacitor surface oxidation groove 1238488. The thickness ratio of the oxide layer on the upper sidewall is about 1/2 to 1/3, in order to increase the thickness of the collar oxide layer (the oxide layer on the upper sidewall of the trench) to produce a higher thickness. The purpose of the initial voltage of the vertical transistor is to avoid the disconnection of the connection between the polycrystalline silicon storage node and the conductive layer caused by the incomplete removal of the oxide layer on the capacitor surface. Here, the implantation of N2 ions is used as For example, the present invention is not limited to implantation. Any ion implantation that can reduce the growth of the oxide layer is included in the present invention. The implantation concentration of N2 is about 2E14 to 4E14, and the implantation energy is about 12 to i5KeV. The implantation depth of N2 is about 0 to 500 A. Then, as shown in Fig. 9, the low pressure chemical vapor deposition method (LpcvD) is used in a furnace tube of about 890 to 910 degrees Celsius and passed through dry oxygen (dry oxygen). Growing the oxide layer 70 'makes the thickness ratio of the surface oxide layer 70a of the trench capacitor to the oxide layer 70b of the upper side wall of the trench about 1/2 to 1/3, wherein the oxide layer includes a thickness of about 100-150A. Oxide layer 70a on the surface of the trench capacitor and a thickness of about 26-30a Oxide layer 70b on the upper sidewall of the trench. Here, the oxide layer on the upper sidewall of the trench can provide a good insulation effect to prevent the buried plate 54 from forming a node side junction (not shown). Leakage current. The oxide layer is then thermally oxidized or tempered, so that the oxide layer extends to the semiconductor substrate 50, which can achieve a larger area of barrier effect. In the step of forming the oxide layer, the past has been improved to avoid trenches The vertical I-type oxygen semi-transistor on the upper side wall generates leakage current, which increases the growth thickness of the oxide layer 70 from 260-300A to more than 300a4. The trench capacitor surface oxide layer 7 is generated. a (above 300A) is not easy to be removed by etching and has to increase the reaction time. Among them, when the thickness of the surface of the trench capacitor is more than 300A, it takes about 30 to 40 seconds for the reactive ion money to be etched, which is complete. However, when the etching time is more than 20 seconds, the upper sidewall of the trench is etched. The corner gp of the emulsified layer 70b may be excessively engraved (Figure 6). Therefore, the present invention achieves the effect of increasing the thickness of the collar oxide layer on the upper side wall of the trench and simultaneously reducing the thickness of the oxide layer on the surface of the trench capacitor. 1238488 Next, as shown in FIG. 10, the trench capacitor surface oxide layer 70a is reactively etched until the surface of the polycrystalline silicon storage node 58 is exposed to form a collar-type dielectric layer on the sidewall of the upper portion of the trench 72. 70b. The collar oxide layer is used to avoid the leakage current of the node side junction and the buried electrode plate 54 formed later, and finally a conductive layer 80 is filled in the trench 51. Here, the thickness of the trench capacitor surface oxide layer 70a is reduced from 260-300A to 100-150A due to the suppression of implanted N2, so that the subsequent reactive ion etching step can be controlled to completely remove the trench capacitor within 15-20 seconds. Surface oxide layer 70a, and avoid the disconnection between the polycrystalline stone storage node 58 and the conductive layer 80 due to the incomplete removal of the oxide layer on the surface of the trench capacitor. In summary, the present invention can grow a thinner trench capacitor surface oxide layer 70a while growing a thicker trench upper side collar oxide layer 70b, so that the trench capacitor surface oxide layer can be easily removed. In summary, the advantages of the present invention are as follows: 1. It has a thicker oxide layer on the upper side wall of the trench to avoid leakage current. 2. It has a thin oxide layer on the surface of the trench capacitor to avoid the problem of disconnection of the connection between the polycrystalline silicon survival node and the conductive layer. 3. It has a thin oxide layer on the surface of the trench capacitor, so the short etching time can avoid the corners of the oxide layer on the upper side of the trench. Although the implementation of the present invention has been read and the above is revealed, the financial and financial records of the present invention, anyone skilled in this art, without departing from the spirit and scope of the present invention, should be savvy. [Brief description of the figure] The first figure of the thousandth figure shows the flat arrangement of trenches of a conventional DRAM cell. Fig. 2 shows a trench container of a conventional coffee cell. ^ Figs. 3 to 5 show a conventional collar oxide layer process. Fig. 6 shows a conventional collar oxide layer system. It is not intended. Section 12 1238488 Schematic diagram of the difficult to remove oxide layer on the younger brother. Figures 7 to 10 show schematic cross-sectional views of the present invention using an ion implantation process to thin the oxide layer on the first polycrystalline silicon. [Description of main component symbols] 10 ~ semiconductor substrate; 12 ~ trench capacitor; 14 ~ lower electrode; 16 ~ node dielectric layer; 18 ~ storage node; 30 ~ oxide layer; 30a ~ trench capacitor surface oxide layer; 30b ~ Oxide layer on the upper sidewall of the trench; 40 ~ second polycrystalline silicon layer; 50 ~ semiconductor substrate; 52 ~ trench capacitor; 53 ~ oxide pad layer; 54 ~ bottom electrode; 55 ~ silicon nitride layer; 56 ~ nitrogen Siliconized layer; 56a ~ node dielectric layer; 56b ~ silicon nitride layer in the area above the trench; 57 ~ patterned pad layer; 58 ~ polycrystalline silicon storage node; 60 ~ ionization process; 62 ~ ionization process Area; 70 ~ oxide layer; 70a ~ trench capacitor surface oxide layer; 70b ~ trench upper sidewall collar oxide layer; 80 ~ conductive layer.