TWI238472B - Method of passivating semiconductor device - Google Patents

Abstract

This invention is related to a method of passivating a semiconductor device. The method includes the steps of performing a high pressure annealing treatment on the semiconductor device and performing a plasma treatment on the semiconductor device in order to dissipate charges accumulated in the semiconductor device after the high pressure annealing treatment is performed. The process gas used in the plasma treatment may be N2, H2, H2O, N2O, O2, NH3 or a mixture.

Description

1238472, V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for protecting semiconductor elements. The function is used to repair defects of semiconductor elements in the previous process. . [Previous technology] Semiconductor devices are generally completed through a number of process steps, which may include money boat deposition, lithography, wet etching, plasma money etching, chemical vapor deposition, plasma-assisted chemical vapor deposition, Ion implantation and annealing steps that activate and drive the implanted ions. Some of these process steps can cause defects in semiconductor devices. For example, the plasma etching process will generate silicon dangling bonds, and the stone dangling bonds will further cause the decrease of electron mobility, which will deteriorate the characteristics of semiconductor components, and the ion implantation process may also Damage to Shi Xi's crystal structure. Recently, a high pressure anneal has been developed to reduce the problems caused by broken silicon bonds. In a high-pressure tempering process, a semiconductor element is generally heated by passing a high-pressure gas (such as hydrogen or ammonia) into it. It is generally believed that the hydrogen that is passed in will form a bond with the broken bonds of silicon in the semiconductor device to remove defects in the semiconductor device that were generated in the previous process. However, this high-pressure tempering is false when the charge of the semiconductor element accumulates, so that its critical charge = two. ld voltage) generate drift, which affects the operation of the designed circuit. SUMMARY OF THE INVENTION The object of the present invention is to provide an improved semiconductor element protection.

1238472 • V. Description of the Invention (2) (passivating) method to overcome or improve the problems of the prior art. The method for protecting a semiconductor device according to the present invention includes performing a high pressure annealing treatment on the semiconductor device and performing a piasma treatment on the semiconductor device to eliminate the high pressure annealing treatment. Then, the electric charge accumulated in the semiconductor element. The high-pressure tempering process includes placing a semiconductor device in a chamber; passing a reaction gas (such as nitrogen, hydrogen, water, ammonia, or a mixture thereof), and heating the semiconductor device until sufficient protection is generated. until. It makes it mixed with the sample), and by this state, the crystals are eliminated here. The semiconductor film is applied to the semiconductor. This electric mass processing can be achieved by an electron cyclotron resonance (ECR) method or an inductively coupled plasma method (ICP). And the process gas used can be nitrogen, hydrogen, water, laughing gas, oxygen, ammonia or substances. In addition, the process of plasma treatment is to place a semiconductor device slot, connect a heater, and apply an electrical bias (eUctric bias), so that the incoming process gas can be ionized into ions or free high temperature and or electric field The charge diffused into the semiconductor element and accumulated in the semiconductor element. That is, the semiconductor element may be a thin layer containing a polycrystalline silicon film layer. The present invention provides another method for protecting a semiconductor element, in which a carcass component is subjected to a high-pressure tempering treatment; thereafter, Forming a ruj: ^ de film (such as a silicon nitride film (siHc〇nn ^ ride or a silicon oxynitride film) on a conductive element; finally, the nitride film is added to a two =

1238472 V. Description of the invention (3) [Embodiment] Referring to FIG. 1, a cross-sectional view of a semiconductor device 100, which is protected according to the principle of the present invention, is shown. The semiconductor device 100 'includes a P-channel metal-oxide-semiconductor (PM0S) transistor 11 () and an N-channel metal-oxide-semiconductor (NM0S) transistor 120. The semiconductor device 100 may be a complementary metal-oxide-semiconductor (CMOS) device, a bi-carrier complementary metal-oxide-semiconductor (BiCMOS) device, a dynamic random access memory (DRAM), or other types of integrated circuits. The semiconductor element suitable for the present invention may be a thin film transistor including a polycrystalline silicon film layer. As shown in FIG. 1, the semiconductor device 100 includes a buffer layer (such as a dioxide layer), which is formed on a substrate 1 Q 4 (such as a glass substrate), and two semiconductor structures. 1 1 1, 1 2 1 (normally a polycrystalline silicon thin film) is formed on the buffer layer 102, a gate dielectric layer 150 (such as a silicon oxide layer) is formed on the semiconductor structures 111, 121, and two gates The electrodes 118, 128 ° PM0S transistor 110, the source 1 1 4 and the drain 1 1 6 are made by using a p-type dopant (d 〇pant) using the gate electrode 1 1 8 as a mask. The self-aligned (sel f -al ign) method is formed by implanting the semiconductor structure 111 by an ion implantation method or a plasma doping method. The source 1 24 of the NMOS transistor 120 and the non-electrode 12 6 are implanted into the semiconductor structure 1 2 1 by using the N-type dopant as the gate electrode 1 2 8 as a mask. And formed. (See FIG. 2) After a protective layer 130 (such as a silicon dioxide layer) is formed on the entire surface of the semiconductor device 100 ′, defects generated in the semiconductor device 100 in the previous process, such as dangling bonds (not Saturated Stone Xi Bond), by performing a high pressure tempering treatment on the semiconductor device 100 (high pressure

00759.ptd page 8 1238472 ‘fifth, the description of the invention (4) anneal ing) and repair it. The process is to place the semiconductor device in a reaction chamber, and then pass in a reaction gas such as water vapor, nitrogen, ammonia or hydrogen into the reaction chamber under high pressure and perform heat treatment. However, in a preferred embodiment, the high-pressure tempering treatment is performed between 5 and 20 atmospheric pressures. In one embodiment, the high-pressure tempering treatment may be performed at a temperature below 600 ° C. The duration of the high-pressure tempering process depends on the pressure used. Since the high-pressure tempering treatment is performed under high pressure, its temperature and time can be effectively reduced. Those skilled in the art can obtain the optimal conditions of the high-pressure tempering treatment of the present invention according to the aforementioned process parameters. However, due to the high-pressure tempering process, the charge accumulation of the protective layer 130, the gate dielectric layer 150, or the semiconductor structure 1 11, 1 1 2 in the semiconductor device 100 is often caused by the high-pressure tempering process. (Figure 3), so that the threshold voltage (threshold voltage) drifts, which affects the operation of the designed circuit. Therefore, referring to FIG. 4, the present invention performs a plasma treatment procedure on the semiconductor device 100 to eliminate the electric charge accumulated in the semiconductor device 100 after the high-pressure tempering treatment. The process is to connect the sample slot of the semiconductor device 100, connect a heater and apply an electric bias, so that the incoming process gas can be ionized into ions or free radicals. 'It diffuses into the semiconductor device 100 under the action of the south temperature and the electric field, thereby eliminating the electric charge accumulated in the semiconductor device 1000. This plasma treatment can be performed by electron cyclotron resonance (e 1 e c t r ο η cyclotron resonance, ECR) or inductively coupled plasma method.

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'Fifth, the invention description (5) (Inductively Coupling Plasma, ICP) to achieve; and the process gas used can be nitrogen, hydrogen, water, laughing gas, oxygen, ammonia or a mixture thereof. It can be understood that the protection method of the present invention can also be implemented before the protection layer 130 is formed. The invention also provides another method for protecting a semiconductor device. First, the aforementioned PMOS transistor 1 10 or NMOS transistor 1 20) is formed on a substrate 104. A protective layer 1 30 (such as a silicon dioxide layer) is further formed on the PM0s transistor 110 and the NMOS transistor 120, and the aforementioned high-pressure tempering treatment (see FIG. 5) is performed, and then a nitride film (nitri) is formed. (1e nim) 132 (such as a silicon nitride film or a silicon oxide nitride film) on the protective layer 13. Finally, referring to FIG. 6, the nitride is further heat-treated. The thin film 3 2 is used to eliminate the electric charge accumulated in the semiconductor element after the high-pressure tempering treatment (the charge is shown in Table 1 as a star symbol and is shown in Figures 5 and 6). The aforementioned heating T treatment Furnace anneaiing or rapid thermal annealing can be used for alder. Using the aforementioned method of the present invention, the charge accumulated in the semiconductor device 100 can be effectively reduced, thereby reducing the semiconductor device effectively. The threshold voltage (threshold v〇itage) drifts, so that the designed circuit works normally. Figure 7 shows the relationship between the voltage applied to the gate and the drain current. The curve A is a diagram Without Id-Vg characteristics of the semi-conductive element under pressure tempering, curve B is a graph showing the half subjected to high-pressure tempering treatment =-with characteristic curve, curve C is a semiconductor element showing high-pressure tempering treatment and 〇electric water treatment Id ~ Vg characteristics. As can be seen from the figure, after high voltage 2

1238472 ’V. Description of the invention (6) The ideal operating mode for the operation of semiconductor integrated circuits for the thermal processing and plasma processing of 02 components. /. Although the present invention is discussed in detail for an active-moment-type metal-oxide-semiconductor (CMOS) circuit: complementary to a variety of thin-film transistor-containing oxygen

MOSFET). Lai Fung & Body Field Effect Transistor (S0I Although the present invention has been implemented in the aforementioned preferred embodiments, the present invention, anyone familiar with this technology =; it is not intended to be used within a limited range, and can be modified and changed Modification: From the spirit of the present invention: The scope of the patent application attached to Dangdang View is defined by the protection scope of the present invention 00759.ptd Page 11 1238472 Simple illustration of the drawings [Simplified illustration of the drawings] Figures 1 to 4 Figures: The main steps of a method for protecting a semiconductor device are shown in a sectional view according to an embodiment of the present invention, and Figures 5 to 6 are views showing the methods of manufacturing a semiconductor device in a sectional view according to an embodiment of the present invention. The main steps; and Figure 7: is a diagram of the relationship between the voltage applied to the gate and the current flowing through the drain. Description of the drawing number: 100, semiconductor element 100 semiconductor element 102 buffer layer 104 substrate 110 PMOS transistor 111 semiconductor structure 112 Semiconductor structure 114 Source 116 Drain 118 Gate electrode 120 NMOS transistor 124 Source 126 Drain 128 Gate electrode 130 Protective layer 132 Nitrogen thin film 150 Gate dielectric layer 200 Complementary metal-oxide-semiconductor circuit

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Claims (1)

1238472 6. Scope of patent application 1. A method for protecting a semiconductor element (passivating), which includes at least the following steps on the semiconductor element: A high pressure annealing step to repair the semiconductor element Defects; and a plasma treatment step for removing charges generated in the semiconductor device. 2. The method for protecting a semiconductor element according to item 1 of the scope of patent application, wherein the high-pressure tempering treatment step includes at least: placing the semiconductor element in a reaction chamber; passing a reaction gas into the reaction chamber (chamber) ); And heating the semiconductor element until protection is sufficient. 3. The method for protecting a semiconductor device according to item 2 of the scope of the patent application, wherein the reaction gas system is one of nitrogen, hydrogen, water, and ammonia, or a mixture thereof. 4. The semiconductor element protection method according to item 1 of the scope of patent application, wherein the plasma processing step is an electron cyclotron resonance method (ECR) or an inductively coupled plasma method (ICP). 5. The semiconductor element protection method according to item 1 of the scope of patent application, wherein one of the process gas systems used in the plasma processing step is one of nitrogen, hydrogen, water, laughing gas, oxygen, and ammonia, or a mixture thereof. 00759.ptd Page 13 1238472 6. Scope of patent application 6. The method for protecting a semiconductor element according to item 1 of the scope of patent application, wherein the semiconductor element is a thin film transistor containing a polycrystalline silicon film layer. 7. The method for protecting a semiconductor element according to item 1 of the scope of patent application, wherein the method for protecting a semiconductor element may also be implemented before the semiconductor element forms a protective layer. 8. A method for passivating a semiconductor device, wherein the method includes at least the following steps: performing a high-pressure tempering step on a semiconductor device to repair defects generated in the semiconductor device; forming a nitride film on the semiconductor device; On the semiconductor element; and performing a heat treatment step on the nitride film to remove the charges generated in the semiconductor element. 9. The semiconductor element protection method according to item 8 of the scope of the patent application, wherein the high-pressure tempering treatment step includes at least: placing the semiconductor element in a reaction chamber; introducing a reaction gas into the reaction chamber; and heating the reaction chamber. The semiconductor element is sufficient to provide protection. 10. The method for protecting a semiconductor device according to item 9 of the scope of the patent application, wherein the reaction gas system is one of nitrogen, hydrogen, water, and ammonia, or a mixture thereof. 00759.ptd Page 14 1238472 VI. Application for patent scope 1 1. The method for protecting semiconductor elements according to item 8 of the patent application scope, wherein the heat treatment step is a furnace annealing (f U rnace annealing) or a rapid annealing Rapid thermal annealing o 1 2. The method for protecting a semiconductor device according to item 8 of the patent application, wherein the semiconductor device is a thin film transistor containing a polycrystalline silicon film layer. 1 3. The method for protecting a semiconductor device according to item 8 of the scope of the patent application, wherein the nitride film is a nitride film (s i 1 i c ο η n i t r i d e) film or a nitrogen oxide 4 silicon oxide nitride (silicon oxide nitride) film o 00759.ptd Page 15