TWI237383B - Junction diode - Google Patents

Abstract

A junction diode comprises a first conductor type substrate, a second conductor type embedded area, a second conductor type well, a first conductor type doped area and second conductor type doped area is provided. The second conductor type embedded area is formed in the first conductor type substrate. The second conductor type well is formed in the second conductor type embedded area. The doped concentration of the second conductor type well is smaller than the doped concentration of the second conductor type embedded area. The first conductor type doped area is formed at the surface of the second conductor type well. The second conductor type doped area is formed at the surface of the second conductor type embedded area. The junction diode has a smaller capacitance, so it can be an electrostatic discharge protecting device of a radio frequency (RF) circuit and won't affect the transmission speed of the RF circuit.

Description

1237383 V. Description of the invention (1) Field of the invention The present invention relates to a diode, and more particularly to a junction diode with low capacitance. Prior art Electrostatic discharge is a phenomenon in which static electricity moves from the surface of a non-conductor, which can cause damage to semiconductors and other circuits in integrated circuits. For example, at high relative humidity, a static voltage of about several hundred to several thousand volts can be detected in a human body walking on a carpet. At low relative humidity, static voltages above 10,000 volts can be detected. In the same way, on machines that package integrated circuits or instruments that test integrated circuits, static voltages of about several hundred to several thousand volts may be generated due to the humidity or other factors in the environment. When the above-mentioned charged body (human body, machine, or instrument) contacts the wafer, it will discharge to the wafer. The instantaneous power of this electrostatic discharge may cause damage or failure of the integrated circuit in the wafer. Therefore, in order to prevent the electrostatic discharge from damaging the integrated circuit in the wafer, various electrostatic discharge protection components are designed accordingly. The most common practice is to design an electrostatic discharge protection circuit on the input / output pads (I / O Pads) on the chip to provide a path for electrostatic discharge so that the circuit on the chip is not damaged by the electrostatic discharge current. Figure 1 is a schematic diagram of the circuit configuration of a general electrostatic discharge protection circuit. Please refer to FIG. 1. The electrostatic discharge protection circuit 100 usually uses a diode as a protection element in the circuit, that is, the diode 104 and the diode 106 indicated in the first figure. Furthermore, in general, the voltage peaks and voltage valleys of the input / output signals of the integrated circuit (not shown) are respectively

12737TWF.PTD Page 6 1237383 V. Description of the invention (2) Near the power supply voltage V d d and its ground voltage V s s. Therefore, the design of this electrostatic discharge protection circuit 100 is to electrically connect the cathode of the diode 104 and the anode of the diode 106 to the power supply voltage V dd and the ground voltage Vss, respectively, and use a metal-oxide semiconductor. The (MOS) transistor 108 serves as a clamping element and is electrically connected to the power supply voltage V dd and the ground voltage V ss to maintain a potential difference between the power supply voltage Vdd and the ground voltage Vss. During the power-on operation of the integrated circuit, the input / output signal of the integrated circuit is input / output by the pad 102, and the diode 104 and the diode 106 are reverse biased at this time, so And will not be turned on. In the case of rapid electrostatic discharge of the integrated circuit, that is, when the voltage peak / valley of the integrated circuit electrostatic discharge is quite large (up to 2K / -2K volts), the diode 104 and the diode 1 0 6 will be in conduction or collapse mode. Therefore, the electrostatic discharge protection circuit 100 can introduce the generated electrostatic discharge to the ground terminal or the power terminal, and will not be received by the internal integrated circuit to achieve the protection effect. However, most diodes used in the prior art are made of MOS devices. However, for a radio frequency (RF) integrated circuit, the capacitance of the MOS element is too large, which easily affects the transmission speed of the radio frequency circuit. In addition, the area occupied by diodes made of M 0S elements is also quite large, which is a major disadvantage for integrated circuits that are increasingly miniaturized. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a junction diode, which has a small capacitance and an area and can be applied to radio frequency (R a d i 〇

12737TWF.PTD Page 7 1237383 V. Description of the invention (3)

Electrostatic discharge protection circuit in Frequency (RF) circuit, which does not affect the performance of the RF circuit, and can be completed in the general process of bipolar complementary metal-oxide semiconductor (Bipolar CMOS, BiCMOS for short). Another object of the present invention is to provide a junction diode, which has a small capacitance and an area that can be applied to an electrostatic discharge protection circuit in a radio frequency circuit, and does not affect the transmission speed of the radio frequency circuit, and can be used in a general complementary type. Adding a photomask to the process of metal oxide semiconductor (CMOS) can be done. The invention proposes a junction diode, which is mainly composed of a first conductivity type substrate, a second conductivity type buried region, a second conductivity type well region, a first conductivity type doped region, and a second conductivity type doped region. . Wherein, the second conductivity type buried region is disposed in the first conductivity type substrate, the second conductivity type well region is disposed in the second conductivity type buried region, and the doping concentration of the second conductivity type well region is less than that of the first conductivity type well region. Doping concentration of the two-conductivity-type buried region. The first conductive type doped region is disposed on the surface of the second conductive type well region, and the second conductive type doped region is disposed on the surface of the second conductive type buried region. According to an embodiment of the present invention, the first conductive type substrate is, for example, a P-type substrate, and the second conductive type buried region is, for example, an N-type buried region. The second conductivity type well area is, for example, an N type well area, and it is preferably an N type epitaxial layer. The first conductive type doped region is, for example, a P-type doped region, and the second conductive type doped region is, for example, an N-type doped region. In one embodiment, the junction diode further includes an isolation structure disposed between the first conductivity type doped region and the second conductivity type doped region. The invention proposes a junction diode, which is mainly composed of a first conductivity type.

12737TWF.PTD Page 81237383 V. Description of the invention (4) Substrate, second conductive type deep well area, first conductive type well area, first conductive type shallow well area, multiple first conductive type doped areas, multiple A two-conductivity type doped region and a plurality of isolation structures. Among them, the second conductive type deep well area is disposed in the first conductive type base, the first conductive type well area is disposed in the second conductive type deep well area, and the first conductive type shallow well area is disposed in the first conductive type well area. The doping concentration of the first conductive type well region is smaller than that of the first conductive type well region. The first conductive type doped region is disposed on the surface of the first conductive type well region, and the second conductive type doped region is disposed on the surfaces of the first conductive type shallow well region and the second conductive type deep well region. According to an embodiment of the present invention, the first conductive type substrate is, for example, a P-type substrate, and the second conductive type deep well region is, for example, an N-type deep well region. The first conductive type well area is, for example, a P type well area, and the first conductive type shallow well area is, for example, a P type shallow well area. The first conductivity type doped region is, for example, a P type doped region, and the second conductivity type doped region is, for example, an N type doped region. In addition, in one embodiment, the junction diode further includes an isolation structure disposed between each of the second conductivity type doped regions and two adjacent ones of the first conductivity type doped regions. It can be known from the above that the doped concentration of one end of the bonded diodes of the present invention is low. The purpose is to reduce the capacitance of the bonded diodes of the present invention, so that the bonded diodes of the present invention are suitable as radio frequency circuits. The electrostatic discharge protection element in the device does not have the problem that the transmission speed of the RF circuit is affected due to the excessive capacitance. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings.

12737TWF.PTD Page 91237383 V. Description of the invention (5) Embodiment The junction diode proposed by the present invention can have a lower capacitance. Therefore, the present invention can be used as an electrostatic discharge protection element in a radio frequency circuit without affecting Transmission speed of RF circuits. Hereinafter, the present invention will be described in detail through preferred embodiments, but is not intended to limit the present invention. In particular, in the following embodiments, the type of the first conductivity type is P type, and the type of the second conductivity type is N type. However, those skilled in the art should know that the first conductivity type The conductivity type is replaced with an N type, and the second conductivity type is replaced with a P type. FIG. 2 is a schematic cross-sectional view of a junction diode according to a preferred embodiment of the present invention. Please refer to FIG. 2. This junction diode is mainly composed of a P-type substrate 200, an N-type deep well region 202, an N-type well region 204, a P-type doped region 208, an N-type doped region 206, and an isolation structure 210. . Among them, 202 in the N-type deep well area is disposed in the P-type base 200, and N-type well area 20 4 is disposed in the N-type deep well area 202, and the doping concentration of the N-type well area 204 is relatively higher. Light, which is, for example, a doping concentration less than 2 2 in the N-type deep well region. The P-type doped region 208 is disposed in the N-type well region 204, and the N-type doped region 206 is disposed in the N-type deep well region 202. The formation method of the N-type deep well region 202, the N-type well region 204, the P-type doped region 208, and the N-type doped region 206 is, for example, an ion implantation method, and the P-type substrate 2 is formed according to the method. Different depths configured in 0 0 use different energies for ion implantation. It is worth noting that, because the doping concentration of the N-type well region 204 is relatively light, the present invention arranges an N-type deep well region 202 between the N-type well region 204 and the P-type substrate 200. In this way, it is possible to prevent the current from flowing into the N-type well region 204 through the P-type doped region 208 because the empty area of the N-type well region 204 is too large and the current is caused.

12737TWF.PTD Page 10 1237383 V. Description of the invention (6) It rushes directly into the P-type substrate 200, thereby invalidating the junction diode. In addition, the isolation structure 210 is disposed between the P-type doped region 208 and the N-type doped region 206 to prevent the P-type doped region 208 and the N-type doped region 206. A path is formed between them to avoid failure of the junction diode element. The method for forming the isolation structure 2 1 0 is, for example, a regional oxidation method (L oca 1 0 X idati ο η, abbreviated as L 0 C 0 S) or a shallow trench isolation method (S ha 1 1 ow Trench Isolation, abbreviated as STI). ). In particular, the junction diode of this embodiment can be directly manufactured by a general B i C M 0 S process, without additional process steps. And in a general BiCMOS process, the N-type well region 204 is, for example, an N-type epitaxial layer, and its doping concentration is at least one order lower than the doping concentration of the general well region. Therefore, it is used as the bonding diode of the present invention. The N-type end of the body can produce a low-capacitance junction diode. In addition, the junction diode of the present invention can also be manufactured by using a common CMOS process step. This embodiment will be described in detail below with reference to the drawings. FIG. 3 is a schematic cross-sectional view of a junction diode according to another embodiment of the present invention. Please refer to FIG. 3, this junction diode is mainly composed of P-type substrate 300, N-type deep well region 302, P-type well region 304, P-type shallow well region 3 0 6, P-type doped region 3 1 0, N-type The doped region 3 0 8 and the isolation structure 3 1 2 are formed. Among them, the N-type deep well area 302 is disposed in the P-type base 300, the P-type well area 3 0 4 is disposed in the N-type deep well area 3 02, and the P-type shallow well area 3 0 6 is disposed in the P-type well. In the region 3 0 4, the doping concentration of the P-type shallow well region 3 6 is relatively light, for example, it is smaller than the doping concentration of the P-type well region 3 0 4.

12737TWF.PTD Page 111237383 V. Description of the invention (7) P-type doped regions 3 1 0 are arranged in P-type well regions 3 0 4 and N-type doped regions 3 0 8 are arranged in P-type shallow well regions 3 0 6 and N 2 deep well zone 3 2 0. The formation method of the N-type deep well region 302, the P-type well region 304, the P-type shallow well region 306, the P-type doped region 310, and the N-type doped region 308 is, for example, an ion implantation method, and the P-type well region is formed according to the method. Ion implantation is performed at different depths in the substrate 300 using different energies. It is worth noting that, in a general CMOS process, a P-type substrate is mostly used as a substrate for forming an element, and in order to prevent signals entering the junction diode from the P-type doped region 310 from passing through the P-type substrate 300, Noise is caused, so the present invention configures an N-type deep well region 302 in the P-type substrate 300 to prevent signals from being transmitted to the P-type substrate 300. In addition, since the doping concentration of the P-type shallow well region 306 is relatively low, the present invention is arranged between the P-type shallow well region 306 and the N-type deep well region 302. In this way, when the current flows into the P-type shallow well region 3 06 through the N-type doped region 3 0 in the P-type shallow well region 3 06, the current is caused by the empty region of the P-type shallow well region 3 06 being too large, which causes the current to flow. It rushes directly into the N-type deep well zone 3 02, thereby invalidating the junction diode. In addition, the isolation structure 3 1 2 is disposed between each N-type doped region 3 1 0 and the adjacent P-type doped region 3 0 8 to prevent the P-type doped regions 3 1 0 and N. A path is formed between the type doped regions 3 0 and 8 to avoid failure of the junction diode element. The method for forming the isolation structure 3 1 2 is, for example, the same as or similar to the isolation structure 2 1 0 (shown in FIG. 2) in the foregoing embodiment, and details are not described herein again.

According to the structure of the above diode, as long as the existing CMOS is used,

12737TWF.PTD Page 12 1237383 V. Description of the invention (8) The process, and adding an additional mask and steps in it to form a P-type well area 304, can complete the junction diode of this embodiment. In summary, the junction diode of the present invention can be completed directly in the existing BiCMOS process, or a photomask can be added to the existing CMOS process to complete the production, without the need to add additional complicated processes. The junction diode of the present invention is completed. In addition, since the size of the capacitance of the junction diode is mainly determined by the concentration at both ends of the junction and its area, the junction diode of the present invention has a lower concentration at one end, for example, in the first embodiment. The purpose of the N-type terminal and the P-type terminal in the second embodiment is to reduce the capacitance of the junction diode of the present invention. It can be known from the experimental results that the bonded diode of the present invention can achieve a human body electrostatic discharge mode of 4,000 volts and a machine electrostatic discharge mode of 2,000 volts with a capacitance of 3 2 · 1 f F. Compared with the conventional diode (capacitance of several hundreds of f F), the capacitance of the bonded diode of the present invention is relatively small, so it can be used as an electrostatic discharge protection element in a radio frequency circuit without It is known that the transmission speed of the RF circuit is affected by the excessive capacitance. Moreover, when the junction diode of the present invention is applied to an electrostatic discharge protection circuit, more than two junction diodes can be connected in series in the circuit, so as to obtain a smaller equivalent capacitance. It can be known from the experimental results that if two junction diodes with a capacitance of 32.1fF are connected in series in the electrostatic discharge protection circuit, the equivalent capacitance provided by the junction diode is 15.6 f F. In addition, the present invention occupies a relatively small area compared with the conventionally used M 0 S diode. Therefore, in the integrated circuit, the connection of the present invention

12737TWF.PTD Page 13 1237383 V. Description of the invention (9) The use of a combined diode instead of the conventional M 0 S diode can solve the problem that the area of the diode is too large and the integration of the integrated circuit is reduced. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

12737TWF.PTD Page 14 1237383 Brief description of the diagram The first diagram is a schematic diagram of the circuit configuration of an ordinary electrostatic discharge protection circuit. FIG. 2 is a schematic cross-sectional view of a junction diode according to a preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a junction diode according to another embodiment of the present invention. [Schematic description] 1 0 0: Electrostatic discharge protection circuit 102: Pads 104, 106: Diode 108: Metal oxide semiconductor transistor 200, 300: P-type substrate 202, 302: N Type deep well region 2 04: N-type well region 2 0 6, 3 0 8 ·· N-type doped region 2 0 8, 3 1 0 · · P-type doped region 2 1 0, 3 1 2: Isolation structure 3 04 : P-type well area 3 0 6: P-type shallow well area Vdd: Power supply voltage V ss: Ground voltage

12737TWF.PTD Page 15

Claims (1)

1237383 VI. Scope of patent application 1. A junction diode, comprising: a first conductivity type substrate; a second conductivity type buried area disposed in the first conductivity type substrate; a second conductivity type well area, Arranged in the second conductivity type buried region, and the doping concentration of the second conductivity type well region is less than the doping concentration of the second conductivity type buried region; a first conductivity type doped region is arranged in the A surface of the second conductivity type well region; and a second conductivity type doped region disposed on a surface of the second conductivity type buried region. 2. The junction diode according to item 1 of the scope of patent application, wherein the first conductive type substrate is a P-type substrate. 3. The junction diode according to item 1 of the scope of the patent application, wherein the second conductivity-type buried region is an N-type buried region. 4. The bonded diode according to item 1 of the scope of patent application, wherein the second conductive well area is an N-type well area. 5. The bonded diode according to item 1 of the scope of patent application, wherein the second conductivity type well region is an epitaxial layer. 6. The bonded diode according to item 5 of the scope of patent application, wherein the stupid layer is an N-type stupid layer. 7. The junction diode according to item 1 of the scope of patent application, wherein the first conductivity type doped region is a P type doped region. 8. The junction diode as described in item 1 of the patent application scope, wherein 12737TWF.PTD Page 16 1237383 6. Scope of patent application The second conductivity type doped region is an N-type doped region. 9. The junction diode according to item 1 of the scope of the patent application, further comprising a plurality of isolation structures disposed between the first conductive type doped region and the second conductive type doped region. 1 0. A junction diode includes: a first conductive type substrate; a second conductive type deep well region disposed in the first conductive type substrate; a first conductive type well region disposed in the second A conductive type well area; a first conductive type well area is disposed in the first conductive type well area, and the doping concentration of the first conductive type well area is less than the doping concentration of the first conductive type well area ; A plurality of first conductivity type doped regions are disposed on the surface of the first conductivity type well region, and a plurality of second conductivity type doped regions are disposed in the first conductivity type shallow well region and the second conductivity type deep well The surface of the area. 1 1. The junction diode according to item 10 of the scope of patent application, wherein the first conductive type substrate is a P-type substrate. 1 2. The junction diode according to item 10 of the scope of the patent application, wherein the second conductive type deep well region is an N type deep well region. 1 3. The junction diode according to item 10 of the scope of patent application, wherein the first conductive well area is a P-type well area. 1 4. The junction diode as described in item 10 of the patent application scope, wherein 12737TWF.PTD Page 17 1237383 6. Scope of patent application The first conductive type shallow well area is a p-type shallow well area. 15. The junction diode according to item 10 of the scope of the patent application, wherein the first conductivity type doped regions are P type doped regions. 16. The junction diode according to item 10 of the scope of the patent application, wherein the second conductivity type doped regions are N-type doped regions. 1 7. The junction diode described in item 10 of the scope of the patent application, further comprising a plurality of isolation structures, which are arranged in each of the first conductivity type doped regions and the adjacent second conductivity type doped regions. Miscellaneous area between two of them. 12737TWF.PTD Page 18