1237344 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種金屬層-絕緣層-金屬層（Μ I M) 電容的結構與其形成方法，特別是關於一種溝槽式金屬層 -絕緣層-金屬層電容的結構與其形成方法。 【先前技術】 隨著將標準的互補金氧半導體（CMOS)技術應用於類 比與射頻互補金氧半導體（RF CMOS)積體電路領域中的趨 勢，愈來愈多的被動元件因蘊而生。由於利用互補金氧半 導體技術製作的元件具有良好的效能且容易製作，故金屬 層-絕緣層-金屬層（Μ I M)電容被廣泛應用於類比與射頻 的目的中。 第一圖所示為傳統的金屬層-絕緣層-金屬層電容結構 的剖面示意圖。一包含底材的半導體結構11 0上覆蓋Μ I Μ的 底金屬層（bottom metal) 112、一介電層114於底金屬層 11 2之上方。其次，於部分介電層11 4上形成Μ I Μ的頂金屬 層（top metal) 116，且於介電層114與頂金屬層11 6上形 成一金屬間介電層（inter-metal dielectric) 118。金 屬間介電層1 18中形成若干介窗（via) 120，介窗120上再 形成金屬層結構1 2 2。 然而，應用於金屬層-絕緣層-金屬層電容結構中的介 電層厚度遠大於一般多晶石夕-絕緣層-多晶石夕或多晶石夕-絕 緣層-底材電容結構的介電層厚度，導致Μ I Μ電容的比電容 值（specific capacitance)較小。當應用於射頻中且須 考量於Μ I Μ與底材之間的較低麵合雜訊時，需要較高的比1237344 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a structure of a metal layer-insulation layer-metal layer (M IM) capacitor and a method for forming the same, and particularly to a trench-type metal layer- Structure of insulating layer-metal layer capacitor and formation method thereof. [Previous Technology] As standard complementary metal-oxide-semiconductor (CMOS) technology is applied to the field of analog and radio-frequency complementary metal-oxide-semiconductor (RF CMOS) integrated circuits, more and more passive components have emerged as a result. Due to the good performance and easy fabrication of components fabricated using complementary metal-oxide-semiconductor technology, metal layer-insulation layer-metal layer (MM) capacitors are widely used for analog and RF purposes. The first figure shows a schematic cross-sectional view of a conventional metal layer-insulation layer-metal layer capacitor structure. A semiconductor metal structure 110 including a substrate is covered with a bottom metal layer 112 (MI), and a dielectric layer 114 is above the bottom metal layer 112. Secondly, a top metal layer 116 is formed on a part of the dielectric layer 114, and an inter-metal dielectric layer is formed on the dielectric layer 114 and the top metal layer 116. 118. A number of vias 120 are formed in the intermetallic dielectric layer 118, and a metal layer structure 12 is formed on the dielectric window 120. However, the thickness of the dielectric layer used in the metal layer-insulation layer-metal layer capacitor structure is much larger than that of the general polycrystalline silicon-insulating layer-polycrystalline silicon or polycrystalline silicon-insulating layer-substrate capacitor structure. The thickness of the electrical layer results in a smaller specific capacitance of the M I M capacitor. When applied in radio frequency and the lower surface noise between M IM and substrate must be considered, a higher ratio is required
1237344 五、發明說明（2) 電容值成為愈來愈重要的課題之一。 【發明内容】 對於上述，本發明之主要目的係在提供一種溝槽式金 屬層-絕緣層-金屬層電容結構與其形成方法，相較於傳統 的金屬層-絕緣層-金屬層電容結構而言，本發明具有更有 效的面積利用率與比電容值。 本發明之另一目的係在提供一種溝槽式金屬層-絕緣 層-金屬層電容結構與其形成方法，使其於射頻應用的高 頻範圍時，其耦合雜訊較低，以避免Μ I Μ結構與底材之間 的耦合雜訊。 根據上面所述，一種金屬層-絕緣層-金屬層電容結構 利用CMOS的技術製成，半導體結構上先形成金屬間介電層 ，其上再形成一導電層，以作為電容的底金屬層，其中具 有至少一溝槽。之後，介電層共形於導電層上，並覆蓋溝 槽的側壁；再以另一導電層填入溝槽中形成電容的頂金屬 層。此溝槽可以為一螺旋狀或若干獨立的溝槽排列成矩陣 狀。 【實施方式】 參照圖第二A圖所示，在半導體結構1 0上依序形成一 金屬間介電層18與一導電層20，以作為電容的底金屬層， 導電層2 0上則利用一般微影方式，先形成一光阻層2 2後再 進行一溝槽Μ I Μ圖案的移轉。於此實施例中，半導體結構 1 0可包含一矽底材，金屬間介電層1 8可以是一般介電常數 或低介電常數介電層，導電層2 0則可為金屬、金屬化物或1237344 V. Description of the invention (2) The capacitance value has become one of the more and more important topics. [Summary of the Invention] For the above, the main purpose of the present invention is to provide a trench-type metal layer-insulation layer-metal layer capacitor structure and a method for forming the same, as compared with the traditional metal layer-insulation layer-metal layer capacitor structure. The invention has more effective area utilization and specific capacitance. Another object of the present invention is to provide a trenched metal layer-insulation layer-metal layer capacitor structure and a method for forming the trench metal layer-insulation layer-metal layer capacitor structure, so that its coupling noise is low in the high-frequency range of radio frequency applications to avoid Μ I Μ Coupling noise between structure and substrate. According to the above, a metal layer-insulation layer-metal layer capacitor structure is made using CMOS technology. An intermetal dielectric layer is formed on a semiconductor structure, and then a conductive layer is formed thereon as the bottom metal layer of the capacitor. There is at least one trench. After that, the dielectric layer is conformally formed on the conductive layer and covers the sidewall of the trench; and then another conductive layer is filled into the trench to form the top metal layer of the capacitor. This groove can be a spiral or several independent grooves arranged in a matrix. [Embodiment] Referring to FIG. 2A, an intermetal dielectric layer 18 and a conductive layer 20 are sequentially formed on the semiconductor structure 10 as a bottom metal layer of a capacitor, and the conductive layer 20 is used In the general lithography method, a photoresist layer 22 is formed first, and then a trench M IM pattern is transferred. In this embodiment, the semiconductor structure 10 may include a silicon substrate, the intermetallic dielectric layer 18 may be a general dielectric constant or a low dielectric constant dielectric layer, and the conductive layer 20 may be a metal or a metal compound. or
1237344 五、發明說明（3) 合金層，例如鋁銅合金、銅或是氮化鈦。 之後，如第二B圖所示，以具有圖案的光阻層2 2為罩 幕，移除部分導電層2 0以形成若干溝槽並暴露出部分的金 屬間介電層18，再移除光阻層22。接著，共形 (conformal)沉積一 MI Μ之介電層2 4於導電層2 0及暴露出 的金屬間介電層1 8上，並覆蓋溝槽之側壁。於此實施例中 ，光阻層2 2可以為乾膜或液態光阻層，Μ I Μ介電層2 4可以 為矽氧化物、矽氮化物或矽氧氮化物。 在第二C圖中，先沉積一導電層2 6填滿溝槽中並覆蓋 頂部的Μ I Μ介電層2 4，之後再經過一道微影蝕刻的步驟， 移除部分的導電層2 6，剩餘的導電層2 6完全覆蓋於溝槽的 上方，此導電層2 6係作為電容的頂金屬層。於此實施例中 ，導電層2 6可為金屬、金屬化物或合金層，例如铭銅合金 、銅或是氮化鈦，且於所有的溝槽上方成連續的一個區域 ，使得各溝槽中具有電性上的連接。後續則可依習知的方 式，繼續形成金屬層間介電層與介窗連接導電層。 藉由上述之形成方法及第二C圖可知，本發明於一半 導體結構1 0上形成有一金屬間介電層1 8，並有一作為底金 屬層之導電層2 0位於金屬間介電層18上，此導電層20中具 有複數個溝槽以暴露出部分金屬間介電層1 8 ; — Μ I Μ介電 層2 4位於導電層2 0與暴露出的金屬間介電層18表面，並覆 蓋溝槽的側壁；以及一作為頂金屬層之導電層2 6填滿溝槽 並形成於Μ I Μ介電層2 4表面，如此即構成一溝槽式金屬-絕 緣層-金屬（ΜIΜ)電容結構。另外，在導電層2 0中係可形1237344 V. Description of the invention (3) Alloy layer, such as aluminum-copper alloy, copper or titanium nitride. Then, as shown in FIG. 2B, using the patterned photoresist layer 22 as a mask, a part of the conductive layer 20 is removed to form a plurality of trenches and a part of the intermetal dielectric layer 18 is exposed, and then removed Photoresist layer 22. Next, a MI dielectric layer 24 is conformally deposited on the conductive layer 20 and the exposed intermetal dielectric layer 18 to cover the sidewalls of the trench. In this embodiment, the photoresist layer 22 may be a dry film or a liquid photoresist layer, and the MIM dielectric layer 24 may be a silicon oxide, a silicon nitride, or a silicon oxynitride. In the second figure C, a conductive layer 26 is first deposited to fill the trench and cover the top M dielectric layer 24, and then a lithographic etching step is performed to remove a part of the conductive layer 26. The remaining conductive layer 26 completely covers the trench. The conductive layer 26 serves as the top metal layer of the capacitor. In this embodiment, the conductive layer 26 may be a metal, a metal compound, or an alloy layer, such as a copper alloy, copper, or titanium nitride, and is formed in a continuous area above all the trenches, so that With electrical connection. Subsequent methods can continue to form a metal interlayer dielectric layer and a dielectric layer to connect the conductive layer in a conventional manner. It can be known from the above-mentioned formation method and the second C diagram that the present invention forms an intermetal dielectric layer 18 on a semiconductor structure 10, and a conductive layer 20 as a bottom metal layer is located on the intermetal dielectric layer 18 Above, the conductive layer 20 has a plurality of trenches to expose a part of the intermetal dielectric layer 18;-the MI dielectric layer 24 is located on the surface of the conductive layer 20 and the exposed intermetal dielectric layer 18, And a sidewall of the trench is covered; and a conductive layer 26 as a top metal layer fills the trench and is formed on the surface of the MI dielectric layer 24, thus forming a trench metal-insulating layer-metal (ΜIM) ) Capacitor structure. In addition, it is shapeable in the conductive layer 20
第8頁 1237344 五、發明說明（4) 成一個或一個以上的溝槽。 第三圖為根據本發明之一溝槽式金屬層-絕緣層-金屬 層電容結構實施例的正視示意圖。於此實施例中，溝槽圖 案係為矩形溝槽，溝槽2 8各個分開並位於導電層2 0中，因 此作為底金屬層的導電層2 0係彼此之間具有電性上的連接 。可以理解的，溝槽2 8的形狀並不限於圖上所示，圓形或 橢圓形等亦不脫本發明之範疇。 第四圖為根據本發明之另一溝槽式金屬層-絕緣層-金 屬層電容結構實施例的正視示意圖。於此實施例中，溝槽 圖案係為連續的螺旋（spiral)狀，導電層20亦為一連續 結構，故亦具有電性上的連接。根據上述所形成的溝槽式 金屬層-絕緣層-金屬層電容結構，更有效地利用底材上的 面積，達到最大的比電容值，並具有較小的耦合雜訊，很 適合類比與射頻方面的應用。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内 容並據以實施，當不能以之限定本發明之專利範圍，即大 凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵 蓋在本發明之專利範圍内。 【圖號說明】 10 半導體結構 18 金屬間介電層 20 導電層 2 2 光阻層Page 8 1237344 V. Description of the invention (4) One or more grooves. The third figure is a schematic front view of an embodiment of a trench metal layer-insulation layer-metal layer capacitor structure according to the present invention. In this embodiment, the trench pattern is a rectangular trench, and the trenches 28 are separated from each other and are located in the conductive layer 20. Therefore, the conductive layers 20 as the bottom metal layer are electrically connected to each other. It can be understood that the shape of the groove 28 is not limited to that shown in the figure, and the circular or oval shape does not depart from the scope of the present invention. The fourth figure is a schematic front view of another embodiment of a trench-type metal layer-insulation layer-metal layer capacitor structure according to the present invention. In this embodiment, the groove pattern is a continuous spiral shape, and the conductive layer 20 is also a continuous structure, so it also has an electrical connection. According to the trench-type metal layer-insulation layer-metal layer capacitor structure formed above, the area on the substrate is more effectively used to achieve the maximum specific capacitance value and has a small coupling noise, which is very suitable for analog and radio frequency. Applications. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. When the scope of the patent of the present invention cannot be limited, That is, any equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered by the patent scope of the present invention. [Illustration of drawing number] 10 semiconductor structure 18 intermetal dielectric layer 20 conductive layer 2 2 photoresist layer
1237344 五、發明說明（5) 2 4 Μ I Μ介電層 26 導電層 28 溝槽1237344 V. Description of the invention (5) 2 4 Μ I Μ dielectric layer 26 conductive layer 28 trench
第10頁 1237344 圖式簡單說明 第一圖為傳統的金屬層-絕緣層-金屬層電容結構的剖面示 意圖。 第二A圖至第二C圖為本發明之一實施例的形成方法的剖面 示意圖。 第三圖為本發明之一結構實施例的正面示意圖。 第四圖為本發明之另一結構實施例的正面示意圖。Page 10 1237344 Brief description of the drawings The first diagram is a schematic cross-sectional view of a conventional metal layer-insulation layer-metal layer capacitor structure. FIGS. 2A to 2C are schematic cross-sectional views of a forming method according to an embodiment of the present invention. The third figure is a schematic front view of a structural embodiment of the present invention. The fourth figure is a schematic front view of another structural embodiment of the present invention.
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