1236798 Λ7 B7 五、發明說明（1) 發明背景 (請先閱讀背面之注意事項再填寫本頁) 本發明係關於一種匯流排開關。圖1爲習知匯流排開 關之電路圖。 圖1顯示一匯流排開關1 0 1用以選擇兩輸入訊號 I N 1和I N2之一以回應選擇訊號SEL 1和SEL2 和傳送所選擇之訊號至一匯流排線B U S ° 匯流排開關10 1包括兩1^通道^[〇3 (NM〇S) 電晶體102 — 1和102 — 2 °，NM〇S電晶體102 一 1和1 0 2 — 2之一之電流路徑之一端連接至匯流排線 B U S ,電晶體之電流路徑之其它端則連接至它們相關的 輸入線1〇3 — 1和103 — 2。兩緩衝電路104 — 1 和1 0 4 - 2之輸出分別連接至輸入線1 〇 3 一 1和 1 0 3 - 2。輸入訊號I N 1和I N 2分別經由緩衝電路 10 4 一 1和1〇4 — 2和輸入線1〇3 — 1和1〇3 — 2供應至NMOS電晶體1 0 2 — 1和1 0 2 — 2之電流 路徑之其它端。 經濟部智慧財產局員工消費合作社印製 N Μ〇S電晶體1 0 2 — 1和1 〇 2 — 2之閘極分別 經由緩衝電路1 0 5 - 1和1 〇 5 - 2供應以選擇訊號 SEL1和SEL2。爲了回應選擇訊號SEL1和 SEL2, NMOS電晶體1〇2—1和1〇2—2選擇 性的啓動。因此，選擇輸入訊號I N 1和I N 2之一且傳 送至匯流排線B U S。保護二極體1 〇 7 - 1和1 0 7 -2分別連接至輸入線1 〇 3 - 1和1 〇 3 — 2。 由於一系統需要以高速操作，當緩衝電路1 〇 4 - 1 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4- 1236798 A7 ___B7_ 五、發明說明（2) 和1 0 4 - 2之輸出雜訊，特別是輸出位準從高位準變成 低位準時所引起之”下衝”之問題變成相當嚴重。 (請先閱讀背面之注意事項再填寫本頁) 假設緩衝電路1 0 4 - 1之輸出位準下衝且在輸入線 1〇3 — 1中之點A之電壓瞬間下降至約一2 V ,如圖 2A所示。在圖1所示之電路中，連接至輸入線10 3 -丄之保護二極體1 〇 7 - 1當成保護輸入線，和在輸入線 1 0 3 - 1中之點B之電壓切去不高於保護二極體1〇7 一 1之下降順向電壓V F之値，且保持在約一 〇 . 7 V。 但是，構成匯流排開關1 0 1之N Μ〇S電晶體 102 — 1和102 — 2之臨界電壓Vth接近0 · 7V 。因此，當NMOS電晶體102 — 1如圖3所示關閉時 ，如果在圖2 A和2 B中之輸入線1 〇 3 — 1中發生”下衝” 時，N Μ〇S電晶體1 〇 2 — 1之閘極對源極電壓V G S 會超過NMOS電晶體1 〇 2 — 1之臨界電壓V t hB, 且NMOS電晶體1 〇 2 — 1瞬間啓動。 如果匯流排線B U S之電位在高位準時，電流I流向 在低位準上之輸入線1 〇 3 - 1和匯流排線B U S之電位 降低。 經濟部智慧財產局員工消費合作社印製 在匯流排線B U S之電位中之上述下降，其乃在匯流 排開關1 0 1不經意啓動時所引起的，乃是瞬間的。但是 ，爲了以高速操作一系統，在其它電路連接至匯流排線 U S下，即使在電位上之瞬間下降亦會被視爲造成如故 障等不良影響之原因。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -5- 1236798 A7 B7 五、發明說明（3) 發明槪要 本發明乃在考量上述情形下製成。本發明之目的乃在 提供一種匯流排開關，其不會由無可避免應用至以高速操 作之系統之雜訊而不經意的啓動。 爲了達成上目的，依照本發明之第一觀點之匯流排開 關包含：第一和第二接線，至少一接線當成一匯流排線； 保護電晶體連接至至少第一和第二接線之一；和開關電晶 體，具有一電流路徑連接至第一和第二接線，開關電晶體 之臨界電壓高於保護電晶體之臨界電壓。 在依照本發明之第一觀點之匯流排開關中，當在至少 第一和第二接線之一中發生”下衝”時，下衝電壓之一些不高 於保護電晶體之臨界電壓之分量受到去除。 由於開關電晶體之臨界電壓設定成高於保護電晶體之 臨界電壓，在發生’’下衝’’之接線和開關電晶體之閘極間產生 之電壓不會超過開關電晶體之臨界電壓。 結果，即使當在至少第一和第二接線之一中發生”下衝” ，亦可抑制在開關電晶體中之通道形成，和可防止開關電 晶體之不經意啓動。 依照本發明之第二觀點之匯流排開關，包含：第一和 第二接線，至少一接線當成一匯流排線；保護二極體連接 至至少第一和第二接線之一；和開關電晶體，具有一電流 路徑連接至第一和第二接線，其中開關電晶體之臨界電壓 高於保護二極體之下降順向電壓。 在依照本發明之第二觀點之匯流排開關中，開關電晶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂-·· 經濟部智慧財產局員工消費合作社印製 1236798 Λ7 _B7_ 五、發明說明（4) (請先閱讀背面之注意事項再填寫本頁) 體之臨界電壓設定高於保護二極體之下降順向電壓。和在 第一觀點之匯流排相似的，在發生”下衝"之接線和開關電晶 體之閘極間產生之電壓不會超過開關電晶體之臨界電壓。 結果，即使當在至少第一和第二接線之一中發生”下衝’ ，亦可抑制在開關電晶體中之通道形成，和可防止開關電 晶體之不經意啓動，如同第一觀點之匯流排開關。 依照本發明之第三觀點之匯流排開關，包含：第一和 第二接線，至少一接線當成一匯流排線；一保護元件連接 至至少第一和第二接線之一；和開關電晶體，具有一電流 路徑連接至第一和第二接線，其中該保護元件除去當開關 電晶體關閉時介於開關電晶體之閘極和至少第一和第二接 線之一間產生之電壓以降低至低於開關電晶體之臨界電壓 〇 經濟部智慧財產局員工消費合作社印製 在依照本發明之第三觀點之匯流排開關中，保護元件 除去當開關電晶體關閉時介於開關電晶體之閘極和至少第 一和第二接線之一間產生之電壓以降低至低於開關電晶體 之臨界電壓。如同第一和第二觀點之匯流排開關，在發生” 下衝”之接線和開關電晶體之閘極間產生之電壓不會超過開 關電晶體之臨界電壓。 結果，即使當在至少第一和第二接線之一中發生”下衝1 ，亦可抑制在開關電晶體中之通道形成，和可防止開關電 晶體之不經意啓動，如同第一和第二觀點之匯流排開關。 本發明之其它目的和優點將於下述構成本發明之一部 份之說明書中說明，或可由實施本發明而學習到。本發明 本紙張尺度適用中國國家標準（CNS)A4規格(21〇 X 297公爱） 1236798 Λ7 B7 五、發明說明（5 ) 之目的和優點可藉由特別於下述指出之結合或實施而達成 與獲得。 (請先閱讀背面之注意事項再填寫本頁) 圖式簡單說明 由下述之說明伴隨附圖之解說，其中本發明之較佳實 施例以說明例顯示，可更加明瞭本發明之上述和其它目的 ，特徵，和優點。 圖1爲習知匯流排開關之電路圖； 圖2 A和2 B爲說明習知匯流排開關之”下衝”之圖； 圖3爲說明習知匯流排開關之問題之電路圖； 圖4爲依照本發明之第一實施例之匯流排開關之電路 圖， 圖5 A和5 B爲圖4之匯流排開關之，’下衝”之說明圖； 圖6爲說明依照本發明之第一實施例之匯流排開關之 優點之電路圖；和 圖7爲依照本發明之第二實施例之匯流排開關之電路 圖。 經濟部智慧財產局員工消費合作社印製 主要元件對照表 1 0 1 匯流排開關 1 0 2 N通道MOS電晶體 103 輸入線 1 0 4 緩衝電路 105 緩衝電路 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 1236798 Λ7 Β7 五、發明說明（6) 107 保護二極體 1 匯流排開關 (請先閱讀背面之注意事項再填寫本頁) 2 N通道M〇S電晶體 3 輸入線 4 緩衝電路 6 緩衝電路 6 N Μ〇S電晶體 7 Ν Μ〇S電晶體 較佳實施例之詳細說明 以下參考附圖說明本發明之較佳實施例。在圖中，相 同的構成元件以相同的參考數字和符號表示。 (第一實施例） 經濟部智慧財產局員工消費合作社印製 圖4爲依照本發明之第一實施例之匯流排開關1之電 路圖。匯流排開關1以半導體積體電路晶片形成以選擇兩 輸入訊號ΙΝ1和ΙΝ2之一，以回應選擇訊號SEL1 和S E L 2，和傳送所選擇之訊號至匯流排線B U S。匯 流排線B U S安排在電路板上。 匯流排開關1包括兩Ν通道Μ〇S ( Ν Μ〇S )電晶 體2 — 1和2 — 2當成開關電晶體。Ν Μ〇S電晶體2 — 1和2 - 2之電流路徑之一端連接至匯流排線B U S，電 流路徑之其它端則分別連接至兩輸入線3 - 1和3 — 2。 兩緩衝電路4 — 1和4 — 2之輸出分別連接至輸入線3 - -9 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1236798 Λ7 _____ B7________ 五、發明說明（7 ) (請先閱讀背面之注意事項再填寫本頁) 1和3 — 2。輸入訊號I N 1和I N 2分別經由緩衝電路 4 一 1和4 — 2和輸入線3 - 1和3 — 2供應至NMOS 電晶體2 - 1和2 - 2之電流路徑之其它端。緩衝電路4 - 1和4 - 2以非形成有匯流排開關1之半導體積體電路 晶片之晶片形成。 N Μ 0 S電晶體2 - 1和2 - 2之閘極分別經由緩衝 電路5—1和5-2供應以選擇訊號SEL1和SEL2 。爲了回應選擇訊號SEL1和SEL2，NMOS電晶 體2-1和2—2選擇性的啓動。因此，選擇輸入訊號 I Ν 1和I Ν 2之一且傳送至匯流排線B U S。二極體連 接NM〇S電晶體6 - 1和6 — 2之每一·個當成一輸入保 護元件乃連接至它們相關接線以在一端連接Ν Μ〇S電晶 體2 - 1和2 — 2至匯流排線B U S。相似的，二極體連 接保護NM〇S電晶體NMOS 7 — 1和7 — 2分別連接 至輸入線3 — 1和3 — 2。緩衝電路5 - 1和5 — 2和保 護NMOS 電晶體 6 — 1，6 — 2, 7 — 1，和 7 — 2 形 成在形成有匯流排開關1之相同晶片上。 經濟部智慧財產局員工消費合作社印製 保護Ν Μ〇S電晶體6 — 1和6 — 2之電流路徑在一 端上連接至用以連接NM〇S電晶體2 — 1和2 — 2之電 流路徑至在一端上之匯流排線B U S之相關接線，而 NM〇S電晶體6 - 1和6 _ 2之電流路徑在另一端上連 接至電源端，如一接地端V s s。Ν Μ〇S電晶體6 — 1 和6 - 2之閘極連接至它們相關接地端V s s。因此，保 護Ν Μ〇S電晶體6 — 1和6 — 2 —般關閉。 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1236798 Λ7 Β7 五、發明說明（8) (請先閱讀背面之注意事項再填寫本頁) 保護N Μ〇S電晶體7 — 1和7 - 2之電流路徑在一 端連接至它們相關輸入線3 - 1和3 - 2，和在另一端連 接至它們相關的電源端，如接地端V s s。Ν Μ〇S電晶 體7 - 1和7 — 2之聞極連接至接地端V s s。和上述 Ν Μ〇S電晶體6 — 1和6 — 2相似的，保護Ν Μ〇S電 晶體7 - 1和7 — 2 —般關閉。 在第一實施例中，保護Ν Μ〇S電晶體6 — 1，6 — 2， 7-1，和7-2之臨界電壓VthA設定成低於構 成匯流排開關1之Ν Μ〇S電晶體2 - 1和2 — 2之臨界 電壓V t h Β。 假設在匯流排開關1中，緩衝電路4-1之輸出位準 下衝和在輸入線3 - 1中之點A之電壓瞬間下降至約 —2V，如圖5A所示。保護NMOS電晶體7— 1,其 連接至輸入線3 - 1，當成保護輸入訊號，和在輸入線3 一 1中之點B之電壓除去不高於保護NM〇S電晶體7 — 1之臨界電壓V t h之値，和保持在約一 V t hA。 如上所述，臨界電壓V t h B設定高於在匯流排開關 1中之臨界電壓V t hA。因此，當NMOS電晶體2 — 經濟部智慧財產局員工消費合作社印製 1關閉如圖6所示時，即使在圖5 A和5 B之輸入線3 — 1中發生”下衝"時，Ν Μ〇S電晶體2 - 1之閘極對源極電 壓V G S不會超過臨界電壓。 結果，即使在輸入線3 — 1和3 - 2中發生”下衝”，亦 可抑制在Ν Μ〇S電晶體中之通道形成，和可防止這些電 晶體之不經意啓動。 -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1236798 經濟部智慧財產局員工消費合作社印製 Λ7 B7 五、發明說明（9) 在第一實施例中，二極體連接NM〇S電晶體6 - 1 和6 - 2連接至它們相關的接線，該接線在一端上用以連 接N Μ〇s電晶體2 - 1和2 - 2之電流路徑至匯流排線 。於此無需提供保護Ν Μ〇S電晶體6 - 1和6 - 2之任 一者，但是，Ν Μ〇S電晶體6 — 1和6 — 2可引進即使 當在匯流排線B U S中發生，，下衝”時，抑制在Ν Μ〇S電晶 體2-1和2-2中形成通道之優點。 上述第一實施例之匯流排開關，其可防止Ν Μ〇S電 晶體2 - 1和2 — 2免於不經意啓動，乃可有效的使用以 降低在以高速操作之系統中之故障。 (第二實施例） 圖7爲依照本發明之第二實施例之匯流排開關之電路 圖。 如圖7所示，第二實施例之匯流排開關和第一實施例 之不同點在於：使用保護二極體6 ’ — 1，6 ’ — 2 , 7 ’ — 1，和7 ’ 一 2以取代保護Ν Μ〇S電晶體6 — 1 , 6 — 2 ，7 - 1，和7 - 2，且連接至接線，該接線用以連接 Ν Μ〇S電晶體2 - 1和2 — 2至匯流排線和輸入線3 — 1和3 — 2。NMOS電晶體2 — 1和2 — 2之臨界電壓 VthB設定成高於保護二極體6’— 1, 6’— 2，7’ — 1，和7 ’ 一 2之下降順向電壓V F。 依照第二實施例，當在輸入線3 - 1和3 — 2中發生” 下衝’’時，輸入線3 - 1和3 - 2之電壓可去除以下降至下 ----ί-------· I------^ --------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -12- 1236798 A7 ___ B7 _ 五、發明說明（1〇) 降順向電壓v F。 (請先閱讀背面之注意事項再填寫本頁) NM〇S電晶體2 — 1和2 — 2之臨界電壓V t hB 設定成高於下降順向電壓V F。因此，當在輸入線3 - 1 和3 — 2中發生”下衝”時，N Μ〇S電晶體2 — 1和2 — 2 之閘極對汲極電壓V G S不會超過臨界電壓V t h Β。 如同第一實施例，即使當在輸入線3 — 1和3 - 2中 發生”下衝”時，亦可抑制在N Μ〇S電晶體2 - 1和2 - 2 中之通道形成，和可防止這些電晶體之不經意啓動。 本發明並不限於第一和第二實施例所述。於此仍可達 成許多改變和修飾，但是它們仍未脫離本發明之主題之範 疇。 第一和第二實施例係針對一種匯流排開關以連接輸入 線至一匯流排線。但是，本發明亦可應用至用以一起連接 匯流排線之匯流排開關，用以連接一匯流排線至積體電路 之輸入線之匯流排開關等。 經濟部智慧財產局員工消費合作社印製 在第一和第二實施例中，匯流排線B U S形成在電路 板上，且匯流排開關1和緩衝電路4 一 1和4 一 2形成在 不同晶片上。但是，無庸贅言的是，它們亦可形成在單一 晶片上。 本發明並不限於上述之實施例，且於此仍可達成各種 改變和修飾，但其仍屬本發明之精神和範疇。因此，本發 明之精神和範疇應由下述申請專利範圍界定之。 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）1236798 Λ7 B7 V. Description of the invention (1) Background of the invention (Please read the notes on the back before filling out this page) The invention relates to a bus switch. Figure 1 is a circuit diagram of a conventional bus switch. Figure 1 shows a bus switch 1 0 1 for selecting one of the two input signals IN 1 and I N2 in response to the selection signals SEL 1 and SEL2 and transmitting the selected signal to a bus line BUS ° bus switch 10 1 includes Two 1 ^ channels ^ [〇3 (NM〇S) transistors 102-1 and 102-2 °, one end of the current path of one of the NMOS transistors 102-1 and 102-2 is connected to the busbar BUS, the other ends of the transistor's current path are connected to their associated input lines 103-1 and 103-2. The outputs of the two buffer circuits 104 — 1 and 10 4-2 are connected to the input lines 1 0 3 1 and 10 3-2 respectively. The input signals IN 1 and IN 2 are supplied to the NMOS transistors 1 0 2 — 1 and 1 0 2 — via the buffer circuits 10 4 — 1 and 10 4 — 2 and the input lines 10 3 — 1 and 10 3 — 2 respectively. The other end of the current path of 2. Printed N MOS transistor 1 0 2 — 1 and 1 0 2 — 2 gates of the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives are supplied via buffer circuits 1 0 5-1 and 1 0 5-2 to select the signal SEL1 And SEL2. In response to the selection signals SEL1 and SEL2, the NMOS transistors 10-2 and 10-2 are selectively activated. Therefore, one of the input signals I N 1 and I N 2 is selected and transmitted to the bus line B U S. The protective diodes 10-7-1 and 10-7-2 are connected to the input lines 10-3-1 and 10-3-2, respectively. Because a system needs to operate at high speed, when the buffer circuit 1 〇 04-1 this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -4- 1236798 A7 ___B7_ 5. Description of the invention (2) and 1 The 0-4-2 output noise, especially the "undershoot" problem caused when the output level changes from a high level to a low level, becomes quite serious. (Please read the precautions on the back before filling this page) Suppose that the output level of the buffer circuit 1 0 4-1 undershoots and the voltage at point A in the input line 103-1 drops to about -2 V instantaneously, As shown in Figure 2A. In the circuit shown in FIG. 1, the protection diode 1 〇 7-1 connected to the input line 10 3-丄 is regarded as the protection input line, and the voltage at point B in the input line 1 0 3-1 is not cut off. 7 V。 Higher than the protection diode 10-7 -1 drop forward voltage VF, and maintained at about 10.7V. However, the threshold voltages Vth of the NMOS transistors 102-1 and 102-2 constituting the bus switch 101 are close to 0.7V. Therefore, when the NMOS transistor 102-1 is turned off as shown in FIG. 3, if a "undershoot" occurs in the input line 1 03-1 in Figs. 2A and 2B, the NMOS transistor 1 〇 The gate-to-source voltage VGS of 2 — 1 will exceed the threshold voltage V t hB of the NMOS transistor 1 0 — 2 and the NMOS transistor 1 2 — 1 will start instantly. If the potential of the bus line B U S is at a high level, the current I flows to the input line 103-1 at a low level and the potential of the bus line B U S decreases. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The above-mentioned drop in the potential of the bus bar B U S is caused by the inadvertent activation of the bus switch 101, which is instantaneous. However, in order to operate a system at high speed, even if the other circuits are connected to the bus bar U S even if the voltage drops momentarily, it will be regarded as the cause of adverse effects such as failure. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -5- 1236798 A7 B7 V. Description of the invention (3) Summary of the invention The invention is made in consideration of the above circumstances. It is an object of the present invention to provide a bus switch that is not inadvertently activated by noise that is unavoidably applied to a system operating at high speed. In order to achieve the above object, the bus switch according to the first aspect of the present invention includes: first and second wirings, at least one wiring being regarded as one bus wiring; a protection transistor connected to at least one of the first and second wirings; and The switching transistor has a current path connected to the first and second wirings. The critical voltage of the switching transistor is higher than the critical voltage of the protection transistor. In the bus switch according to the first aspect of the present invention, when "undershoot" occurs in at least one of the first and second wirings, some of the undershoot voltage is not higher than the critical voltage of the protection transistor. Remove. Since the threshold voltage of the switching transistor is set higher than the threshold voltage of the protection transistor, the voltage generated between the wiring where the 'undershoot' occurs and the gate of the switching transistor will not exceed the threshold voltage of the switching transistor. As a result, even when "undershoot" occurs in at least one of the first and second wirings, formation of a channel in the switching transistor can be suppressed, and inadvertent activation of the switching transistor can be prevented. A bus switch according to a second aspect of the present invention includes: first and second wirings, at least one wiring being regarded as a bus line; a protection diode connected to at least one of the first and second wirings; and a switching transistor Has a current path connected to the first and second wirings, wherein the critical voltage of the switching transistor is higher than the falling forward voltage of the protection diode. In the bus switch according to the second aspect of the present invention, the paper size of the switch transistor is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order -·· Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1236798 Λ7 _B7_ V. Description of Invention (4) (Please read the precautions on the back before filling this page) The threshold voltage of the body is set higher than that of the protection diode向 volt. Similar to the busbar in the first point of view, the voltage generated between the "undershoot" wiring and the gate of the switching transistor will not exceed the critical voltage of the switching transistor. As a result, even when at least the first and The occurrence of "undershoot" in one of the second wires can also inhibit the formation of channels in the switching transistor, and can prevent inadvertent activation of the switching transistor, like the bus switch of the first aspect. A bus switch according to a third aspect of the present invention includes: first and second wirings, at least one wiring being regarded as a bus line; a protection element connected to at least one of the first and second wirings; and a switching transistor, Having a current path connected to the first and second wirings, wherein the protection element removes a voltage generated between the gate of the switching transistor and at least one of the first and second wirings to reduce to a low level when the switching transistor is turned off The threshold voltage of the switching transistor is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the bus switch according to the third aspect of the present invention, the protection element is removed when the switching transistor is turned off. A voltage generated between at least one of the first and second wirings is lowered below a threshold voltage of the switching transistor. Like the bus switches of the first and second aspects, the voltage generated between the “undershoot” wiring and the gate of the switching transistor will not exceed the critical voltage of the switching transistor. As a result, even when "undershoot 1" occurs in at least one of the first and second wiring, the formation of a channel in the switching transistor can be suppressed, and inadvertent activation of the switching transistor can be prevented, as in the first and second viewpoint The other purpose and advantages of the present invention will be described in the following description constituting a part of the present invention, or can be learned by implementing the present invention. The paper size of the present invention is applicable to the Chinese National Standard (CNS) A4 Specifications (21〇X 297 public love) 1236798 Λ7 B7 5. The purpose and advantages of the invention description (5) can be achieved and obtained through the combination or implementation of the following special points. (Please read the notes on the back before filling (This page) The drawings are briefly explained by the following description accompanied by the accompanying drawings, in which the preferred embodiments of the present invention are shown by way of illustrative examples, which can better understand the above and other objects, features, and advantages of the present invention. Figure 1 is Circuit diagram of a conventional bus switch; Figures 2 A and 2 B are diagrams illustrating the "undershoot" of a conventional bus switch; Figure 3 is a circuit diagram illustrating the problem of a conventional bus switch; The circuit diagram of the bus switch according to the first embodiment of the present invention, FIG. 5A and 5B are explanatory diagrams of the “undershoot” of the bus switch of FIG. 4; FIG. 6 is a diagram illustrating a first embodiment according to the present invention A circuit diagram of the advantages of the bus switch; and FIG. 7 is a circuit diagram of the bus switch according to the second embodiment of the present invention. The comparison table of the main components printed by the employees ’cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 0 1 Bus switch 1 0 2 N-channel MOS transistor 103 Input line 1 0 4 Buffer circuit 105 Buffer circuit -8- CNS) A4 size (210 x 297 mm) 1236798 Λ7 Β7 V. Description of the invention (6) 107 Protection diode 1 Bus switch (Please read the precautions on the back before filling this page) 2 N channel M0S power Crystal 3 Input line 4 Buffer circuit 6 Buffer circuit 6 N MOS transistor 7 N MOS transistor Detailed description of preferred embodiments The following describes preferred embodiments of the present invention with reference to the drawings. In the drawings, the same constituent elements are denoted by the same reference numerals and symbols. (First Embodiment) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Fig. 4 is a circuit diagram of the bus switch 1 according to the first embodiment of the present invention. The bus switch 1 is formed of a semiconductor integrated circuit chip to select one of the two input signals IN1 and IN2, in response to the selection signals SEL1 and S E L 2, and transmits the selected signal to the bus line B U S. The bus lines B U S are arranged on a circuit board. The bus switch 1 includes two N-channel MOS (N MOS) transistor 2-1 and 2-2 as switching transistors. One end of the current path of the NMOS transistor 2-1 and 2-2 is connected to the bus line BUS, and the other ends of the current path are connected to the two input lines 3-1 and 3-2, respectively. The outputs of the two buffer circuits 4 — 1 and 4 — 2 are connected to the input lines 3--9-This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1236798 Λ7 _____ B7________ 5. Description of the invention ( 7) (Please read the notes on the back before filling out this page) 1 and 3-2. The input signals I N 1 and I N 2 are supplied to the other ends of the current paths of the NMOS transistors 2-1 and 2-2 via the buffer circuits 4-1 and 4-2 and the input lines 3-1 and 3-2, respectively. The buffer circuits 4-1 and 4-2 are formed of wafers other than the semiconductor integrated circuit wafer on which the busbar switch 1 is formed. The gates of the N M 0 S transistors 2-1 and 2-2 are supplied via buffer circuits 5-1 and 5-2 to select signals SEL1 and SEL2, respectively. In response to the selection signals SEL1 and SEL2, the NMOS transistors 2-1 and 2-1 are selectively activated. Therefore, one of the input signals I Ν 1 and I Ν 2 is selected and transmitted to the bus line B U S. Diodes each of NMOS transistors 6-1 and 6-2 as an input protection element are connected to their associated wiring to connect N MOS transistors 2-1 and 2-2 to Bus line BUS. Similarly, the diode connection protection NMOS transistor NMOS 7-1 and 7-2 are connected to the input lines 3-1 and 3-2, respectively. The snubber circuits 5-1 and 5-2 and the protection NMOS transistors 6-1, 6-2, 7-1, and 7-2 are formed on the same chip on which the bus switch 1 is formed. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints and protects the current paths of NMMOS transistors 6-1 and 6-2 at one end connected to the current paths used to connect NMOS transistors 2-1 and 2-2. The relevant wiring to the bus bar BUS on one end, and the current path of the NMOS transistor 6-1 and 6 _ 2 is connected to the power supply terminal on the other end, such as a ground terminal V ss. The gates of the NMOS transistors 6-1 and 6-2 are connected to their associated ground terminals Vss. Therefore, the protection NMOS transistors 6-1 and 6-2 are generally turned off. -10- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 1236798 Λ7 Β7 V. Description of the invention (8) (Please read the precautions on the back before filling this page) Protect N M〇S The current paths of transistors 7-1 and 7-2 are connected at one end to their associated input lines 3-1 and 3-2, and at the other end to their associated power terminals, such as the ground terminal Vss. The MOS electrodes of the MOS transistors 7-1 and 7-2 are connected to the ground terminal V s s. Similar to the above NMOS transistors 6-1 and 6-2, the protection NMOS transistors 7-1 and 7-2 are generally closed. In the first embodiment, the threshold voltages VthA of the NMOS transistors 6-1, 6-2, 7-1, and 7-2 are set to be lower than the NMOS transistors that constitute the bus switch 1. The threshold voltages V th Β of 2-1 and 2-2. Assume that in the bus switch 1, the output level of the buffer circuit 4-1 undershoots and the voltage at the point A in the input line 3-1 drops to about -2V instantaneously, as shown in FIG. 5A. Protect NMOS transistor 7-1, which is connected to input line 3-1, as a protection input signal, and the voltage at point B in input line 3-1 is not higher than the threshold of protecting NMOS transistor 7-1 The sum of the voltage V th is maintained at about one V t hA. As described above, the threshold voltage V t h B is set higher than the threshold voltage V t hA in the bus switch 1. Therefore, when the NMOS transistor 2 — Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 1 is closed as shown in FIG. 6, even when “undershoot” occurs in the input lines 3 — 1 of FIGS. 5 A and 5 B, The gate-to-source voltage VGS of the NM MOS transistor 2-1 will not exceed the critical voltage. As a result, even if "undershoot" occurs in the input lines 3-1 and 3-2, it can be suppressed at NM. The formation of channels in the S transistor can prevent the accidental activation of these transistors. -11-This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1236798 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System Λ7 B7 V. Description of the invention (9) In the first embodiment, the diodes are connected to NMOS transistors 6-1 and 6-2 to their associated wirings, which are connected at one end to N M 〇s transistor 2-1 and 2-2 current path to the busbar. There is no need to provide protection for any of the MOS transistor 6-1 and 6-2, but the NM transistor 6 — 1 and 6 — 2 can be introduced even when it occurs in the busbar BUS. The advantage of channel transistor electrically 〇S 2-1 and 2-2 are formed. The bus switch of the first embodiment described above, which can prevent NMOS transistors 2-1 and 2-2 from accidental startup, can be effectively used to reduce malfunctions in a system operating at high speed. (Second Embodiment) Fig. 7 is a circuit diagram of a bus switch according to a second embodiment of the present invention. As shown in FIG. 7, the bus switch of the second embodiment is different from the first embodiment in that the protection diodes 6 ′-1, 6 ′ 2, 7 ′ 1, and 7 ′ 2 are used. Instead of protecting the NMOS transistor 6-1, 6-2, 7-1, and 7-2, it is connected to a wiring for connecting the NMOS transistor 2-1 and 2-2 to the bus Cable and input lines 3-1 and 3-2. The threshold voltages VthB of the NMOS transistors 2-1 and 2-2 are set higher than the forward voltages V F of the protection diodes 6 '-1, 6'-2, 7 '-1, and 7'-2. According to the second embodiment, when "undershoot" occurs in the input lines 3-1 and 3-2, the voltage of the input lines 3-1 and 3-2 can be removed by the following and dropped to ------ ----- · I ------ ^ --------- (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -12- 1236798 A7 ___ B7 _ V. Description of the invention (1〇) Decrease forward voltage v F. (Please read the notes on the back before filling this page) NM〇S transistor 2 — 1 and 2 — The threshold voltage V t hB of — 2 is set higher than the falling forward voltage VF. Therefore, when “undershoot” occurs in the input lines 3-1 and 3-2, the N MOS transistors 2-1 and 2 — The gate-to-drain voltage VGS of — 2 does not exceed the threshold voltage V th Β. As in the first embodiment, even when “undershoot” occurs in the input lines 3-1 and 3-2, it can be suppressed at N The formation of channels in the MOS transistors 2-1 and 2-2 can prevent the inadvertent activation of these transistors. The invention is not limited to the first and second embodiments. Many changes and Grooming, but it It still does not depart from the scope of the subject matter of the present invention. The first and second embodiments are directed to a bus switch for connecting an input line to a bus line. However, the present invention can also be applied to a bus for connecting bus lines together. Bus switch, used to connect a bus bar to the input line of the integrated circuit, etc. Busbar switch, etc. printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In the first and second embodiments, the bus bar BUS is formed in the circuit Board, and the bus switch 1 and the buffer circuit 4-1 and 4-2 are formed on different chips. However, it goes without saying that they can also be formed on a single chip. The present invention is not limited to the above embodiments, Various changes and modifications can still be achieved here, but they still belong to the spirit and scope of the present invention. Therefore, the spirit and scope of the present invention should be defined by the scope of the following patent applications. -13- This paper size applies Chinese national standards (CNS) A4 size (210 X 297 mm)