1236755 玖、發明說明 【發明所屬之技術領域】 本發明是有關於一種銲錫凸塊結構，且特別是有關於 一種覆晶封裝的銲錫凸塊結構。 【先前技術】1236755 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a solder bump structure, and more particularly, to a flip chip package solder bump structure. [Prior art]
PiC者半導體技術的發展及產品功能的多樣化，元件構 裝（Packaging)技術的種類也越來越多變，以符合不同的需 求。傳統晶片與基板間藉由打線（w i r e - b 〇 n d i n g )的訊號傳 遞方式，已成為高速性能IC的發展的瓶頸。為了解決此 一問題並配合1C製程的快速發展，業界採用了覆晶接合 (Flip-Chip Packaging)的方式。 因為接合材料的不同可分為金屬接合和非金屬接合 兩種，其中金屬接合材料包含銲錫凸塊（S〇lder bump)和金 凸塊（Gold bump)等，非金屬接合材料包含導電膠 (Electrical Conductive Adhesive; ECA)和異向性導電膜 (Anisotropic Conductive Film; aCF)，目前仍就以銲錫凸 塊為最大宗。 而不論疋那一種覆晶技術，凸塊（bump)的製作是少不 了的，凸塊的電子和機械特性關係到覆晶構裝結果的好 壞。因此，構裝技術的提供者莫不極力的改進凸塊電子和 機械特性，以滿足客戶需要的規格。 1236755 【發明内容】 因此本發明的目的就是在提供一種覆晶封裝的銲錫 凸塊結構’用以改善銲錫凸塊結構的機械特性。 據本發明之上述目的，提出一種覆晶封裝銲錫凸塊 結構至少包含半導體積體電路，其上已覆蓋-氮化石夕 濩層及一鋁銲墊；高分子材料層，位於氮化矽護層及鋁銲 墊之上方，且位於鋁銲墊上之高分子材料層和位於氮化矽 護層之高分子材料層之中具有一間隙；一凸塊底層金屬 層，覆蓋於鋁銲墊及氮化矽上之高分子材料層及高分子材 料層間的間隙上；以及一銲錫結構，覆蓋於凸塊底層金屬 上。 依照本發明一較佳實施例，凸塊底層金屬層包含黏著 層、擴散阻絕層、潤濕接合層或抗氧化層。黏著層的材料 可以是鈦（Ti)、鉻（Cr)、銅（Cu)或钽（Ta)。擴散阻絕層的 材料的選擇包含銅（Cu)、鎳（Ni)、鈦（Ti)、鉻（Cr)、钽 (Ta)或鎢化鈦（Tiw)。上述的凸塊底層金屬層係以真空濺 鍍、真空蒸錄或電鍍方法製作。 由上述可知，本發明之銲踢凸塊結構中，内含有高分 子材料，可使銲錫凸塊結構承受更大擠壓的應力而不被破 壞，並且改善機械性質。 【實施方式】 1236755 本發明的重點在於改良銲錫凸塊結構的機械特性，使 用的方法是在銲錫凸塊結構中，形成一緩衝的結構，使晶 片在覆晶封裝的製程中，銲錫凸塊結構可以承受擠壓的應 力而結構不破壞。以下藉由實施例和圖示來進一步說明本 發明之銲錫凸塊結構及其製造方法。 請參照第1圖，其繪示依照本發明一較佳實施例的一 種尚未封裝的晶片示意圖。圖中繪示一已完成積體電路製 程但尚未封裝的晶片剖面。積體電路1 〇上覆蓋了氮化矽 (ShN4)護層12及鋁銲墊14。氮化矽（Si3N4)護層用來保護 積體電路免於水氣和機械性質傷害，鋁銲墊14則是積體 電路輸入和輸出的接觸點。 請參照第2-7圖，其繪示依照本發明一較佳實施例的 在干錫凸塊結構製造流程晶片剖面示意圖。在2圖中，在已 完成積體電路上形成一高分子材料層16(P〇lymer or Polyamide)，再用蝕刻的方法只留下鋁銲墊14上部份的 咼分子材料16’且和兩旁的高分子材料16具有一間隙 1 5。在第3圖中’在經光學或餘刻製程後的高分子材料層 16上’應用真空錢鍍、真空蒸鑛或電鑛方法等方法形成 一黏著層（Adhesion layer)18。黏著層18的材料可以是鈦 (Ti)、鉻（Cr)、銅（Cxi)或鈕（Ta)。在第4-5圖中，其緣示 在黏著層1 8上形成擴散阻絕層（Diffusion Bar：riei· Layer) 的步驟。先用光阻層20定義出欲形成擴散阻絕層的位 1236755 置，再用真空濺鑛、化學鍍或電鍍填入擴散阻絕層22金 屬。適用於擴散阻絕層22的金屬包含銅（Cu)、鎳（Ni)、鈦 (τ〇 、鉻（ο)、鈕（Ta)或鎢化鈦（Tiw)。以上所述之黏著 層18和擴散阻絕層22通常稱作凸塊底層金屬層（Under Bump Metallurgy，UBM)。凸塊底層金屬層的功能不外乎 黏著層、擴散阻絕層、潤濕接合層或抗氧化層。在本發明 實施時，可依不同需求改變凸塊底層金屬的材料。 在第6圖中，繼續在光阻層2〇所定義出之擴散阻絕 層的上方，植入銲錫材料（銲錫結構）。接著在第7圖中， 移除光阻層和高分子材料層16上方的黏著層18。移除的 方法是以钱刻的方式去除。 請參照第8圖，其繪示依照本發明一較佳實施例的一 ，銲錫凸塊結構示意圖。第7圖中的銲錫凸塊結構經過適 當的加熱重流（Reflow0《可以形成如第8圖的結構。 由上述本發明較佳實施例可知，本發明之銲錫凸塊結 構中，内含有高分子材料，可使銲錫凸塊結構承受更大擠 壓的應力而結構不破壞，且機械性質也具有彳艮大的改善。 、雖然本發明已以一較佳實施例揭露如上，然其並非用 M限定本發明，任何熟習此技藝者，在不脫離本發明之精 =和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 1236755 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易僅’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1圖係繪示依照本發明一較佳實施例的一種尚未 封裝的晶片示意圖； 第2-7圖係繪示依照本發明一較佳實施例的銲錫凸 塊結構製造流程晶片剖面示意圖；以及 第8圖係繪示依照本發明一較佳實施例的一種銲錫 凸塊結構示意圖。 【元件代表符號簡單說明】 1〇 :積體電路 1 2 :氮化石夕護層 14 :紹銲墊 15 :間隙 16:高分子材料層 18 :黏著層 20 :光阻層 22 ·擴散阻絕層 24 :銲錫結構The development of PiC semiconductor technology and the diversification of product functions, the types of component packaging (Packaging) technology are also more and more varied to meet different needs. The signal transmission method between the conventional wafer and the substrate by wire (wier-bon d i n g) has become the bottleneck of the development of high-speed performance ICs. In order to solve this problem and cooperate with the rapid development of the 1C process, the industry has adopted Flip-Chip Packaging. Because the difference in bonding materials can be divided into two types: metal bonding and non-metal bonding. Metal bonding materials include solder bumps and gold bumps. Non-metal bonding materials include conductive adhesives. Conductive Adhesive (ECA) and Anisotropic Conductive Film (acf) are still the largest block of solder bumps. Regardless of the flip chip technology, bump production is indispensable. The electronic and mechanical characteristics of bumps are related to the quality of flip chip assembly. Therefore, the provider of fabrication technology has worked hard to improve the electrical and mechanical characteristics of the bumps to meet customer specifications. 1236755 [Summary of the invention] Therefore, an object of the present invention is to provide a solder bump structure of a flip-chip package 'to improve the mechanical characteristics of the solder bump structure. According to the above object of the present invention, a flip-chip package solder bump structure at least includes a semiconductor integrated circuit, which is covered with a nitride nitride layer and an aluminum pad; a polymer material layer located on the silicon nitride protective layer. There is a gap between the polymer material layer on the aluminum pad and the polymer material layer on the silicon nitride protective layer; and a bump bottom metal layer covering the aluminum pad and the nitride A polymer material layer on silicon and a gap between the polymer material layers; and a solder structure covering the underlying metal of the bump. According to a preferred embodiment of the present invention, the bump bottom metal layer includes an adhesion layer, a diffusion barrier layer, a wetting bonding layer, or an anti-oxidation layer. The material of the adhesive layer may be titanium (Ti), chromium (Cr), copper (Cu) or tantalum (Ta). The material of the diffusion barrier layer includes copper (Cu), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), or titanium tungsten (Tiw). The above bump metal layer is made by vacuum sputtering, vacuum evaporation or electroplating. From the above, it is known that the solder bump structure of the present invention contains a high-molecular material, which enables the solder bump structure to withstand greater crushing stress without being damaged, and improves mechanical properties. [Embodiment] 1236755 The focus of the present invention is to improve the mechanical characteristics of the solder bump structure. The method used is to form a buffer structure in the solder bump structure, so that the chip has a solder bump structure during the flip-chip packaging process. Can withstand the stress of extrusion without damaging the structure. Hereinafter, the solder bump structure of the present invention and a manufacturing method thereof will be further described by way of examples and drawings. Please refer to FIG. 1, which illustrates a schematic diagram of an unpackaged chip according to a preferred embodiment of the present invention. The figure shows a cross section of a chip that has completed the integrated circuit process but has not yet been packaged. The integrated circuit 10 is covered with a silicon nitride (ShN4) protective layer 12 and an aluminum pad 14. The silicon nitride (Si3N4) protective layer is used to protect the integrated circuit from moisture and mechanical damage. The aluminum pad 14 is the contact point of the input and output of the integrated circuit. Please refer to FIGS. 2-7, which are schematic cross-sectional views of a wafer in a dry bump structure manufacturing process according to a preferred embodiment of the present invention. In FIG. 2, a polymer material layer 16 (Polymer or Polyamide) is formed on the completed integrated circuit, and only a part of the plutonium molecular material 16 ′ on the aluminum pad 14 is left by etching, and The polymer material 16 on both sides has a gap 15. In Fig. 3, an "adhesion layer" 18 is formed on the polymer material layer 16 after the optical or post-etching process by vacuum plating, vacuum evaporation, or electric ore method. The material of the adhesive layer 18 may be titanium (Ti), chromium (Cr), copper (Cxi), or button (Ta). In Figures 4-5, the edges show the steps of forming a diffusion barrier layer (Dii ·· Layer) on the adhesive layer 18. First use the photoresist layer 20 to define the position 1236755 where the diffusion barrier layer is to be formed, and then fill the diffusion barrier layer 22 with metal by vacuum sputtering, electroless plating or electroplating. Suitable metals for the diffusion barrier layer 22 include copper (Cu), nickel (Ni), titanium (τ0, chromium (ο), button (Ta), or titanium tungsten (Tiw). The adhesion layer 18 and diffusion described above The barrier layer 22 is commonly referred to as an Under Bump Metallurgy (UBM). The function of the bump bottom metal layer is nothing more than an adhesive layer, a diffusion barrier layer, a wetting joint layer, or an anti-oxidation layer. When the present invention is implemented, The material of the underlying metal of the bump can be changed according to different needs. In Figure 6, continue to implant solder material (solder structure) on top of the diffusion barrier layer defined by the photoresist layer 20. Then in Figure 7 In the process, the photoresist layer and the adhesive layer 18 above the polymer material layer 16 are removed. The method of removing is to remove money. Please refer to FIG. 8, which illustrates a first embodiment according to a preferred embodiment of the present invention. Schematic diagram of solder bump structure. The solder bump structure in Figure 7 is reflowed after appropriate heating (Reflow0 "can form the structure shown in Figure 8. From the above-mentioned preferred embodiment of the present invention, it can be seen that the solder bump of the present invention In the structure, it contains polymer materials, which can make the solder bump The structure can withstand greater compression stress without damaging the structure, and the mechanical properties are also greatly improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not limited to the present invention by M, anyone familiar with this Artists, without departing from the spirit of the present invention, can make various modifications and retouches, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. 1236755 [Schematic description of the drawings In order to make the above and other objects, features, and advantages of the present invention more obvious and easy, only a preferred embodiment is given below, and it is described in detail with the accompanying drawings as follows: FIG. A schematic diagram of an unpackaged wafer according to a preferred embodiment of the present invention; FIGS. 2-7 are schematic cross-sectional diagrams of a wafer according to a preferred embodiment of the present invention for manufacturing a solder bump structure; and FIG. 8 is a schematic diagram according to the present invention. A schematic diagram of a solder bump structure according to a preferred embodiment of the invention. [Simple description of component representative symbols] 10: Integrated circuit 12: Nitride lining 14: Shao pad 15: Gap 16: High score The material layer 18: adhesive layer 20: light-blocking layer 22 and diffusion barrier layer 24: solder structure