TWI236217B - Apparatus and method for adjusting the impedance of an output driver - Google Patents

Abstract

An output impedance bias compensation system for adjusting output impedance of at least one output including a reference impedance generator, an impedance matching controller, at least one output impedance generator, and a programmable bias controller. The reference impedance generator develops a reference impedance based on a reference value. The impedance matching controller continually adjusts an input of the reference impedance generator to match the reference value within a predetermined tolerance. Each output impedance generator is coupled to a corresponding output and is controlled by an output impedance control input. The programmable bias controller combines a bias amount with the value of the input of the reference impedance generator to provide the output impedance control input. The bias controller is programmable to provide a bias amount to compensate for any process variations between the reference impedance generator and each output impedance generator.

Description

1236217 V. Description of the invention (1) [Cross-reference to related applications] [0001] This application claims the case number 60/434284, the application date is the Provisional Application of the United States on December 17, 2002, and the case The number is 10/730425, and the application date is December 5, 2003. In the United States, the two applications of priority are actually incorporated herein by reference. [0 0 0 2] This application is related to the following U.S. patent applications that are jointly awaiting judgment, which is the same as the application of this application, which has a common assignee and at least one co-inventor, and that it will actually All are incorporated for reference. Serial number "File number> Name Φ 10 / 730389- OUTPUT DRIVER IMPEDANCE CNTR.2116 CONTROLLER. Controller of output driver circuit impedance f 10/730169. APPARATUS AND METHOD FOR CNTR.2117, PRECISELY CONTROLLING TERMINATION IMPEDANCE. · Device and method for controlling terminal impedance [Technical field to which the invention belongs] [0003] The present invention relates to an integrated circuit (1C) output driving circuit, and more particularly, to a method and device for adjusting the impedance of an output driver program circuit. To compensate for process variations throughout 1C. [Prior Art]

V. Description of the invention (2) Circuit = 4f] i; The early integrated circuit (ic) is set: Ten, and the moving program is set as push-pul 1 element. Therefore, the noise seen by the output bus will obviously change = scaung in response to various factors (including circuit temperature, supply = voltage, process difference, number of components on the bus, etc.), so the designer has been forced to actively The ground handles the noise problem on the μ row, so that the operating speed of the circuit in the system ::: 5 current row ϋ t includes cluster status ☆ system board or similar: 1 /, or evening Signal lines, where each signal line can be modeled (for example, reflection, cr0ss talk, etc.) dominated transmission ^ Miscellaneous holes [00 05] One of the more recent output driver circuit solutions The industry has changed from a push-pull output configuration to a differential receiver configuration. In the differential receiver configuration t, one side of the differential receiver is provided with a reference voltage for L and the side is driven by an open-drain channel element. The open drain N element is located on the chip, and the bus pull-up terminal impedance (tennination) is generally located externally, usually on the system motherboard or Ϊ = Ϊ 二 ΪΪΠ terminal impedance is located on the motherboard, which allows the system to set When the bus noise problem, there are two-fixed range changes. 』6 The type of driver circuit that has been described in the wheel of the description has been Π86 microprocessor (product of Intel Corporation == sub-series by Pentium series using open-drain N-channel output elements: & no. Pentlum 1 1 Reference Threshold voltage m.5V busbar switch on / off, drive with h0 volts. The motherboard of this processor is generally 1236217

Terminal impedance. Although specific pull-down and timing specifications have not been specified. However, the system is not compensated: the line compensation: will make the open-circuit n-channel output driver circuit circuit board: the range of the month can be changed from about 4 ohms to 80 ohms. The designer of the processor can only consider the process in advance and The acceptable range of the field has forced Pentium_n to be compatible with the main two = control the slew rate of 2-3 nanoseconds (ns) level to 2 years to the edge to reduce noise on the output bus. Will use the impedance, the bus cuts into the channel due to the slight change in the design output signal [00 07] In Pentium-ηι, Intel introduced a mechanism that will provide the output driver circuit that can be used to set the bus The reference impedance is given to the designer. The pins on the processor package (referred to as a few NCHCTRL) are connected to the bus voltage (referred to as νττ) through a precision 14 ohm resistor (the maximum specified resistance value is ohms). The precision resistor is external to the microprocessor chip and is therefore independent of the temperature and voltage changes seen by the output driver circuit on the chip. Therefore, the external resistor is used as a reference for setting the pull-down impedance of the open-drain N-channel output driver circuit. [0 0 0 8] In addition, the pull-up termination impedance of the compatible configuration is located on the chip rather than on the system board. For the pull-up termination impedance, another pin, called RTT, is used to allow a precision resistor R to be connected between this pin and ground. The impedance across the precision resistor is the impedance required for all pull-up termination impedances. Therefore, the system designer can set the pull-up impedance of the bus of the user signal on the component through an external resistor. Range of resistance according to specification

1236217 V. Description of the invention (4) 40 to 130 ohms, so the pull-up terminal impedance on the system design and on the bus is used to make up the N-channel open-drain sink [000 9] Yu Er'er describes a device and method for accurately controlling an open circuit of the N channel in a US patent application, and the impedance of the ancestral,, and 钿 are used. The N channel or p channel element of the pull-up or down-carry array is used as The final example is the use of two by the logic piece $ ... to monitor the reference impedance. The conducting element is determined. However: 'If there is a system throughout the die', it is: writing a binary array. Writing a binary array and the output driver circuit $ The surname will cause a complex difference, which is determined by the reference array. Real best number. [0010] Compensation system, using an anti-generator, and programmable impedance control to continuously adjust the deviation of a matching output impedance of a corresponding output voltage controller system [0011] according to In the present invention, the reference impedance controlled by adjusting to the impedance matching bias control input is predetermined tolerant, and one implementation is used to clarify the bias control input and one output controller is omitted. Reference resistance reference resistance control input, within degrees. The output impedance of each output impedance is less than the output impedance of one of the reference examples. The impedance matches the reference impedance output impedance production input to control the impedance control output impedance, including the impedance production to produce the control reactance and the generator system. The reference bias device can be combined with a bias bias, and the reference device is coupled to the program bias with the reference value. It is produced in another embodiment. The bias controller includes an output bias logic. Page 10 V. Invention Explain (5) to edit and adjust the bias voltage, and the combination of bias voltage and memory can be generated by logic. Value, which can be a percentage of the anti-control input [0012] circuit (1C), with resistance and at least one impedance generator. Impedance Matching Logic Logic is used for resistance and programmability. Output Integer value combination, whole logic. Adjusting the logic output resistance is suitable for adding a bias amount to the parameter. Its representative can be added or based on the output. There is an output resistance, and the impedance control logic package control input periodically refers to the impedance adjustment logic. The generation of the output and output bias voltage is used to reduce the range of the impedance of the control input bias, including the symbol, the reference impedance, and the reference impedance. The generator is used to bias the output impedance control logic into the input. Arbitrary, or polarity input control input ratio. Examples include using pins and series. For each control, between the impedance and the reference resistance, the reference resistance is programmed in turn and the reference is made to a type such as a safe bit. Another one hundred is used to generate a programmable non-swinging wire for the impedance impedance control input. Volatility, or a symbolic type, is the ratio of the bias voltage. The reference resistor provides one that is coupled to at least one programmable external programmable output and coupled to a comparator logic, anti-generator, and so on. Control input so that the gap is between the pre-impedance control input and the integrated electrical reference output wheel output impedance output connection and the input comparator reference electrical setting tolerance bias voltage adjustment will be blocked by [^ 01 3] according to the present invention. An embodiment provides a method for adjusting the output impedance of at least one output of 1C based on chirped impedance, including applying a reference voltage to a reference impedance and a reference impedance generator, and adjusting a reference impedance input of a reference generator so that The difference between the impedance of the reference impedance generator and the reference impedance is within a predetermined tolerance. Measure the reference impedance to ^ 1236217

Any difference between the output impedance of the volatile component and the reference resistance is reduced by one output resistance to compensate for the anti-input combination, anti-generator output variation, and bias any measurement difference to produce coupling Out impedance input. The integer value will be negated on I c; and the bias will be adjusted to correspond to the output. [Embodiment] [〇0 2 4] The following description is to enable a person skilled in the art to complete and use the present invention, such as a specific application And their requirements are provided in this article. However, it will be apparent to those skilled in the art that various modifications to the preferred embodiment will be apparent, and that the general principles defined herein may be applied to other examples. Thus, the invention is not intended to be limited to the specific embodiments shown and described herein, but is to be accorded the broadest scope consistent with the principles and novelty disclosed herein. [0 0 2 5] The inventors of the present application have understood the need to compensate for process variations across the die between the reference impedance generator and the output impedance generator including a pull-up or pull-down element. Therefore, it has developed a device and method for adjusting the impedance of the output driver circuit, and will further explain the technical features of the present invention with reference to the drawings of FIGS. 1-7. [0 0 2 6] FIG. 1 is a simplified block diagram of an integrated circuit (1C) 101 which includes a system for precisely controlling the termination impedance of a transmission line. Among them, ic 101 includes some input / output (I / O) pins that can be used for external connection, including the reference resistance pin RTT and multiple output pins, which are individually displayed as OUT1, OUT2, ..., OUTN, where N is positive Integer. Unless otherwise specified, a pin and its transmitted signal will be referred to by the same name. 1C 101 will generate electricity

Page 12 1236217 V. Description of the invention (7) Press the reference signal or receive the supply voltage signal 0]). 〇D can be provided from an external pin relative to the f (GND) pin (not shown). In the embodiment shown, the reference resistance R shown in dotted lines is externally connected between the pin rtt and the ground. 2 Although the present invention does not limit any specific value, range or resistance type, according to the specification, the resistance R The range is between 40 and 13 ohms, and can be a precision resistor or similar (for example, a 1% resistor).

[0027] The IC 101 further includes impedance matching logic 103, which is used to receive the VDD signal ' and to monitor the resistance of the reference resistor r and the internal impedance generator 207 (as shown in FIG. 2). In this embodiment, the impedance matching logic 丨 〇3 is used to monitor the potential of the RTT pin, and transmits the 6-bit digital value SUM [5: 0] on the 6-bit internal bus 105. The bias control logic element 106 is sequentially connected to the corresponding terminal impedance or pull-up logic element 10 7 (individually numbered from 1 to n) located on I c 1 〇1. Each individual pull-up logic element 107 receives a VDD signal and is coupled to a corresponding one of the output pins OUTx (where "X" is any integer from 1 to N representing a particular output pin). Within each pull-up logic element 07, each bit in the adjusted SUM [5: 0] value (that is, PSUM —X [5: 0]) will enable / disable a corresponding group An array of matched p-channel elements can have a common sink point and can be used to pull up and terminate the corresponding OUTx pin. The PSUM_X [5: 0] value specifies the number of p-channel components to be turned on in each pull-up logic element 107, which pulls up and terminates the corresponding UTx signal within the specified tolerance. In the embodiment shown, the PSUM__X [5: 0] value is adjusted in 64 equally spaced steps, and the impedance of the pull-up logic element 107 can be adjusted.

Page 13 1236217

During the operation of the component [0021], the impedance matching logic 103 will keep matching the binary fish array of the p-channel 107, which is substantially the same as each pull-up logic element and the binary array. Each array will be configured or divided into a binary group for the number: ff as described below. The resistance f of the local binary array in the impedance matching logic 103 will be continuously monitored and the SUM [5: 〇] value will be increased or decreased periodically, so that the voltage across the internal array and the resistance R The voltage difference is within a predetermined tolerance. In one embodiment, the predetermined tolerance is an error voltage of about 50 millivolts (mv). The selection period of the bus clock (INT Bcu) (for example, every two INT BCLK cycles) determines or periodically updates the optimal impedance of the pull-up logic element 107, and the value of SUM [5: 0] is determined by the bus Row 105 is passed to each bias control logic element 106, and pull-up logic element 107 is significantly updated. [0 0 2 9] The bias control logic element 06 is used to add or subtract a bias to the value of SUM [5: 0] located on the bus 105. This can be used to implement impedance adjustments for each pull-up logic element 107 to compensate for process variations throughout the die. In one embodiment, the bias controller 106 is used for each pull-up logic element 107. In another embodiment, the bias controller is used for a local group in the pull-up logic element 107. [0 0 3 0] FIG. 2 is a more detailed block diagram of an exemplary embodiment of the impedance matching logic 103. The impedance matching logic 103 includes an impedance controller 201, which is used to receive INT BCLK, VDD, and RTT signals. The impedance controller 201 includes a voltage sensor 203 for receiving a VDD signal and for monitoring the voltage of the RTT pin (locally shown as a signal I NP). The I NP signal is transmitted to the impedance

1236217 V. Description of the invention (9) The generator 207 displays the impedance between the VDD and I NP signals based on the 6-bit input control value SUM [5: 〇]. The voltage sensor 20 can effectively compare the voltages of the VDD and I NP signals and generate a signal η [and LO sent to the impedance control logic 2 05 to try to make the potential across the impedance generator 20 7 and The potentials of the resistors r differ within a predetermined tolerance. The impedance control logic 205 will respond to the HI / LO signal and increase / decrease the value of SUM [5: 0] to control the impedance of the impedance generator 20 7 until the difference between (VDD — INP) and INP is not greater than a predetermined error voltage (or So that the gap between the voltage of the INP signal and half of the VDD voltage is within a predetermined error voltage). In other words, the voltage sensor 2 03 and the impedance control logic 2 05 will cooperate to try to make the impedance (by voltage) of the impedance controller 2 07 differ from the resistance (by voltage) of the resistor R by a predetermined value. Within tolerance (by the amount of error voltage). [003 1] The VDD source voltage is divided by the resistor R and the impedance of the impedance generator 207 to provide an intermediate voltage of the INP signal. If the voltage of the INP signal is too high (indicating that the impedance of the impedance generator 207 is too low or lower than the resistance value of the resistor R), the voltage sensor 203 enables the HI signal and invalidates the LO signal. The impedance control logic 205 responds by reducing the SUM [5: 0] value to increase the impedance of the impedance generator 207. When the INP signal is too low (meaning that the impedance of the impedance generator 207 is too high relative to the resistor R), the voltage sensor 20 3 enables the LO signal and invalidates the HI signal. The impedance control logic 20 5 responds by increasing the value of SUM [5: 0] to reduce the impedance of the impedance generator 207. In the embodiment shown and described, although a proportional relationship is also considered, the SUM [5: 0] value is inversely proportional to the impedance of the impedance generator 207.

Page 15 1236217 V. Description of the invention (10) [0 0 3 2] In one embodiment, the voltage sensor 2 0 3 includes a pair of sense amplifiers (not shown), the voltage setting of which is half the VDD voltage Separated by a predetermined error voltage. In this case, the high-sense amplifier has a set point of approximately more than 1/2 VDD plus half the error voltage to control the η I signal, and the low-sense amplifier has a setting lower than 1/2 VDD minus half the error. The voltage set point is used to control the LO signal. Each sense amplifier compares the voltage of the I NP signal relative to its set point. If the voltage of the I NP signal rises to more than half of the error voltage, it will enable ΗI. If the value of I NP drops to less than half of the error voltage, it will enable the LO, and if the difference between INP and 1 / 2VDD is not Exceeding 1/2 error voltage will not enable HI or LO and will not take action. In a more specific embodiment, the predetermined error voltage is about 50 mV, so that the high-sense amplifier system is set to approximately more than 1 / 2VDD plus 25mV, and the low-sense amplifier system is set to approximately less than 1 / 2VDD. Subtract 25mV. The gap of the error voltage can be set to tight tolerances for higher accuracy or to a fairly wide tolerance to save power. [0 033] In an embodiment, the impedance control logic 205 is a digital circuit controlled by the INT BCLK signal, and during a selection period of the INT BCLK signal (such as each clock cycle or every other clock cycle) Etc.) will adjust (for example, increase or decrease) the SUM [5: 0] value. [0034] Referring now to FIG. 3, a more detailed block diagram of the bias control logic 106 in FIG. 1 is shown. The bias control logic 106 has a non-volatile logic 302, which is coupled to the output bias logic 301. The output bias logic 3W is coupled to the bias adjustment logic 303 via the signals PADD [3: 0] and psuBEN. INT BCLK and SUM [5: 0] are sent to the bias adjustment logic

1236217 V. Description of the invention (11) 303, which will generate the corresponding signal PSUM_χ [5 ·· 〇], as shown in FIG. 1. [0035] During operation, during the selection period of the clock signal INT BCLK (such as every other clock cycle or similar clock cycle), the bias adjustment logic 303 will be based on the value and signal of PADD [3: 0] PSUBEN state to adjust (eg, increase or decrease) the value of PSUM_χ [5: 〇]. The 4-bit value PADD [3: 〇] is transferred from the output bias logic 301 to the bias adjustment logic 303 to identify the amount to be added or subtracted from the SUM [5: 0] value. The sign or polarity signal psuBEN is passed from the output bias logic 301 to the bias adjustment logic 303 to determine whether to add (when PSUBEN is disabled) or subtract (when PSUBEN is enabled) this number. The PSUBEN signal and the PADD [3 ·· 0] value collectively constitute the signal bias adjustment value. In one embodiment, the SUM [5: 0] value is directly added (for example, when PSUBEN is logic 0 or disabled), or directly subtracted (for example, when psuBEN is logic 1 or enabled) PADD [3 : 0] value. In this case, the value of pADD [3: 〇] indicates that a fixed amount of bias voltage reaches a range of 1/4 of the value of SUM [5: 〇]. In another embodiment, the value of 'SUM [5: 0] is proportionally increased or decreased according to the PADD [3: 0] and psuBEN signals. For example, if pADD [3 ·· 〇] is set to 丨 00b (binary) and PSUBEN is not enabled, SUM [5: 〇] will increase by 50%. [0 0 3 6] In another specific embodiment, the output bias logic 3 01 includes, or is programmed by, a programmable non-volatile logic element 302 included in the IC. Any type of non-volatile programmable components can be considered, such as any type of non-volatile memory or a group of fuses or similar components. For example, one or more fuses can be blown, or several bits of a non-volatile memory element can be set or programmed to produce a pADD [3 ·· 〇] value and

IBM Page 17 1236217 V. Description of the invention (12) PSUBEN signal. The stylized state of the element 302 is determined by a part-by-part test procedure or the like. In one embodiment, almost every bit in the 'element 302 corresponds to the lower bit of the SUM [5: 0] value. In this way, programming component 302 allows the designer to increase or decrease the SUM [5: 0] value. Therefore, the output bias logic 301 is a way for the designer to compensate for process variations throughout I C 101. 4 is a schematic diagram of an exemplary embodiment of the impedance generator 400, which can be used to implement the impedance generator 207, and / or to implement any one of the pull-up logic elements 107. The impedance generator 400 includes 63 P-channel elements PI-P63 (or P63: P1) in a binary array. In one embodiment, each p-channel element P 6 3: P1 is matched so that the impedance from the drain to the source will be substantially the same. The source of each component P63: P1 is coupled to VDD, and the drain is coupled to the pull-up signal PUP, which represents the INP signal of the impedance generator 207, or the corresponding OUTx of any pull-up logic component 107 Signal. The components P63 ·· P1 are grouped in binary to correspond to the binary impedance value XSUM [5: 〇] (when the impedance generator 20 7 is implemented, it represents the value of SUM [5: 〇], or when any pull-up logic is implemented Element 107 'represents each of the six bits of PSUM_x [5: 0] value). The first array group is a single element p1 having a gate for receiving the signal PS0, and the second array group 401 includes two elements P2 and P3 (P3: P2), each having a gate for receiving the signal PS1 The third array group 403 includes four elements p4-p7 (p7: p4), each having a gate for receiving the signal PS2, and the fourth array group 405 includes eight elements p8-pi5 ( P15: P8) 'Each has a gate for receiving the signal pS3, the fifth array group 40 7 includes 16 elements 1 ^ 16-1) 31 (? 31: 1 > 16), each with

Page 18

1236217 V. Description of the invention (13) The gate for receiving the signal PS4, and the sixth array group 309 includes 32 elements P3 2_P63 (P6 3: P32), each having a gate for receiving the signal PS5. [0038] The PS5-PSO signal collectively constitutes a binary value enabled by the buffer 4 (which is used to receive the XSUM [5: 0] value). The parent in the pS5-pS〇 signal is the corresponding bit in the buffered XSUM [5: 0] value. For example, SUM5 bits are buffered, NS5 bits are generated, SUM4 bits are buffered, NS4 bits are generated, and so on. Therefore, when the value of SUM [5: 0] is increased or increased, the impedance between VDD and PUP will decrease, and vice versa. For example, an XSUM [5: 0] value of 100000b enables an array group 409 coupled to about half (or 32) of the p-channel elements in parallel, while an XSUM [5: 0] of 1000b The value will enable coupling of 33 array groups p 1 and 4 009 in the parallel P-channel element, and the value of XSUM [5: 0] of 1000 1 0b will make the coupling in the parallel p-channel element 34 array groups 403 and 409 are enabled and so on. The XSUM [5 ·· 0] value of 〇〇〇〇〇〇〇b will turn off all P-channel components in the high impedance state, and the value of 丨 丨 丨 丨 丨 lb will cause all 63 P-channel components at the lowest impedance level to cause can. In one embodiment, the array of components P63: P1 will be arranged and grouped according to size, and a pull-up impedance ranging from about 20 to 150 ohms will be generated to make the operating temperature and the bus voltage condition in the expected range. , As well as margins that pre-consider process changes. [0039] FIG. 5 is a simplified block diagram of another 1C 501 including a controller of an output driver circuit impedance. 1C 501 is similar to 1C 101, and the logic and circuits of both can be located on the same 1C if desired. 1C 501 also includes most of the external I / O pins, including bus voltage input pin VTT, N-channel control pin NCHCTRL, and multiple output pins

Page 19 1236217 V. Description of the invention (14) 〇UT1, OUT2 ......... OUTN or OUTx, as described previously. The external voltage signal VTT that generates the reference bus potential is located on the pin VTT, such as 1.5 Volts (V), for example. In one embodiment, the external reference resistor REXT shown in dashed lines is coupled between the pins VTT and VCHCTRL. If a KE × τ resistor is not provided, the internal resistor RINT will be used instead as the default reference resistor. It is assumed that the resistor REXT is provided, and the description of the resistor RI NT is fully described in the relevant disclosure, and will not be further explained here. In a particular embodiment, the REXT resistor is 14 ohms, and may be a precision resistor or a similar resistor. In this particular embodiment, the RINT resistor is implemented as a silicon diffusion. [0040] The IC 501 also includes impedance matching logic 503, which operates in a similar manner to the impedance matching logic 103 to monitor and compare the impedance with the internal impedance generator. In the displayed :, the impedance matching logic 503 is used to monitor νττ and the J-bit of the Dingli pin, and it will transmit the 6-bit number on the 6-bit internal bus 505.

[5: 0] transmitted to multiple bias control logic elements 506 whose M is on the corresponding output driver program circuit 507 on IC 501, and the input and output program circuits 507 are individually from i to N The pre-add / output driver circuit 507 is lightly connected to the J-second output of the output pin 〇υΤχ. Each output driver circuit 507 is similar to each; and also includes an array of matching, rugged 1 (II class N i channel, and X is P, s, or *) resistant to 70 pieces, except for these components For N-channel 'instead of P-channel, it operates as a pull-down element: for the °° In particular, in each output driver circuit 5Q7 ^ Each bit in OSUM —X [5: 0] causes An array of OUTx pins that correspond to and move to the bank group, eight drain points, and an array used to drive the group to match the N channel element is 1236217 V. Description of the invention (15) Enabled / disabled. 〇SUlW Y "c; γμ to go to drink ΛΑ Μ — χ [5: 0] value is an output enable signal with a state set according to the output driver program ρρ —, turn-out state 0 En = library two Λ number Based on the logic of the component (not shown) ..., the state of the output signal of the two τ 1 ί pins 0UTx. When the corresponding 0 = number is low, the value of _x [5: o] will be Specify the number of each open, first-° from the red circuit 507 'the open circuit (or enable) to be opened (or enabled) n = ^ =. In one embodiment, the 6-bit bus Row 5 0 5 will adjust the impedance of the output driver circuit in 64 step-by-step steps. 0041] During operation, the impedance matching logic 503 will keep matching the n-channel bureau Λ binary array, in fact f is the same as each output driver and a carry array. Each array is configured or divided into a digital input ^ and a carry group in a similar manner to the *: 2 211: array described previously. The impedance of the binary array of the impedance matching logic 503 will be continuously monitored, and will be adjusted up or down periodically.], So that the voltage system across the internal array and the jumper selection parameter 2 REXT ( (Or RINT resistor) voltages are within a predetermined tolerance. ^ In one embodiment, the predetermined tolerance is an error voltage of about 50 millivolts (mV). Furthermore, in an embodiment, the output driver circuit 5 The optimal impedance of 〇7 is determined by every two cycles of the INT BCLK signal, and the sum [5. Value is transmitted to each bias control logic element via bus 505, which will obviously be updated. Output driver circuit 507. [0042] Just like IC 10 As described in 1, IC 501 includes similar bias control logic element 506 to add or subtract the value of 讥 1 [5: 〇] on bus 505. This can be used to implement each Output driver circuit 507 1236217 Description of the invention (16) The impedance is trimmed to compensate for process variations throughout the die. In one embodiment, the 'bias controller 5' is used in the 5c Each output driver circuit 507 on 〇1. In another embodiment, the bias controller 506 is for a local group in the output driver circuit 507 on 1C 501. [0 0 4 3] FIG. 6 is a more detailed block diagram of an exemplary embodiment of impedance matching logic 503. In the configuration shown, the impedance matching logic 50 3 is substantially similar to the configuration and operation of the impedance matching logic 03 discussed in conjunction with FIG. 1. In the related disclosure, the impedance matching logic 503 is implemented in a slightly more complicated manner 'and includes a sensing circuit. It is used to sense whether the REXT resistor is connected ’and if not, it will enable another one, similar to an impedance controller using the resistor R 丨 NT as a reference resistor. [0044] The impedance matching logic 503 includes an impedance controller 601, which is used to receive the INT BCLK signal, and includes a voltage sensor 603, which is used to monitor the voltage of the VTT and NCHCTRL pins. The NCHCTRL pin shown will generate a signal I NP ′ which will be transmitted to an impedance generator referenced to ground 607. The impedance generator 607 inputs the control value SUM [5: 〇] and displays the impedance between the INp signal and ground. The voltage sensor 603 can effectively compare the voltage between the VTT and NCHCTRL pins with the voltage from the NCHCTRL pin to ground, and generate signals HI and LO sent to the impedance control logic 605 to try to make the potential at Within the tolerance. The impedance control logic 60 will increase / decrease the value of SUM [5: 0] to control the impedance of the impedance generator 607 until the difference between (VDD — INP) and INP is within a predetermined error voltage (or even the INp signal The voltage is half of the voltage νττ). In other words, assuming an external REXT resistor, the voltage sensor 603 and the impedance control logic 605 will cooperate to try to make the impedance

1236217 V. Description of the invention (17) The voltage of the controller 607 is equal to the voltage of the resistor r in the predetermined error voltage. [0045] When the REXT resistor is external, the ντΤ source voltage is determined by

The REXT resistor and the impedance of the impedance generator 607 divide the voltage, and provide the corresponding voltage on the ijyp signal. If the voltage of the INP signal is too high (meaning that the impedance of the impedance generator 607 is too high (or greater than REXT)), the voltage sensor 603 will enable the HI signal and invalidate the LO signal. The impedance control logic 605 will respond by increasing the value of SUM [5: 0] to reduce the impedance value of the impedance generator 607. When the impedance of the impedance generator 607 is too low, the voltage sensor 603 will enable the LO signal and invalidate the ΗI signal. The impedance control logic 605 will respond by reducing the SUM [5 ·· 0] value to increase the impedance value. In the embodiment shown and described, 'although a proportional relationship is considered, the value of sUM [5 ·· 〇] is inversely proportional to the impedance of the impedance generator 607. In one embodiment, the voltage sensor 603 includes a pair of sense amplifiers (not shown), which are substantially configured in a similar manner to the voltage sensor 203 described above. Furthermore, in one embodiment, the 'impedance control logic 605 is a digital circuit controlled by the I NT BCLK signal, and during the selection period of the INT BCLK signal (such as each clock cycle or every other clock cycle) Etc.) will adjust (eg, increase low) the SUM [5: 0] value. Fortunately, referring now to FIG. 7, a more detailed block diagram of the bias control logic 506 in FIG. 5 is shown. The bias control logic 506 has a non-volatile logic element 702 which is coupled to the output bias logic 701. The output bias logic 701 is coupled to the bias adjustment logic 703 via a signal ADD [3: 0] & SUBEN. The signal INT BCLK and SUM [5: 0] will be transmitted to the bias adjustment logic 703, which will generate the corresponding signal 0SUM-χ [5: 〇], as shown in Figure 1236217 V. Description of the invention (18) TJn ° [0047] During operation, during the selection period of the clock signal INT BCLK (such as every other clock cycle or similar clock cycle), the bias adjustment logic 703 will be based on the value and signal of ADD [3: 0] SUBEN status to adjust (eg, increase or decrease) the 〇SUM-X [5: 〇] value. The 4-bit value ADD [3: 0] is transferred from the output bias logic 7 0 1 to the bias adjustment logic 7 03 to identify the amount to be added or subtracted from the SUM [5: 0] value. The sign or polarity signal SUBEn is transmitted from the output bias logic 701 to the bias adjustment logic 703 to determine whether to add (when SUEN is disabled) or subtract (when SuBEN is enabled) this number. The SUBEN signal and the ADD [3: 0] value together constitute the signal bias adjustment value. In one embodiment, the SUM [5: 0] value is directly added (for example, when SUBIN is logic 0 or disabled), or directly subtracted (for example, when SUben * is logic 1 or enabled) PADD [3 : 0] value. In this case, the value of ADD [3: 0] means that a fixed amount of bias voltage is in the range of 1/4 of the value of SUM [5: 0]. In another embodiment, the value of 'SUM [5: 0] is proportionally increased or decreased according to the ADD [3: 0] and the suben signal. For example, if ADD [3 ·· 0] is set to 1000b (binary) and SUBIN is not enabled, SUM [5: 0] will increase by 50%. [0048] In another specific embodiment, the output bias logic 701 includes or is comprised of a programmable non-volatile logic element included in the IC 501 (such as a non-volatile memory or fuse or Similar components). The output bias logic 701 and programmable non-volatile logic element 702 in IC 5 〇1 are substantially the same as the output bias logic 301 and programmable non-volatile, logic element 302 in 1C 101 Operation without further explanation. 1236217 V. Description of the invention (19) [0049] Figure 8 is a schematic diagram of an exemplary embodiment of the impedance generator 800, which can be used to implement the impedance generator 607, and / or the output driver circuit 507. Either. The impedance generator 800 includes a binary array of 63 N-channel elements \ 1-1 ^ 63 (or N63: N1). In one embodiment, each N-channel element N 6 3: N1 is matched so that the impedance from the drain to the source is substantially the same. The source of each element N 6 3: N1 is coupled to ground, and its non-pole is coupled to signal INP. Elements N6 3: N1 are grouped in binary to correspond to each of the six bits of the binary impedance value ZSUM [5: 0]. The first array group is a single element N1, which has a gate for receiving a signal ⑽ ^, and the second array group 801 includes two elements? ^ 2 and (1 ^ 312), each with Receiving the gate of the signal NS1, the third array group 803 includes four elements N4-N7 (N7: N4), each having a gate for receiving the signal NS2. The fourth array group 805 includes eight N8 — N15 (N1 5: N8), each having a gate for receiving the signal NS3, the fifth array group 807 includes 16 elements N16-N31 (N31: N16), each with The gates for receiving the signal NS4 and the sixth array group 809 include 32 elements n32-N63 (N63: N32), each having a gate for receiving the signal $ NS5. [0050] The NS5-NS0 signal will constitute a binary value NS [5: 〇] enabled by the buffer 811, which is used to receive the ZSUM [5: 0] value. Each bit in the Ns [5: 〇] value is the corresponding bit in the buffered iZSUM [5: 〇] value. Therefore, when the value of Z S U M [5: 0] is increased or increased, the impedance of the I n p signal will decrease, and vice versa. For example, a ZSUM [5: 〇] value of 100000b enables the array group 809, which couples about half (or 32) of the parallel N-channel elements, and 10001 b A ZSUM [5: 0] value will cause 33

1236217 V. Description of the invention (20) array groups N1 and 809 are enabled, and the ZSUM [5: 0] value of 1 0 0 0 1 0b will couple 34 to 4 array groups in parallel N-channel components 8 0 3 and 8 9 enable and so on. A ZSUM [5: 0] value of 0 0 0 00 0b will turn off all N-channel components in the high impedance state, while a value of 111111 b will enable all 63 N-channel components at the lowest impedance level. In an embodiment, the array of elements N63: N1 will be arranged and grouped according to size, and a pull-down impedance ranging from about 4 to 24 ohms will be generated to make the operating temperature and the bus voltage situation in the expected range, and will Leaving margins for advance consideration of process changes. [0051] Although not shown, each output driver circuit 507 may be configured in a similar manner to the impedance generator 507. For each output driver circuit 507, the value of 31 ^ [5: 0] is replaced by the value of (^ 1 ^ [5: 0], and additional logic (such as an array and gate or similar) is used Combine the 0 EN signal with each of the NS 5-NS 0 signals, as described in the related disclosure. In this way, the IC 5 0 1 is configured in a similar manner to the IC 1 0 1, where each output driver circuit 5 0 7 includes a matching impedance element of a binary array 'which will match the matching impedance element of a reference binary array located in the impedance generator 607. [0052] 1C 101 is described using a matched P-channel pull-up element, while 1C The 501 is explained by using a matched N-channel pull-down element. In any kind of brother, the impedance controller (for example, 201, 601) will modify the digital value (Example 2 'SUM [5: 0]) in an attempt to make the impedance generator ( For example, the impedance of 20.7, 60.7) matches the reference component (for example, r, REXT), where the digital value is used to set a similar impedance generated in the output component that is coupled to the output pin of the relevant IC Device impedance. Impedance matching logic (for example, 103, 503)

1236217

The impedance of the reference impedance generator in is used to match the impedance of each impedance generator in the wheel-out element (eg, 507). If there are process variations throughout the die, this will cause a significant difference between the replication binary array and the wheel-out drive element. The number of impedance elements determined by the reference array will not be the optimal number of output elements. [0053] Output bias logic (for example, 301, 701) and bias adjustment logic (for example, 303, 703) will provide a way for designers to drive by assigning to known pull-up components or output programs These components within the circuit (or a group of pull-up components or output program drive circuits) bias control logic components 06, 506 to compensate for these process variations throughout the chip. For example, after manufacturing, the designer may place c into a test device (not shown), which connects the 1C vehicle to a reference impedance (eg, r * rext). The test setup measures any difference between the output of the reference impedance and the resulting impedance (pull-up or pull-down) to identify errors or bias offsets. Therefore, the designer can program the output bias logic (for example, 301, 701) to remove errors to compensate for process variations on the chip. [0 054] FIG. 9 is a flowchart of a method for adjusting an output impedance of at least one output of an IC based on a reference impedance according to another exemplary embodiment of the present invention. In the first box 9 0 1, it means that I c belonging to the test is placed in a test device or similar device for performing the test procedure, and a reference impedance (for example, a reference resistance R, REXT) may be externally connected if necessary. Note that if the reference resistor R I NT is internal, it can be used as a reference impedance. At block 90 3, it means that after the power of 1C is turned on and started to operate, it will apply the reference voltage to the reference impedance and the reference impedance generator. In this real

Page 27 1236217 V. Description of the invention (22) In the embodiment, the reference voltage may be a voltage source (such as a VDD signal or a similar signal), which is applied across a series-connected reference resistance and reference impedance. [0055] At block 905, it means that 1C adjusts the reference impedance input of the reference generator so that the difference between the impedance of the reference impedance generator and the reference impedance value is within a predetermined tolerance. In this embodiment, the voltage is measured at the mid-plane between the reference impedance and the reference impedance generator, and compared with the percentage of the reference voltage (for example, VDD or VTT). Furthermore, the reference impedance input is adjusted periodically or continuously to stay within a predetermined tolerance. At block 9 07, the selected number of matching impedance elements representing the binary array of the reference impedance generator will be internally enabled by Ϊ C based on the reference impedance input. In this embodiment, the reference impedance input is a digital value, where each bit enables a matching impedance element (which may be an N-channel or P-channel element) in an array of a selection group. [0056] At block 909, it means that the output impedance input connected to each output impedance generator (which is coupled to the corresponding output) is based on the reference impedance input and is controlled by IC. At block 9-11, it means that the selected number of matched impedance elements in the binary array of each output impedance generator will be enabled based on the round-out impedance input. In this way, IC will attempt to adjust the impedance of its output based on the reference impedance. As mentioned earlier, each pull-up logic element 107 and / or each output driver circuit 507 includes a matching impedance element with the same configuration as the reference impedance generator, so that the output termination impedance of each output will be based on Reference impedance. [0 0 5 7] At box 9 1 3, it means that any difference between the reference impedance and at least one output impedance is measured. This can be achieved automatically by the test device

Page 28 1236217 V. Description of the invention (23) It can be achieved manually or by the test operator. Another way, ’if the resistance R I NT is used as a reference resistance during the test, the measured output impedance is compared with the known or desired value of the output pull-up and / or pull-down resistance. On the next box 9 1 5, on I c, the non-volatile components corresponding to the measured output impedance will be programmed with bias adjustment values to compensate for any measured impedance differences. In the specific embodiment described, the bits of the non-volatile memory element are set, or the selected fuse contained in [c] is blown to provide a control mechanism that compensates for process variations throughout Ic. In block 917, it means that 1C will combine the bias adjustment value with the reference impedance input, and output the impedance as the whole round. In the embodiment shown, the bias adjustment logic (303 '703) incorporates (adds, subtracts, or combines) the value of ADD [3: 0] or PADD [3: 0] SUM [5: 0] value, and respectively generate OSUM-X [5: 〇] value or PSUM —X [5 ·· 0] value, which will be transmitted to each output element (for example, pull-up logic element 107 or output driver circuit 5 〇7). The test procedure will be repeated again to ensure proper compensation, or to pull up the logic element 107 or the output driver circuit 507 PSUM-X [5: for different areas corresponding to 丨 c 1 〇 丨, 5 〇 丨0] and OSUM-X [5: 0] will produce different compensation values. [0 0 5 8] During operation, the impedance controller will continuously adjust the output impedance of each selected output element (or component group) of 1C (the bus of the output driver circuit) in the clear and easy-to-understand manner described above. Pull-down impedance, or pull-up termination impedance). An apparatus and method for adjusting the impedance of an output driver circuit according to an embodiment of the present invention enables a system designer to adjust the impedance to compensate for process variations throughout 1C. Programmable non-volatile logic elements (such as non-volatile memory or fuses or similar) are located on the chip.

Page 121236217

It is possible to program each bias adjustment value. Each bias adjustment value is used by its corresponding bias adjustment logic element to produce the desired compensation. [0059] Although the present invention has been described in detail in conjunction with certain preferred embodiments, other forms and variations are possible and can be considered. For example, various methods of making the programmable impedance generator and the reference resistance phase 4 can be considered, such as current technology or similar technology. Furthermore, any type of non-volatile programmable device may be considered for programming the compensation. In addition, although the present invention contemplates an embodiment using a metal-oxide-semiconductor (MOS) type element (including a complementary MOS element and the like, such as, for example, a NMs & pMOS transistor), it may also be used. A similar approach applies to different or analogous types of technology or similar elements, such as bi-amplitude elements or similar elements. [0 0 6 0] Finally, those skilled in the art should understand that, in order not to depart from the spirit and scope of the present invention as defined by the scope of the appended patent application, in order to carry out the same purpose as the present invention, It can immediately use the disclosed concepts and specific embodiments as the basis for designing or modifying other structures.

Page 1236217 Brief description of the drawings [Simplified description of the drawings] [0014] With the following description and accompanying drawings to disclose the advantages, features, and effects of the present invention will make it easier for your reviewers to understand, of which [[0 0 1 5] FIG. 1 is a simplified block diagram of an integrated circuit (IC) including an example system for accurately controlling the termination impedance of a transmission line; [0 0 1 6] FIG. 2 is a diagram of impedance matching logic in FIG. 1 A more detailed block diagram of an exemplary embodiment; [0 0 1 7] FIG. 3 is a more detailed block diagram of the bias control logic in FIG. 1;

[0 0 1 8] FIG. 4 is a more detailed overview of an exemplary embodiment of the impedance generator, which can be used to implement the impedance generator in FIG. 2 and / or implement any of the pull-up logic elements in FIG. 1 A; [0 0 1 9] FIG. 5 is a simplified block diagram of an IC including a controller of an output driver circuit impedance; [0 0 2 0] FIG. 6 is a modification of an exemplary embodiment of the impedance matching logic in FIG. 5 Detailed block diagram; [0 0 2 1] FIG. 7 is a more detailed block diagram of the bias control logic in FIG. 5;

[0 0 2 2] FIG. 8 is a schematic diagram of an exemplary embodiment of the impedance generator in FIG. 6, which can also be slightly modified and used as the impedance generation in the output driver circuit in FIG. 5. [0 0 2 3] FIG. 9 is a flowchart of a method for adjusting an output impedance of at least one output of an IC based on a reference impedance according to an exemplary embodiment of the present invention. Schematic description:

1236217 on page 31 Brief description of the diagram 101, 501 Integrated circuit (1C) 103, 503 Impedance matching logic 105, 505 Internal bus 106, 506 Bias control logic element 107: Pull-up logic element 201, 601 Impedance controller 203 , 603 voltage sensor 205, 605 impedance control logic 207, 607 impedance generator 301, 701 output bias logic 302, 702 non-volatile logic element 303, 703 bias adjustment logic 400, 800 impedance generator 401, 801 No. Two array groups 403, 803 Third array group 405, 805 Fourth array group 407, 807 Fifth array group 409, 809 Sixth array group 411, 811 Buffer 507 • Output driver circuit

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Claims (1)

1236217 An output impedance bias compensation system is an output impedance of at least one output, and includes: a reference impedance generator for generating a reference impedance controlled by a reference impedance control input; an impedance matching controller for continuously Adjust the reference impedance control input to make the difference between the reference impedance and a reference value within a predetermined tolerance; at least one output impedance generator, each of which is coupled to a corresponding output, and is controlled by an output impedance control input Control; and a programmable bias controller for combining a bias amount with the reference impedance control input to generate the output impedance control input. 2 · The output impedance bias compensation system according to item 1 of the scope of patent application, wherein the bias controller includes: output bias logic, which can be programmed to generate the bias amount; and bias adjustment Logic, coupled to the output bias logic and the impedance matching controller, for combining the bias amount with the reference impedance control input to generate the output impedance control input. 3. The output impedance bias compensation system according to item 2 of the scope of patent application, wherein the output bias logic includes a plurality of fuses. 4. The output impedance bias compensation system according to item 2 of the scope of patent application, wherein the output bias logic includes a programmable non-volatile logic element. 5. The output impedance bias compensation system as described in item 2 of the patent application scope, wherein the bias amount includes a sign bias value, which is added to the reference impedance control input. I2362i7 Apply the patent scope so that the gap between the reference resistor and the programmable reference impedance generator is within a predetermined tolerance; otherwise, adjust the logic, which will adjust the reference impedance control input with a bias voltage 11 Combined to generate the output impedance control input. The integrated circuit described in item 10 of the patent scope is adjusted, wherein the round-out 1 2 / Chu logic includes a plurality of programmable fuses. The integrated circuit described in item 10 of the patent application scope, wherein the round out 1 3 · = Chu logic includes a programmable non-volatile logic element. The integrated circuit described in claim 10 of the patent scope, wherein the programmable red reference impedance generator and each of the programmable output impedance generators include a matching element of a binary array. 14 · The integrated circuit as described in the scope of the patent application, wherein the reference impedance control input adds or subtracts the bias adjustment value. 1 5 · The integrated circuit as described in item 10 of the patent scope of the patent, wherein the bias adjustment value includes a percentage value, which represents a percentage of the reference impedance control input, and the reference impedance control input is added with or Subtract this percentage value. 16. · A method for adjusting the output impedance of at least one output of an integrated circuit based on a reference impedance, comprising: applying a reference voltage to the reference impedance and a reference impedance generator ', the reference impedance generator has a reference impedance Input ·, adjust the reference impedance input so that the difference between the impedance of the reference impedance generator and the reference impedance is within a predetermined tolerance; measure any difference between the reference impedance and at least one output impedance Page 1236217 6. The scope of the patent application is different; a non-volatile component on the integrated circuit is programmed with a bias adjustment value to compensate for any measurement difference; and the bias adjustment value is combined with the reference impedance input, and An output impedance input is generated for at least one output impedance generator, and each output impedance generator is coupled to a corresponding output. 17. The method as described in item 16 of the scope of patent application, wherein the programming of a bias adjustment value includes blowing out at least one fuse. 18. The method as described in item 16 of the scope of patent application, wherein the programming a bias adjustment value includes programming at least one bit of a non-volatile memory. 19. The method as described in item 16 of the scope of patent application, wherein the bias adjustment value includes a plus sign bias value, and wherein combining the bias adjustment value with the reference impedance input includes adding the Add the sign bias value. 2 0. The method as described in item 16 of the scope of patent application, wherein the bias adjustment value includes a percentage value, which represents a percentage of the reference impedance input, and a polarity signal, and wherein the bias adjustment Combining the value with the reference impedance input includes adding or subtracting the percentage to the reference impedance input based on the polarity sign. Page 36