TWI235458B - MOS transistor and fabrication method thereof - Google Patents

Abstract

A method for fabricating MOS transistor. The method includes the steps of providing a substrate with a gate structure thereon, and then forming first spacers on the sidewalls thereof. Thereafter, a first ion implantation is carried out using the gate structure and the first spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, second spacers are formed on the exterior sidewalls of the first spacers. Then, a second ion implantation is carried out using the gate structure, the first spacers and the second spacers as a mask to form source/drain regions in the substrate. The first and second spacers are then etched to expose a portion of the vertical sidewalls of the gate and a portion of the substrate adjacent to source/drain regions. The exposed top surfaces of the gate, the exposed portion of the vertical sidewalls of the gate and the exposed source/rain regions are then covered by silicide formed during silicidation. Finally, the remaining metal is removed and the formation of salicide (self-aligned silicide) is completed.

Description

I235458 ": —______—_ V. Invent WTi)! ~~ '[Technical Field to which X Month belongs] The present invention relates to a partition wall structure and a method for manufacturing the same. In particular, the method for manufacturing a integrated circuit element for forming a self-aligned silicide on an etch-back gap wall in Part 1 can arbitrarily control the loss of the top of the gap wall, reduce the contact resistance of the self-pairing lithium oxide, and improve the inner dielectric trench Fill in the process. [Prior art] With the increase in the density of components in semiconductor integrated circuits, the volume of components is getting smaller and smaller ’The critical line width (CD) of a component is also smaller

^ Coming narrower. At the same time, as the minimum line width of the device decreases, the ratio of the CD of the spacer on the gate side to the CD of the gate polycrystalline silicon layer also increases. In the field of complementary CMOS technology, narrow questionnaires (to increase speed) and tight polysilicon spacing (to increase layout density) are needed for logic and memory cell design applications. Therefore, it is often applied to the connection of CMOS gates (PM0S gate to NM0S gate, n-internal wiring. From the perspective of process limitation, narrow gates must eventually reach the limit, leading to unstable The chip resistor 'method to solve this problem is to expose the exposed area of the door egg to increase the formation of silicide (as shown in Figure 2). This means that A must over-etch the gap wall, but over-etching the gap wall will lead to a more private, wall Side profile (pro fi 丨 e) and poor gap wall width control. This-gap asymmetry causes large current fluctuations, causing the SRAM or logic line U to lose its time. Due to the tight polycrystalline chip spacing, a Extra Nitride

1235458 V. Description of the invention (2) cont 2 ^ ^ 2 2 materials, as a borderless contact window (borderless contact) ^, ^. 4 π &θ; ι electrical layer 1 L D trench filling process problems will occur f ^ i ^ 1 gap soil network or side profile, so the same ~ ~ ~ 70 pieces of current fluctuation control. Figures 1 Α and 1 Β are surface diagrams of Qiande & μ ^, ra made from VII, + h ning ", and traditional M0S elements without over-etching spacers, ΑΛ1Π Γ]. Please refer to the first hundred references Figure 1A, which provides half of the lead 2 pt 4 t / with a gate structure 2 〇 including a gate oxide layer 30 and a complex bipolar 40 ° semiconductor substrate 10 surface with a shallow trench isolation region to isolate each疋. A dielectric layer (not shown) is conformally formed on the semiconductor substrate 10, covering the gate structure 20. The above dielectric layer is anisotropically etched, and a gap wall 60 is formed on the gate electrode. On the sidewall of structure 20, please refer to FIG. 1B. A contact stop stop layer 70 is formed from si ^, ^ ⑽, or other suitable high-dielectric constant material, and is covered with a gate electrode. The structure 20, the spacer 60 and the surface of the semiconductor substrate 10 are finally formed with an inner dielectric layer 80 covered with an etch stop layer 70. The above-mentioned method for fabricating the metal-oxide half-element without over-etching the spacer will result in the interlayer dielectric After the electrical layer 80 is filled in, a void 90 is formed, or after the contact with the tungsten plug is deposited, it causes the longitudinal beam (W-str inger), which affects the electrical performance of the device. Figures 2A and 2B show the traditional method of manufacturing a MOS device with over-etched spacers. First, please refer to Figure 2A to provide a semiconductor substrate 10 with a gate electrode on it. The structure 20 includes a gate oxide layer 30 and a polycrystalline silicon gate electrode 40 °. A shallow trench isolation region 50 is provided on the surface of the semiconductor substrate 10 to isolate each element. A dielectric layer is conformably formed on the semiconductor substrate 10 ( Not shown),

0503-9596TW (Nl); TSMC2002-1219; 1292; hmngwo.ptd Ϊ235458

Cover the gate structure 20 to form over-etching. Please layer the surface of the material. The upper electrode silicide will not produce gaps. Refer to Section 2B to form a junction. Cover with the gate to form the coin engraving to reduce voids. Wall side wheel. Using the gap map of anisotropic etching, the contact resistance is made from Si3N4 contact stopper structure 20, and an inner dielectric barrier wall is used to make the contact resistance. However, the over-etching templet (prof i 1 e) #etches the dielectric layer and makes it excessive. The wall 60 a is on the side wall of the gate structure 20. SiON or other suitable high dielectric constant layer 70 (contact etch stopper gap wall 60 a and the semiconductor substrate 10 layer 80 is covered with a etch stop layer 70). The method can form a low-resistance complex crystalline silicon gate and cause the inner dielectric layer 80 to be filled, which will lead to poor control of the barrier wall width. A wider barrier wall will result in a higher source / drain (S / D) impedance, so that the improvement of the performance of the device is limited by the S / D impedance; on the other hand, a gap wall more than I will cause the S / D empty area of the element to invade the channel area and cause a sigma plane breakdown (punch) In addition, when the top loss of the compensation spacer (0f fset spacer) is insufficient, it will lead to poor self-aligned silicide chip resistance Rs distribution. US Patent No. 65 09264 discloses a method of first applying the gate surface Chemical, mechanical grinding process, and then isotropic etching In order to obtain a larger reaction area of the polysilicon gate silicide, thereby reducing the sheet resistance. In contrast, U.S. Patent No. 646 1 951 discloses a method of directly passing the nick of the spacer to obtain a comparative Large silicide region of the polycrystalline silicon gate, thereby reducing the chip's resistance. Neither of the above two known methods can avoid the problems caused by poor gap wall width control and gap wall side profile (pr0fi 1e) control. US Patent No. 6 1 8 7 6 4 5 discloses a method for avoiding

1235458 5. Description of the invention (4) Free the generation of gate-to-drain capacitor Cgd and reduce the width of the polycrystalline silicon gate. In addition, 'U.S. Patent No. 598 1 3 25 discloses a manufacturing method of a CMOS with a compensation gap structure to reduce the overlap capacitance between the gate and the source / drain' to increase the manufacturing window. However, by the above-mentioned conventional method, when the top loss of the compensation spacer (Offset Spacer) is insufficient, it will lead to a poor distribution of the sheet resistance Rs of the self-aligned silicide, and the internal interlayer is caused by the over-etching of the spacer After the electrical layer is filled in, voids are generated, or tungsten struts (W stringer) are caused after the contact tungsten plug is deposited. If the compensation gap will be included

When the wall is engraved, because the etching selection ratio of the nitride layer and the oxide layer is not high enough, the thin barrier layer cannot completely block the etching, resulting in gate structure gouging. Summary of the Invention: In view of this, the present invention The purpose is to provide a method for manufacturing metal-oxide half-elements. Another object of the present invention is to provide a two-stage etch-back method for manufacturing metal-oxide half-elements to obtain a better self-aligned silicide chip resistance Rs distribution. Another object of the present invention is to provide a metal-oxide half-element structure and a method for manufacturing the metal-oxide half-element structure, which avoid problems caused during subsequent filling of the inner dielectric layer trench. Another method for producing the oxygen half of the present invention is Cgd. The purpose is to provide a gold with compensating bulkhead structure to reduce the overlap between the gate and source / drain.

0503-9596TWF (Nl); TSMC2002-1219; 1292; Jamngwo.ptd Page 11 1235458 V. Description of the invention (5) According to the above-mentioned purpose, the present method 'includes the following steps: · Structure is provided. Then a first gap gate structure is formed and the first gap wall is inside the body substrate, so as to form a lightly doped gap wall in the half gap wall of the first gap wall and the second gap wall in the cover 'to form a source electrode and a Ming provides a metal-oxygen half-element manufacturing side two spacers, which are contracted to expose self-aligned metal silicide. The method according to the present invention includes the following steps: providing a structure. A gap wall is formed on the gate and the gap wall is a cover screen, which is implanted into a source electrode and a drain region and a part of the side wall of the gate electrode. The top surface of the structure is formed and the exposed compliant stop layer is covered with the surface of the conductor substrate. And forming layers. According to the above purpose, the present invention includes at least: a semiconductor substrate region 'in the semiconductor substrate, the semiconductor substrate formed on a sidewall of the gate structure is formed on a side cover of the gate structure, and the impurity drain is separated from the impurity with a low energy. (LDD) region < on a conductor substrate. With the gate, implanted ions enter the drain region. Qian carved part of the side wall of the first gate, and the top of the gate, this half of the structure of the ion is introduced. An internal layer of the self-gate junction metal stone and the exposed invention provide a different body substrate. The sidewall of the semiconductor is inserted into the semiconductor spacer and aligned with a part of the metal silicide and the interlayer dielectric layer. The above has a gate wall. The semiconductor is implanted with the above-mentioned daughter. A second electrode structure is formed, the first semiconductor substrate, a spacer, and a first. And forming a sidewall surface. A MOS system has a gate junction in the gate structure base, so that its internal shrinkage exposes compounds on the gate wall. A gap wall is formed and the half of the surname is engraved. Ming also provides a kind of gold oxide, which has a gate below the gate structure. _ And the gate structure, half-element structure, and structure are exposed. A channel partition wall, part of the side wall of the formation. 0503-9596TW (Nl); TSMC2002-1219; 1292; Jamngwo.ptd Page 12 1235458

A source and a drain doped region are formed in the semiconductor substrate, adjacent to the side of the region. A self-aligned metal silicide is formed on the surface of the divided side wall of the gate top p, and the surface of the source and the non-polar doped region. An etch-stop layer is compliantly formed to cover the self-aligned metal sulfide, the wall, and the surface of the semiconductor substrate. And an inner layer JI electrical layer 'is formed to cover the remaining stop layer. Implementation:

The & drawings and preferred embodiments are described below to explain the present invention in more detail. X Example 1 Figures 3 to 8 are sectional views showing the arrangement according to a preferred embodiment of the present invention. Please refer to FIG. 3, and firstly provide a semiconductor substrate 100, such as a silicon substrate. There is a gate structure 200 thereon, including a gate dielectric 210 and a gate conductive layer such as a polycrystalline silicon layer 22 on the gate dielectric layer 210. The semiconductor substrate 100 has a shallow trench isolation region 300 in its surface to isolate each element. ^ Please refer to FIG. 4 afterwards, sequentially conforming on the semiconductor substrate 100

A first oxide layer 230 and a first nitride layer 240 are formed to cover the gate structure 200 and the semiconductor substrate 100. The first oxide layer 23 may be TEOS-Si02 deposited by a chemical vapor deposition (CVD) method and has a thickness of 10 A to 60 A ', such as 30 A. The first nitride layer 240 may be nitride nitride deposited by a CVD method, and has a thickness of 50 A to 200 A, such as 150 A. 2. Next, please refer to FIG. 5 to etch the first oxide layer 2 3 0 and the first with an anisotropic etching process, such as reactive ion etching (RI E) or plasma etching.

I

0503-9596TW (Nl); TSMC2002-1219; 1292; Jamngwo.ptd Page 13 1235458 V. Description of the invention (7) A nitride layer 2 4 0, which exposes the top surface of the gate structure 200 and covers the gate structure The sidewall of 2000 is used to form a first gap wall 250 on the sidewall of the gate structure 2000. This first gap wall 250 is also called a compensation gap wall "" ^ spacer) and has a thickness of 50A to 200A ', such as 10QA. After the first spacer 250 is formed, low-energy ions 500 are implanted into the semiconductor substrate 100 to form a lightly doped anode L D D region 400. The formation of the lightly doped non-polar LDD region 400 is to form NLDD with kun or filling ions or PLDD with hafnium or boron ions. The implantation energy is 1 to; [0 keV, the implantation concentration is 1E12 to 3E15 atoms / cm2, and the implantation depth is 200 to 80 A.

Referring to FIG. 6 ′, a second oxide layer 2 60 and a second nitride layer 2 70 are sequentially and compliantly formed on the semiconductor substrate 100 in order to cover the upper part of the gate structure 2000 and the first The sidewalls of the spacer wall 250 and the semiconductor substrate 001. Similarly, the second oxide layer 260 may be TEOS SiO 2 deposited by CVD or PECVD method, as much as 100A to 300A, for example; [50A. The second nitride layer 270 may be nitride nitride deposited by a CVD or PECVD method, and has a thickness of 30qa to 100A, such as 600A. Anisotropic etching, such as reactive ion etching or plasma etching, is used to etch the second oxide layer 2 60 and the second nitride layer 27 0 'to form a second gap wall 2 8 0 to expose the gate. The top surface of the pole structure 2000 covers the side wall of the first partition wall 250. The second spacer wall 2 〇 is also called a main spacer, with a thickness of 300 A to 100 A, such as 60 A. A high-dose ion 600 (HDD) is re-implanted into the semiconductor substrate to form a source 4 10 and a drain region 4 1 0. Forming the source / drain region 410 forms nmOS with arsenic or phosphorus ions or pMOS with indium or boron ions. Planting energy is 5 to 60 keV and planting concentration is 1E15 to 1E16

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at〇mS / Cm2. During the process of forming the source / drain region 41 °, the temperature is 600 to 12 ° C., Nipponbori & n ^ Torr. The heart UC day is 0 to 40 seconds, and the pressure is ip. Please refer to Figure 7 and use the remaining time to suffice | Fen Guang-^ H ^ 980 0…] Etching a gap wall 25 0 and the first The interstitial soil 280 shrinks to expose the upper vertical side wall portion & of the gate electrode and a portion of the source electrode and the drain electrode on both sides of the gate electrode ^.

The reaction area of the compound becomes larger, and the sheet resistance of the gate conductive layer is reduced. It also increases the area of metal silicide formation on the source and drain surfaces, reducing S and reducing contact resistance. Among them, the wet etching method first uses hot phosphoric acid at a temperature of "^ ⑽" to perform nitrogen and layer etching, and then uses diluted HF and buffered oxide etching (b0e) solution to perform oxide layer etching. Therefore, the exposed gate can be arbitrarily controlled The size of the vertical sidewall part a on the upper part of the electrode and the area b of the source and drain electrode close to the sides of the gate. These areas are for the subsequent formation of metal silicide, so that the metal silicon on the top of the gate is finally formed by referring to Figure 8 and forming itself. Aligning the metal silicide layer 290: using an evaporation method, a sputtering method, or a CVD method,

Compliant to form a refractory metal layer (not shown), such as platinum, cobalt, nickel, or titanium, with a thickness of 100 to 300 A, covering the 2000 surface of the gate structure, the first spacer 250, and the first Two spacers 280 and a semiconductor substrate 100. Between the metal layer and the exposed top surface of the gate, between the metal layer and the upper vertical sidewall portion of the exposed gate, and between the metal layer and the source and drain regions of the semiconductor substrate. 1 Between 0, a contact surface is formed. The semiconductor substrate 100 is further subjected to an annealing process at a temperature of 400-12 0 ° C and a time of 6-60 seconds. Make the metal layer and the polycrystalline silicon layer 2 2 0 react and make the metal layer and the semiconductor

1235458 V. Description of the invention (9) The bulk substrate m reacts to selectively form a metal lithoxide (Mi) hard crystalline silicon layer 220 and the above-mentioned contact surface of the semiconductor substrate! 00. y s in the ㈣metal process ’such as Long 3, Nη4〇η, Η202μ2〇 mixed solution,

Unreacted metal layer to form self-aligned metal silicide "elf to remove aligned silicide) 70 0. Then, use CVD or pECVD, SiON or other suitable high dielectric constant (k > 5) materials such as SiaN4 conforms to form a contact etch stop layer (not shown), compound 700, first spacers 250 and second spacers 280, and half metal:: 1 layer 00 surface. Finally, an inner dielectric layer is formed. (Not shown) covered with etching 'According to the present invention, it is possible to arbitrarily control the exposed side of the upper vertical gate of the gate a and the source and drain portions of the region near the gate b on both sides of the gate. The reaction area of the object becomes larger, reducing the gate conductivity: the sheet resistance (Rs), and increasing the metallization of the source and non-electrode surface, reducing the contact resistance. The A m product is shown in FIG. 8. The metal-oxide half-element structure includes:-a semiconductor substrate 100 'having a gate structure 2000 channel region on the semiconductor substrate 100 below the gate structure 2000. a

The gap wall 25 ′ is formed on the side wall of the idle electrode structure 2000 and exposes a part of the side wall of the closed electrode structure. -The second gap wall 28o is formed on the side wall of the first gap D wall 250 ... the source and drain doped regions 41o are formed in the semiconductor substrate 100, adjacent to both sides of the channel region. And self-aligning metal silicide 70 0 is formed on the top surface of the gate, the exposed part of the side wall surface, and the surface of the source and drain doped regions 4 10.

1235458

Second embodiment, Figs. 9 to 12 are sectional views showing the arrangement according to another preferred embodiment of the present invention. Compared with the first embodiment, this embodiment forms only one set of partition walls.

Referring to FIG. 9, a semiconductor substrate 100 is provided, which has a gate structure 200 thereon, including a gate dielectric layer 210 and a gate dielectric layer 210 such as a polycrystalline silicon layer 220. Very conductive layer. The semiconductor substrate 100 has a shallow trench isolation region 300 in its surface to isolate each element. A lightly doped drain LDD region 400 is formed in the semiconductor substrate 100 near the two sides of the gate 200. 2. Forming a lightly doped drain LDD region 400 forms NLDD with europium or phosphorus ions, and forms PLDD with surface or collar ions. The implantation energy is i to 10 keV, the implantation degree is 1E12 to 3E15 atoms / cm2, and the implantation depth is 200 to 80 A.

On the entire semiconductor substrate 1000, an oxide layer and a dielectric layer (not shown) are sequentially and compliantly formed to cover the gate structure 2000. The dielectric layer may be silicon nitride, Si ON, or other suitable materials with a high dielectric constant (e.g., k > 5), such as SisN4. The oxide layer can be TEOS-SiO2 deposited by CVD or pECVd method, and the dielectric layer can be nitrided nitride deposited by CVD or PECVD & The oxide layer is used as an etch stop layer, and anisotropic etching, such as reactive ion etching (RIE) or plasma etching, is used to etch the dielectric layer to form a square barrier wall 2 50, and the gate structure 2 000 On the side wall, the thickness is about 500a to 1000a, such as 700A. Please refer to FIG. 10 ′, and then form a source electrode and a region (not shown), and sequentially use a lithography process and implant ions 5 0 0 (for example, NM0S uses As or P ion source;

1235458 5. Description of the invention (11) PMOS enters the semiconductor substrate 100 with a B or BF2 ion source) to form a drain / source region 410. The implantation energy is 5 to 60 keV, and the implantation concentration is π "to 1E16 atoms / cm2. After forming the source / drain region 41 °, an annealing process is performed, and the temperature is 60 0-120 °. The time is 0-40 seconds and the pressure is 10-6 Torr.

Please refer to Fig. 11. The oxide layer is etched with diluted HF and buffered oxide etching (B0E) solution, and the nitride layer is etched with hot phosphoric acid at a temperature of 80 ° -2 °. Etching the gap wall 25〇 (30person to 30person) make the inside thin into a partition wall 250a, exposing the upper vertical side wall portion a of the gate electrode and a part of the source and drain electrodes that are close to the two sides of the gate electrode b. In order to form a metal silicide in the following regions, the reaction area of the metal silicide on the top of the gate becomes larger, reducing the sheet resistance (Rs) of the conductive layer of the gate, and the area of the metal silicide formed on the source and non-electrode surfaces. Increase and decrease the contact resistance. 0 Please refer to Figure 12 to form a refractory metal layer (not shown), such as platinum, cobalt, by compliance with evaporation (sputtering), sputtering, or CVD. , Nickel, or titanium, with a thickness of 1000 to 3,000 A., covering the surface of the gate structure 2000, the barrier wall 250 a, and the semiconductor substrate 100. On top of the metal layer and the exposed gate Between surfaces, between the metal layer and the upper vertical side wall portion of the exposed gate And forming a contact surface between the metal layer and the source and non-electrode regions 4 1 0 of the semiconductor substrate 100, and then subjecting the semiconductor substrate 100 to an annealing process at a temperature of 400-1 2 0 ° C, time is 6-60 seconds. The metal layer is reacted with the polycrystalline silicon layer 22 0 and the metal layer is reacted with the semiconductor substrate 100 to selectively form a metal silicide (MxSiy) layer 700

0503-9596TWF (Nl); TSMC2002-1219; 1292 ;: Umngwo.ptd page 18 1235458 5. Description of the invention (12) ----- Between the polycrystalline silicon layer 2 20 and the aforementioned contact surface of the semiconductor substrate 100. Metallization and wet etching metal processes, such as NH3, NH4OH, 402 and mixed solutions, are removed to remove unreacted metal layers' to form self-aligned si 1 pesticide 7 0 0 ° Please refer to Figure 13 for CVD or PECVI ^ deposition of SiA, SiON and other suitable high dielectric constant (k > 5) materials, such as "汍. Compliance to form a 〃 contact etch stop layer 80 0 cover metal The silicide 700 and the spacer support "the surface of the semiconductor substrate 100." Finally, an inner-layer dielectric layer 900 etch stop layer 800 is formed. According to the present invention, it is possible to arbitrarily control the size of the exposed vertical sidewall portion a of the upper part of the gate, and the partial regions b of the source and drain electrodes close to both sides of the gate. Make ^ the reaction area of the metal silicide on the top of the gate larger, reduce the gate conductive layer: sheet resistance (Rs). It also increases the metal silicide formation surface on the source and drain surfaces, reducing contact resistance. '' According to the present invention, the over-etched spacer can prevent voids from being generated after the inner dielectric layer 90 is filled, or the tungsten longitudinal beam (W-str i nger) can be triggered after the contact with the tungsten plug is deposited, as described in Section 13 As shown in the figure, the present invention provides a metal oxide containing at least ...-a semiconductor substrate 100 having a free electrode 22 on it. A channel region is below the gate structure 2000 in the semiconductor substrate 100. A gap wall 250a is formed on the side wall of the gate structure 2000 and exposes part of the side wall of the gate structure 2000. A source and drain doped region 40 is formed in the semiconductor substrate 100 and is adjacent to both sides of the channel region. A self-aligned metal silicide 700 is formed on the top surface of the gate, the exposed part of the sidewall surface and the source

1235458 V. Description of the invention (13) The surface of the pole and drain doped regions 41 °. An etch stop layer 800 is formed conformably to cover the surface of the self-aligned metal silicide 700, the spacer 25a, and the semiconductor substrate 100. An inner dielectric layer 900 is formed to cover the etch stop layer 800. [Features and Effects of the Case] The features and effects of the present invention are as follows: The present invention provides a method for manufacturing metal-oxide half-elements with self-aligned silicide by forming an etchback spacer. The top surface of the gate structure is exposed by over-etching to form a better self-aligned sheet resistance & distribution. Secondly, the present invention can avoid poor gap wall width control and gap wall side profile control problems caused by overetching the gap wall. In addition, the present invention can also avoid the occurrence of voids after the filling of the trenches of the inner dielectric layer, which can cause the tungsten stringer (w_stringer) after the tungsten plug is deposited. The invention also provides a method for manufacturing a metal-oxide half-element with a compensation gap structure to reduce the overlap between the gate electrode and the source / drain capacitor. Although the present invention has been disclosed above in a preferred embodiment, its And ^: Dingshi invention 'I am familiar with this art, without departing from the invention': and: within the scope of * can be changed and moistened, θ Λ protection scope of the invention; s see the attached patent The scope defined shall prevail. Encircle

1235458 Brief description of the drawing. Figures 1 A and 1 B are cross-sectional views showing the arrangement of integrated circuit components with self-aligned debris formed by the conventional barrier wall without over-etching. Figures 2 A and 2 B show the conventional non-over-etching. Sectional views of the arrangement of integrated circuit elements with the spacers forming self-aligned silicide; Figures 3 to 8 show a preferred implementation of an integrated circuit element with the spacers formed by etching back the spacers to form self-aligned silicide FIG. 9 to FIG. 13 are layout cross-sectional views of another preferred embodiment of an integrated circuit element in which a self-aligned silicide is formed by etching back a gap wall according to the present invention. [Symbol description] Known part 2 0 ~ gate structure; 40 ~ complex silicon gate; 60, 60a ~ spacer 80 ~ inner dielectric layer; ❿10 ~ semiconductor substrate; 30 ~ gate Dielectric layer; 50 to shallow trench isolation area; 70 to contact etch stop layer; 90 to void. Part of this case (Figures 3 to 13) 10 0 ~ semiconductor substrate; 2 0 0 ~ gate dielectric layer; 2 30 ~ first oxide layer; 2 50 ~ first spacer; 2 0 0 ~ gate structure; 2 2 0 ~ multi-crystal chip gate 240 ~ first nitride layer 2 8 0 ~ second spacer

0503-9596TWF (Nl); TSMC2002 -1219; 1292; J amngwo. Ptd page 21 1235458 Brief description of the diagram 3 0 0 ~ shallow trench isolation area; 400 41 0 ~ source and drain area; 500 ~ low energy Ion implantation; 600 7 ◦ 0 ~ self-aligned metal silicide; 8 0 0 ~ contact etch stop layer; 9 0 0 high-dose ion implantation in the lightly doped non-electrode area into the inner dielectric layer a, b ~ in the spacer Shrink the exposed area

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Claims (1)

I23545R ---- One E No. 92118 · __ ^ year? !!曰 条条 正 禾 _ 6. Scope of patent application L A method for manufacturing metal-oxide half-elements, comprising the following steps: providing a semiconductor substrate having a gate structure thereon; forming a first gap wall on the gate structure On the sidewall; using the gate structure and the first gap wall as a mask, implanting ions into the semiconductor substrate to form a lightly doped region and a pole region; forming a second gap wall on the first gap wall On the semiconductor substrate on the side wall; using the gate structure, the first gap and the second gap as a mask, implanted ions enter the semiconductor substrate to form a source and a > and electrode region; and The first gap wall and the second gap wall of the money engraved part are contracted to expose a part of the side wall of a gate electrode. 2. The method of manufacturing a metal-oxygen half element according to item 1 of the scope of patent application, wherein the gate structure includes a gate dielectric layer and a closed conductive layer on the gate dielectric layer. 3. The manufacturing method of the metal-oxygen half element according to item 1 of the scope of patent application, wherein the first gap wall is a compensation gap wall, and the manufacturing method further includes the following steps: sequentially forming an oxide layer on the semiconductor substrate And a nitride layer to cover the upper and side walls of the gate structure; and an anisotropic engraving of the oxide layer and the nitride layer to form a first gap wall, exposing the surface of the gate structure to cover the gate electrode The side walls of the structure. 4. The method for manufacturing a metal-oxygen half element according to item 3 of the scope of the patent application, wherein the thickness of the first spacer is 50-200 A. 0503-9596TWFl (Nl); TSMC2002-1219; 1292; JammGwo.ptc page 23 "Repair", 5. The method of making metal-oxygen half-elements as described in item 1 of the scope of patent application, wherein the method for manufacturing the second spacer further includes the following steps: Net 4 is sequentially on the semiconductor substrate Forming / oxidizing layer and a nitride layer, W overlying the top of the idler structure and the side wall of the third spacer and the bottom of the semiconductor; and anisotropically etching the oxide layer and the nitride layer to A second partition wall is formed to expose the top surface of the gate structure and cover the side walls of the first gap wall. 6. The manufacturing method of the metal-oxygen half element according to item 1 of the scope of the patent application, wherein the first and second spacers are carved with wet etching #. ^ 7. The method for manufacturing a metal-oxygen half element according to item 3 or 5 of the scope of the patent application, wherein the oxide layer is wet-etched with a diluted HF or buffered oxide etching (BOE) solution. ^ 8. The production of metal-oxygen half-elements as described in item 3 or 5 of the scope of patent application, the heart side; wherein the nitride layer is wet-etched with a phosphoric acid solution. 9. The method for manufacturing a metal-oxygen half element according to item 1 of the scope of the patent application, wherein the first and second gaps are contracted and exposed on the surface of the source and the drain and close to the gate. Part of the plaque domain on both sides of the polar structure. 10_ The method for manufacturing a metal-oxygen half element as described in item 1 of the scope of the patent application, wherein the height of the gate sidewall exposed by the first and second gaps shrinking is 30-100 Å. . 11 · The method for manufacturing a metal-oxygen half element according to item 1 of the scope of patent application, wherein the gate structure includes a polycrystalline silicon gate and the semiconductor substrate is 0503.6 Shi (N1); l * 2002_1219; 1292; Jairfwoptc, p. 24 12354% & Year Amendment ^-Case No. 921180 ^ 6. Scope of patent application Shi Xi base. 1 2 The method of manufacturing a metal-oxide half-element as described in item 11 of the scope of the patent application further includes forming a self-aligned metal silicide on the top of the gate and the exposed sidewall surface. 1 3 · The method for manufacturing a metal-oxygen half element according to item 12 of the scope of the patent application, wherein the method for manufacturing self-aligned metal silicide includes the following steps: forming a metal layer overlying the gate structure, the A first spacer wall, a second spacer wall, and the semiconductor substrate; subjecting the semiconductor substrate to an annealing process so that the metal layer reacts with the polycrystalline stone layer and reacts the metal layer with the semiconductor substrate to form a metal A silicide layer; and removing the unreacted metal layer by a chemical wet etching metal process. 1 4 · According to the manufacturing method of the metal-oxygen half element described in item 13 of the scope of patent application, the metal layer is made of refractory metal. 15. The method for manufacturing a metal-oxygen half element as described in item 13 of the scope of the patent application, wherein the metal layer includes: '° 1 6 · — a method for manufacturing a metal-oxygen half element composed of platinum, cobalt, nickel, or titanium , Including the following steps: 'provide a semiconductor substrate with a gate structure thereon; form a gap wall on the side wall of the gate structure; use the gate structure and the gap wall as a cover and a curtain, implant ions into the clinic , A conductive substrate to form a source and a drain region; and the gap wall of the half-etched portion, so that it is contracted to expose a gate Zou Ba 0503-9596TWF1 (N1); TSMC2002-1219; 1292; JammGwo.ptc Page 25 Amendment Year 1235458 ^ --- No. 921180 Zhan VI. Method of Patent Application 1 7 · As described in Item 16 of the Patent Application The fabrication of oxygen half-elements is a method in which the gate structure includes a gate dielectric layer and a gate conductive layer above the gate dielectric. Fang 1 8 Manufacture of metal-oxygen half-elements as described in item 16 of the scope of patent application `` wherein the method of making the spacer further includes ... on a semiconductor substrate, sequentially forming an oxide layer and a Dielectric is used to cover the gate structure; and the oxide layer is used as an etch stop layer, and the dielectric layer is etched isotropically to form a gap wall. / 9 · According to the manufacturing method of the metal-oxide half-element described in item 18 of the scope of patent application, wherein the dielectric layer is a dielectric material with a dielectric constant k > 5. 20 · The method for manufacturing a metal-oxygen half element according to item 18 of the scope of the patent application, wherein the dielectric material is silicon nitride. 2 1 · According to the manufacture of the metal-oxygen half element described in item 16 of the scope of the patent application, wherein the exposed portion of the single gap wall further includes the surface of the source and the drain and is close to both sides of the gate structure Part of the area. 2 2 · The manufacturing method of the metal-oxide half-element as described in item 6 of the patent application scope ', wherein the height of the gate sidewall exposed by the internal shrinkage of the spacer is 30-1000 A. 2 3 · The method for manufacturing a metal-oxide half-element as described in item 16 of the scope of patent application, wherein the gate structure includes a polycrystalline silicon gate and the semiconductor substrate is a broken substrate. 24. The method of manufacturing a metal-oxygen half element according to item 23 of the scope of the patent application, wherein after the step of etching the gap, the method further includes forming 0503-9596TW_); TSMC2002-1219; 1292; JaramGw〇.ptc 26 K 1235458 Correction: Self-align metal silicide on the top surface of the gate structure and part of the side wall of the gate structure that is exposed. 25. The method for manufacturing a metal-oxygen half element according to item 24 of the scope of the patent application, wherein the method for manufacturing a self-aligned metal oxide compound includes the following steps: forming a metal layer covered with the gate electrode and the gap wall And the semiconductor substrate; subjecting the semiconductor substrate to an annealing process so that the metal layer reacts with the polycrystalline stone layer and reacting the metal layer with the semiconductor substrate to form a silicide layer; and a chemical wet etching metal process Remove the unreacted metal layer. 26. The method for manufacturing a metal-oxygen half element according to item 25 of the scope of patent application, wherein the metal layer is made of refractory metal. 27. The method for manufacturing a metal-oxygen half-element as described in item 25 of the scope of the patent application, wherein the metal layer includes platinum, cobalt, nickel, or titanium. 28. The method for manufacturing a metal-oxygen half-element as described in the patent application No. 6 and further including: forming a compliant etch stop layer covered with the metal silicide, the spacer and the surface of the semiconductor substrate; And forming an inner dielectric layer and covering the etch stop layer. 29. The method for manufacturing a metal-oxygen half element according to item 28 in the scope of the patent application, wherein the coin stop layer is a dielectric material having a dielectric constant k > 30. The method for manufacturing a metal-oxygen half element according to item 28 of the scope of the patent application, wherein the material of the etch stop layer is silicon nitride. 05O3-9596TWFl (Nl); TSMC2002-1219; 1292; JammGwo.ptc Page 27 123508 Case No. 92118035 6. Scope of patent application 31. The method for producing and producing a metal-oxygen half element as described in item 28 of the scope of patent application, wherein the inner dielectric layer is composed of Si02, borophosphosilicate glass coat w (BPSG), fluorine-doped glass ( FSG) or tetraethoxysilane (TE0s), which is a single layer or multiple layers. ', Ren 32 · — A metal-oxygen half-element structure including at least: a semiconductor substrate' having a gate structure thereon; a channel region under the gate structure in the semiconductor substrate; a first gap wall formed at The side wall of the gate structure and a part of the side wall of the gate structure are exposed; ~ ^ The first gap wall is formed on the side wall of the first gap wall; A retracted gap wall; a source and a drain doped region formed in the semiconductor substrate, adjacent to both sides of the channel region; and a self-aligned metal silicide formed on the top surface of the gate, The surface q of the side wall of the trowel and the surface of the source and the non-doped region; wherein the area of the source and drain doped regions is smaller than that of the surface of the source and the impurity region of the drain. The area of silicide. 33. The metal-oxygen half-element structure according to item 32 of the scope of patent application, wherein the gate structure includes a gate dielectric layer and a gate conductive layer on the gate layer. 3 4 · As stated in Item 32 of the Patent Scope The metal-oxygen half-structure, wherein the first-intermediate unit is oxygen-cutting and nitrogen-cutting or / any ^ == 3 / .. The metal-oxygen half-element structure described in item 32 of the scope of patent application, in which the first The thickness of the partition wall is 500-200A. jj35458 Case No. 921180: _ _ month and month _ 6. The scope of patent application 36 6 The metal-oxygen half-element structure described in item 32 of the scope of patent application, wherein the second partition wall is oxidized stone and nitrided stone or Any of them. 37. The metal-oxide half-element structure as described in item 3 β of the scope of patent application, wherein the height of the gate sidewall exposed by the retracted gap wall is 30-1 0 0 0 A 〇 3 8 The metal-oxygen half-element structure described in the item 32 of the scope, wherein the gate structure includes a polycrystalline silicon gate and the semiconductor substrate is a silicon substrate. · 39 · The metal-oxygen half-element structure according to item 38 of the scope of patent application, wherein the self-aligned metal silicide is a metal layer and the silicide formed by the reaction of the polycrystalline silicon gate and the Shixi substrate Made up. 40. The metal-oxygen half-element structure according to item 39 of the scope of the patent application, wherein the metal layer comprises platinum, cobalt, nickel, or titanium. 4 1 · A metal-oxygen half-element structure, at least including: $ —car body body bottom, which has a gate structure; a channel region, under the gate structure in the semiconductor substrate; a gap wall, the It is formed on part of the side structure of the gate structure of the gate structure; of which, 踏 n is stepped out of the gate. The gap wall of the free Bajia is a retracted gap wall, which is one of the etched back. Straight-tomb β, where the interpolar structure and the complete interposition are defined on both sides of the semiconductor substrate area; and #% d pass term-self-aligned metal silicide to form Part of the surface of the side wall and the surface of the retrospective #, the surface of the Fentolite A port, the surface of the chrome / primary electrode and the doped region of the drain; 1235458 ^ Case No. 92] 1Rfl! ^ VI. Patent Application Range Amendment Wherein the area of the source and non-doped regions is smaller than the area of the metal lithosite on the surface of the source and the hetero regions. 42. The metal-oxygen half-element structure according to item 41 of the scope of the patent application, wherein the gate structure includes a gate dielectric layer and a gate conductive layer on the gate dielectric layer. 4 3 · The metal-oxygen half-element structure according to item 41 of the declared patent scope ’, wherein the partition wall is made of silicon oxide and silicon nitride or any of them. 44. The metal-oxygen half-element structure according to item 41 in the scope of patent application, wherein the height of the side wall of the gate exposed by the retracted gap wall is 5 0-1 0 0 0 Α 〇 4 5 The metal-oxygen half-element structure according to item 41, wherein the gate structure includes a polycrystalline silicon gate and the semiconductor substrate is a silicon substrate. 46. The metal-oxygen half-element structure as described in item 41 of the scope of application for patent, wherein the .. 5 rows are opposite to the silicide formed by the reaction of a metal silicide-based gold spreading layer with the complex silicon gate and the silicon substrate. Composition of things. 47. The metal-oxygen half-element structure according to item 46 of the scope of patent application, wherein the metal layer comprises: starting, starting, nickel, or titanium. 48. The metal-oxygen half-element structure as described in item 41 of the scope of the patent application, further comprising: a coin-cut stop layer compliantly formed to cover the self-aligned metal silicide, the spacer, and the surface of the semiconductor substrate; And an inner dielectric layer to form an etch stop layer. 4 9. The metal-oxygen half-element structure described in item 48 of the scope of patent application, 0503-9596TWFl (Nl) >TSMC2002-1219;1292; JammGwo.ptc Page 30 1235458 Case No. 92118035_year month__ VI. Application for patent scope where the etch stop layer is a dielectric constant k > 5电 材料。 Electric materials. 50. The metal-oxygen half-element structure according to item 48 of the scope of application for a patent, wherein the material of the #etch stop layer is nitrided silicate. 5 1. The metal-oxygen half-element structure according to item 48 of the scope of the patent application, wherein the inner dielectric layer is composed of borophosphosilicate glass (BPSG), fluorine-doped glass (FSG), or tetraethoxysilane ( TEOS) made of any single or multiple layers. 0503-9596TWFl (Nl); TSMC2002-1219; 1292; JammGwo.ptc Page 31