TWI235331B - Method and apparatus for maintaining status coherency between queue-separated functional units - Google Patents

Abstract

An apparatus and method in a microprocessor having two unaligned functional unit pipelines which enables an instruction queue for the second pipeline to be placed at an intermediate pipeline stage rather than after the stage in the first pipeline that retires instructions. The apparatus maintains coherency between the status of each instruction in the queue relative to its status in the first pipeline. The status comprises an age of the instruction and a valid bit. The age specifies the stage in the first pipeline in which the instruction resides. The apparatus includes logic for updating the age and valid bit based on whether the first pipeline is stalled, on valid bits from the first pipeline, and on whether the queue is downshifting. The microprocessor selectively updates its user-visible state with the instruction execution results from the second functional unit based on the instruction age and valid bit.

Description

1235331

_ Case No. 9121961,1 V. Description of the Invention (1) No. 10 / 279,213, in which the main a is Zhang 22, Wu Yi: Priority of the case of Shen: Japanese case: case [the technical field of the invention] [0 0 0 2] The present invention relates to the field of pipelined microprocessors, and more particularly to a pipelined microprocessor having multiple functional units. [Prior technology] [0 0 0 3] Modern microprocessors usually have multiple functional units, such as integer units (integer units (IUs) and floating-point units (floating points) for executing integer, floating-point, and multimedia instructions, respectively.) — P〇in1: unit (referred to as FPU) and vector arithmetic unit, such as MMX unit (MXU). Each functional unit is a pipeline with multiple stages. When an instruction or operation passes through the pipeline, each stage will execute a part of the instruction or operation. ^ [0 0 0 4] Because floating-point and multimedia instructions usually Involving longer 77 arithmetic calculations, so the FPU and MXU usually require more clocks to execute the "7" instruction than the IU. In some cases, this will cause the operation of the I U pipeline to stop, for example, when F P U or M X U is not ready to receive another instruction or operation. Outside 'because the data cache memory will be paused when the FPU or MXU is not ready to receive = data to be sent, so the fact that the FPU and MXU need more time to execute will cause the lack of operation of the data cache memory Pulse rate. In order to solve these problems, a command and data file can be added to put the FPU or MXU to receive the command and its related data, so that the fetch memory can continue to operate. Shell material fast [0 0 0 5] The microprocessor can be seen by the user

1235331

V. Description of the invention (2)

U device concept of the state. For example, in the architecture's microprocessing, the user-visible state includes the general-purpose register (such as the EAX register), the field ',-^ (such as the floating-point register,) in the user-visible register. And V such as the flag I register: temporary storage phase crying off temporary storage "Can only be… ^ 4 minutes before you can update the user's visible status, such as righteous cases. This is because certain events or conditions will occur. That is, certain events or conditions will occur. Line means; 丄; Do not update the messenger of the processor; or; = Stop execution flow. * The processor later: The entry of the long handle μ knife and fork that was already in the functional unit pipeline is predicted to be wrong. Even if the execution of the hypothetical 2 steps after the instruction branch completes the partial execution, it must be visible to the user . On the other hand, it is invalidated, and it is not allowed to update the exception. For example, a paging error ^ invalidation event is an exception. In addition, the most common reason for fluttering '= different', general protection abnormality, or invalid operation, is that the day when I can enter the pipeline, it is invalid. This stage of the pipeline was not populated with valid > person " buffer caches. ^ 9 $, resulting in operation pauses or bubbles. [00〇7] When a power tool such as —, the FPU needs to be executed according to / = Wu Ru FPl ^ to prepare the execution state of the instruction to be visible to the executor. In order to update the use of the processor with specific instructions, the instruction is still valid and visible to the user. The FPU must know this visible state. In order to ensure that the user of this instruction to update the processor is allowed to execute the instruction validation function, the instruction 1 is still valid, and the conventional processor will set a queue at the end of the functional unit.

Mm I ai_ ftiLI ι · 」· ι ·· _li _ ι ·· _ι · _ ^ _

Page 81235331 Amendments to the fifth invention description (3) is "Γ:] Yes? Two pieces (such as branch prediction 0 $ this, early features. That is, the Λ pieces /; X or Λ will be notified by the invalidation bar. Often) informs the integer pipeline 104 whether it will be valid according to the microprocessor i'OO combination of // order or operation. Figure 1 is used to refer to the end of = to set the rank 106. Because 04. By queuing 10 column 106 before passing through the integer pipeline

: Or two = :; the end of the two, you can ensure that the end of A "will not be sent; 'Λ'Λ ;;: the second is OK ,; once the instruction reaches the pipeline [0 〇〇9] The instruction is effective. The creep at the end of the yuan will have disadvantages. It requires people; 仃 The end of the single-effect functional unit pipeline for the function of the validating function ": Before entering the queue, f proceeds to the first through the functional unit pipeline. : Said tf before entering the queue, it must be able to pass without, but therefore the two shi & 邛 stage, these stages could have been effective before the effective amount: the delay of Bu. That is, the function single stage, you can receive Command and start the middle stage of a meta pipeline that is far from the end of the 70 S line, data cache: two two j: 'The data needed to validate functional units such as FPU. Therefore, the human body can provide other The clock cycle required for the functional unit pipeline phase is 7 and the extra delay through the remaining effective function sheets [00〇10] will cause gate 7 to be more ^ unnecessary delay. The integer multiplication function reduces the integer unit by 74. An example is that MXU provides integer multiplication for MX professional method instructions. Take the ^ Yu Ding to remove the integer multiplier to reduce the micro-processing H circuit 7 ^ every day, then the instruction will be able to use the MXU integer multiplier to y, inch, and the integer multiplication is performed. However, because Page 121235331 Case No. 92129613 Amendment ^ Replace f Ⅴ 5. Description of the Invention (4) —— Instruction sequences, integer multiplication instructions are quite common, so when performing integer multiplication, place MXIK column at the end of the pipeline of integer units The additional delay may be unacceptable. [0 0 1 1] However, if MXIK is placed at a stage where the instruction may be invalidated later, once the instruction enters MXIK column, MXU cannot determine that the instruction is still valid. That is, because the MXIK column is located before the end of the integer pipeline, when the instruction is in the MXIH column, or when the MXU has received an instruction from the column During execution, invalidation conditions may occur. When the instruction passes through the IU and MXU pipelines, it will no longer be chained closely. Therefore, the integer unit may cause the instruction to be delayed during any delay in the MXIK list. MXU does not know whether it can update the user-visible state. [0 0 1 2] Therefore, a mechanism is needed to maintain the command state between the functional units when the functional unit queues are not aligned. [Abstract] [0 0 1 3] The present invention provides a device for tracking the age (age) of instructions or operations in an instruction queue register of a functional unit, regardless of whether the instructions or operations are in the queue. What is the position of the function. That is, the functional unit will record the corresponding IU pipeline stage of the instruction at any time. In addition, for each instruction in the queue, the functional unit will record a valid bit. If the I U informs the functional unit that an instruction has been invalidated, the functional unit will update the valid bit accordingly. If the instruction is completed in the functional unit and its age indicates that it has passed the end of the IU line and is still valid, the functional unit can update the user's visibility status of the machine. Furthermore, if in a functional unit, the instruction has not been completed and its

Page 101235331 Amendment No. 92119613_ V. Description of the Invention (5) The end of the line is still valid, then work: [0014] Therefore, in order to achieve the above objective, a microprocessor instruction is provided to indicate- The special register includes the first plurality of storage elements, each: this instruction is an instruction executed by the first functional unit. The storage of the 7G pieces of this Yayako _ energy unit's multiple pipeline stages: said: 〖stored in the second power; including the second plurality of storage elements 丄; this refers to: "line" of the register line = factory unit Stored in Yiyue: Should-instructions stored in one: m: Whether the specified instruction of a plurality of storage elements is valid. Valid bit 70. This valid bit is used by [0015] ι 田 面 'The-feature of the present invention is to propose a coherence, and the second one; the second f is to maintain the instruction type Λ between the two instruction pipelines instead of running synchronously' ::: "于-instruction queue The register will "store N instructions. This queue register has N items for the purpose _ logic 4 device: ^ should be temporarily stored in the N instruction queue 2 to store the _ finger = middle mother solid Logic elements include-age temporary storage: which of which-order 7 is also stored in the first 7 of the two pipelines. The N instructions Y,-, logic ^ # effect position. Each logic element Also includes page 111235331 _Case No. 92119613_ Year Month Revision _ V. Description of the invention (6) Including a multiplexer, which selects a plurality of valid bits based on the age signal A signal is provided to the active register. The plurality of valid bits corresponding to a first signal line means a plurality of stages of stored instructions is valid.

[0 0 1 6] In another aspect, a feature of the present invention is to provide a microprocessor. The microprocessor includes a first instruction pipeline including a plurality of stages for storing instructions. The microprocessor also includes a second instruction pipeline coupled to the first instruction pipeline to receive a first portion of the instructions from the first instruction pipeline and execute them. The microprocessor also includes an instruction queue register for storing a second part of the first part of the instruction until the second instruction pipeline is ready to execute the second part. The microprocessor also includes a control logic coupled to the instruction queue register to store a current state of each instruction of the second part and a valid bit. This current state indicates which stage of the first instruction pipeline stage the instruction of the second part is stored in.

[0 0 1 7] On the other hand, a feature of the present invention is to propose a method for maintaining consistency of instruction states among functional units in a microprocessor. The stages of the microprocessor are not due to the existence of a queue. alignment. The method includes storing an instruction in a pipeline stage of a first functional unit, storing a first significant bit of the instruction in this pipeline stage, and storing the instruction in a queue of a second functional unit until The second functional unit is ready to execute the instruction. The method further includes storing a second significant bit of the instruction in the

Page 12 1235331 said --- ^ ~ tM 92120 ^ Amendment V. Description of the invention (7) 丨 in the queue 'and storing the' ~~ out of the instruction in the queue are stored in the queue. This age refers to the ^ receive-signal, whose display is ::: solid pipeline stage. This method

I and second significant bit. The text position and the reception of the signal, update this SI processing "1 2 21 / column V storage" The clear and broad item feature is to propose-a kind of micro-plurality of storage elements #, 丄 1; the two-two instruction list register includes First =. The instruction is also stored in: from the first functional unit: connected to the-plurality of storage elements, each: ;; the number of storage elements' is to store the first plurality of two storage elements 丨 age. This age is designated! :: Single :: The state of the instruction of the == ... two functional unit pipeline stages [0 0 1 9] An advantage of the present invention is that ^ .1 f # ϋ 1 ^ ^, tti; & ^ ^ Delay caused by the end of the pipeline. In its place, the queue of early offenders is placed in an earlier pipeline stage, while ensuring that the instruction can be positive = Xu Jiangzai [0 0 20] Other features and advantages of the present invention are provided in the configuration | and attached drawings Later, it will be more prominent. j 灰 月 [Embodiment] [0 0 2 6] Please refer to FIG. 2 ′, which is a block diagram of a microprocessor 2000 according to the present invention. The microprocessor 2 0 0 includes an integer pipeline 2 0 2. One time. “B. Cache Cache 1253331 Case No. 9212% β 丨 Year” Five. Description of the invention (8) One by one memory 2 0 4. One MXU Pipeline 2 0 6,-Order queue register 2 1 2. [0 0 2 7] Integer pipeline 2 02 includes R-stage 2 2 1, A-stage 2 2 2, paragraph 2 2 5, 8-stage 226, and register register of all data stored by the households. These operations The unit, the processor's control and status register, and the address of the instruction pointer or process to generate the memory address generate the data phase, which is used to retrieve data from the memory. The data is memorized by the data cache -MXU data queue 208 and an MXU refers to a plurality of phases connected together, including D-phase 2 23, G-phase 224, E-phase 22 7. The R-phase 221 includes data such as instruction operands, address generation status information, flags, stacked indicators, and district counts. A-phase 2 2 2 includes appliances. D-stage 223 and G-stage 2 24 are loaded into data cache memory 204 and sent to G-stage 224. E-phase 2 2 5 includes execution units such as arithmetic logic units that perform integer arithmetic or logical operations. S-stage 2 2 6 includes logic to store the command results in memory and data cache memory 2 0 4. W-phase 2 2 7 includes logic to write the instruction results back to R-phase 221. That is, W-stage 22 7 is used to update the user-visible state of the microprocessor 2000. w-stage 2 2 7 also discards the instruction and is the last stage of the integer pipeline 2 0 2. In addition, W-phase 2 7 will provide an operator transfer function to transfer the results to G-phase 2 24, E-phase 2 2 5 and S-phase 2 2 6 in the integer pipeline 202. [0 0 2 8] R-Phase 2 2 1 will receive instructions 2 7 6 from other integer pipeline phases 2 0 2 (such as instruction fetch and decode phases) which are not shown in the figure. The instruction 2 7 6 will go down each stage of the integer pipeline 202 until it reaches the final stage of the integer pipeline 202, which is W-phase 2 2 7. When the instruction is decoded, it is also sent to other appropriate functional units according to the type of decoded instruction. In particular, the MMX instruction is sent to the MXU pipeline 206. In one embodiment,

Page 14 1235331 V. Description of the invention No. 92129613 (9) 丨 Replace 4 Modification The floating-point instruction will be sent to the floating-point functional unit. [0 0 2 9] The MX U pipeline 206 includes a plurality of stages connected together, similar to and mostly corresponding to the integer pipeline 202. Μ XU pipeline 2 0 6 includes R-phase 2 6 1, R 2-phase 2 6 2, A-phase 2 6 3, D-phase 2 6 4, G-phase 2 6 5, E-phase 2 6 6, S-phase 2 6 7, W-phase 2 68 and M-phase 2 6 9. In a consistent embodiment, the MXU pipeline 206 with a name corresponding to the integer pipeline 202 stage performs similar functions. In particular, E_stage 2 6 6 includes execution units, such as arithmetic logic units, to execute multimedia instructions. [0 0 3 0] R 2-stage 2 6 2 is an additional register stage, which provides a clock The cyclic delay gives the data cache memory 2 04 to send the data to the MXU official line 206. Since there are R2-stages 2 6 2, the MXU pipeline 20 6 will move down by one more stage than the integer pipeline 2 02. Therefore, the D-phase 264 of the μ X u pipeline 20 6 will correspond to the G-phase 2 24 of the integer pipeline 202. M-phase 2 6 9 performs a result write-back function to update the user-visible state of microprocessor 2000, similar to W-phase 22 7 of integer pipeline 202. In addition, the M-phase 269 will provide an operand transfer function to transfer the results to G ^ 2 265, E-phase 266 or S-phase 266 of the pipeline. When the instruction reaches the M-level, 2 6 9, the M-phase 2 6 9 breaks according to whether the instruction is valid and which stage of the integer official line y 0 2 has been reached, or whether the instruction has been discarded from the integer pipeline 2 02. Do you want to update the user's visible status of the microprocessor 2000 or transfer it? The validity and the stages reached are recorded by the Mxυ instruction as detailed below in conjunction with the remaining diagrams. Ancient [0 0 3 1] The same R-stage 2 2 1 to D-stage 2 2 3 of the integer pipeline 2 0 2 The same cardiac conditions are also applicable to the R-stage 261 to A-stage of the MXυ pipeline 206

Page 15 1235331 _Case No. 92119613_Year Month and Date _ Zheng V. Description of the invention (10) 2 63. Therefore, the instructions that have reached the D-phase 2 64 of the MXU pipeline 206 also synchronously reach the G-phase 2 2 4 of the integer pipeline 202. However, the pause or movement of instructions in the D-phase 2 64 to M -phase 2 6 9 of the MXu instruction queue register 2 12 and the M XU pipeline 2 06 is controlled by another set of conditions. The control conditions are different from the G-phase 224 to the W-phase 2 2 7 of the integer pipeline 2 02 phase. That is, the MXU instruction queue register 21 2 and the MXU pipeline 206 are D-phase 2 64 to M-phase 2 6 9 and the integer pipeline 20 02 is G-phase 2 24 to W-phase 2 2 7 operations are asynchronous. [0 0 3 2] The R-phase 261 of the MXU pipeline 2 0 6 also selectively receives the instructions 2 7 6 from the instruction fetch and decode phase of the integer pipeline 202. Therefore, if the instruction 2 7 6 is an MMX instruction, when it is fetched and decoded, it will go through the integer pipeline 2 0 2 and will go down the various stages of the MXU pipeline 2 0 6 until it reaches the M XU pipeline 2 0 6 The final phase (M-phase 2 6 9) and the final phase of the integer pipeline 2 0 2. Depending on the existence of certain conditions (such as in conjunction with the description in Figure 3), instruction 2 7 6 will also pass the MX U instruction queue register 2 1 2 on the path to the end of the MXU pipeline 206. [0 0 3 3] The M × U data queue 208 is coupled to the data cache memory 2 04 through a data bus 2 7 4. The MXU data queue 2 08 includes a plurality of storage elements (called queue items) for storing data received from the data cache memory 2 04 on the data bus 2 7 4. In the embodiment of FIG. 2, Μχυ 彳 彳 彳 列 2 08 includes five items. The mxu data line 208 will send data from its bottom item to the G-phase 26 5 of the MXU pipeline 206. '[0 0 34] Architecturally, the Mxυ instruction queue register 21 2 is located in the D-stage 264 of the MXU pipeline 206. The MXU instruction queue register 21 2 includes a plurality of storage elements (called queue items) for storing the data received from D_stage 2 64.

Page 16 1235331

Case No. 921296U 5. Instructions for Invention (11) Directive. In the embodiment of FIG. 2, the instruction queue register 21 2 includes five queue items, which are not QDO 240, QD1 241, QD2 242, QD3 2 4 3, and Q D 4 2 4 4. Q D 0 2 4 0 is the bottom item of the MX U instruction queue register 2 12, and QD 4 244 is the top item of the MXU instruction queue register 212. That is, when the MXU instruction queue register 21 2 is full, Qj) 0240 is located at the head of the MXU instruction queue register 212 and holds the oldest instruction, while QD4 244 is located in the MXU instruction queue The end of the register 212 holds the latest instruction. When the instruction enters the MXU instruction queue register 212, it enters the first empty item closest to the bottom or head of the MXU instruction queue register 2 1 2. For example, if the instruction is occupying QD0 240 and QD1 241 and QD2 242 is the next empty item ’, the incoming instruction will be stored in QD2 242. If the MXU instruction queue register 21 2 is completely empty, the instruction will be stored in QD〇 240. [0 0 3 5] D-stage 2 64 of the MXU pipeline 2 0 6 also includes a multiplexer 2 1 4 with two inputs. The first input of the multiplexer 2 1 4 receives instructions directly from the D-phase 264. The second input terminal of the multiplexer 21 4 receives the instruction from QD〇 24〇, that is, the bottom item of the MXU instruction queue register 2 12. The output of the multiplexer 2 1 4 will select the instruction from the two inputs to send it to the G-phase 2 6 5 of the Μχ υ pipeline 2 0 6. When an instruction reaches D-stage 2 64, if this instruction is valid and the MXU instruction queue register 21 2 is empty, and the MXU pipeline 2 0 6 is moving (that is, not paused), the multiplexer 2 1 4 will The first input is selected to send the instruction directly to G-stage 265, thereby bypassing the MXU instruction queue register 212. However, if the MXU instruction queue register 21 2 is not empty or there is a pause in the MXU pipeline 20 6, the multiplexer 21 4 will select the second input to send the instruction in qd〇24 0 to the g-stage 2 6 5 until MXU instruction queue register 21ι

Page 17 1235331 Case No. 92129613 V. Description of the invention (12) When there is no instruction. [00 0 6] Please refer to FIG. 3, which is a block diagram of logic 3 0 for controlling the MX × 8 in FIG. 2 of the present invention to temporarily store 2 1 2 as the logic. Control logic 3 includes four multiplexers (labeled as multiplexer 1 302, multiplexer 2 304, multiplexer 3 30 6 and multiplexer 4 316), an age register 312, and a valid register Save ^ 3 0 8 and other related logic. For each instruction stored in the Mxυ instruction queue register > 212, the control logic 3 0 0 will record its age and state bits. The age and valid bits are stored in the age register 3 and the valid register 308, respectively. In the embodiment of FIG. 3, the age register 32 includes two bits, and the valid register 30 includes one bit. ° [0 0 3 7] In Figure 3, the age of the instruction is marked as "ps", which is the present state. The age of the directive indicates its current stage in the 敫 P pipeline 202. That is, the correspondence between the age value and the position of the instruction at the stage of integer == 2 0 2 is as follows: & Line 0 0 = E of integer pipeline 2 0 2 ~ Stage 2 2 5 0 1 = S of integer pipeline 2 0 2 -ρ 2 2 6 1 0 = W of integer pipeline 2 〇 2-W 2 of integer pipeline 2 2 7 1 1 = W beyond integer pipeline 2 〇 2-Phase 2 2 7 [0038] Therefore, once the instruction reaches u's Age, if its Ge Yuan is still in the set state, MXU knows that the instruction will complete and the processor state visible to the user. In Fig. 3, "NS" indicates the next stage of the pipeline 202. [0 0 3 9] Each MXU instruction queue register 2 丨 2 is equipped with the control logic 300 of FIG. 3. That is, for the five items in FIG. 2 that are queued and ancient, ° will be matched with the five sets of control logic 3 0 in FIG. 3. In the configuration of the Suining column, " "

Case No. 92129

1235331 V. Description of the invention (13) The control logic 3 0 0 is coupled together so that in the M × υ instruction queue 212, the output of the related control logic 300 of an item will become the control logic of the next item 3 0 0 inputs. In Figure 3, "γ your branch, Jin Liukoukou 9 1 9 is composed of one. A s α χ" means a known item in the MXU instruction queue temporary storage state 2 1 2, r χ + 丨 "means, ... the next highest or latest item or item in the column register 212. Because: ps (o) is the oldest or lowest item in the queue (that is, the age of qd〇24㈧ in Figure 2. 卞 [0 0 4 0] control logic 3 0 0 includes one; multiplexer " 02. More The tool " .2 includes three pairs; it is VaUX) 344 and Val (X + "342. No .: H input 354 and PS (X + 1) 3 52. No. = needle input a is, QCO brother pair input is NS (X) 364 and NS (X + 1); 〇b Z ° [004 1] The signal Val (X) 344 is the output of multiplexer 4 316. The table of MXU instruction queue register 212 is torn and stored. Is the instruction currently. The signal Va1 (X + 〇342 is the output of the multiplexer 4 316 of item ^ 1 of the MXU instruction queue register 212, which indicates whether the instruction of the item χ + i is currently valid. [0042] Signal PS (X) 354 indicates the current age of the instruction stored in item X of the MX × instruction queue temporary cry 212, which is stored in the instruction. The age register 312. That is, PS (X) 354 represents an integer Which stage of the pipeline 202 holds the instruction that is also stored in the item χ of the MXU instruction queue register 2 丨 2. The signal PS (X + 1) 3 5 2 indicates that the Mxu instruction queue register 12 Item X + The current age of the order is stored in the age register 312 of the order. [0043] Control logic 300 also includes logic 322, which is based on ps (x)

Page 19 1235331

3 54 and signal B (1 乂-? 3 76 generate signalization (乂) 364, as shown in truth table 1 of Figure 4. If the instruction is initially loaded into the MXU instruction queue register 2 丨 2 items In X, LdX-P is true or enabled (act i ve). For the integer pipeline stage 202 of the instruction stored in item X of the instruction queue register 212, the signal NS (X) 3 64 indicates the following The next integer pipeline stage 202. For the integer pipeline stage 2 0 2 which holds the item χ + 丨 of the MXU instruction queue register 2 丨 2, the signal NS (X + i) 3 6 2 shows it. The next stage is an integer pipeline of 202. As shown in Table 丨 of Figure 4, if the instruction is initially loaded into the 〇υ instruction queue register 212, ^ (乂) 3 64 is 〇〇, which corresponds to Integer official line 2 0 2-stage 225. Otherwise, ^ 8 (\) 3 6 4 is determined by? 8 (\) 354 and HldX-P 372, as shown in Table 1 of Figure 4. [〇〇 44] Please refer to Figure 3 again, the multiplexer! 302 will input H ldX_P 372 according to a selection, and select one of each of the three pairs of inputs. HldX-P 37 2 represents the MXU instruction queue Whether the items in the register 21 2 are shifted downward. When an instruction is to be shifted down in the MXU instruction queue register 21 2, for example, because an instruction is to be moved from the MXU instruction queue register 2 丨 2

Removal of 'HldX-P 372 will become inactive. Disabled HldX P 3 7 2 will cause the multiplexer 1 3 0 2 to select Val (X + 1) 342, PS (X + 1) 3 from the higher item below the MXU instruction queue register 2 1 2 52 and NS (X + 1) 3 6 2. The enabled HldX-P 372 will enable the multiplexer 1 3 0 2 to maintain the current items Val (X) 344, PS (X) 3 5 4 and NS (X) from the MXU instruction queue register 212. 3 6 4 value. The multiplexer 1 3 0 2 will provide the selected next stage value in the output signal ns 3 9 2, provide the selected state value in the output signal PS 3 9 4 ', and output the signal V a 1 3 The selected significant bit value is provided in 9 6.

Page 20 1253331 Case No. 92119613 Amendment V. Description of the Invention (15) [0045] The control logic 30 0 also includes a 3: 1 multiplexer coupled to the multiplexer 1 302, labeled as multiplexer 2 3 0 4. The multiplexer 2 3 0 4 is used to update the age of the instruction in item X to its appropriate value. The multiplexer 2 3 0 4 will receive three command status values, that is, three sets of values containing a valid bit and two age bits, and select one of the status values to output. The first command status value includes PS output 3 94 and Val output 3 9 6 of the multiplexer 1 3 0 2. That is, the first instruction state includes the age selected by the multiplexer 1 3 0 2 from PS (X) 3 5 4 and PS (X + 1) 3 5 2 and the multiplexer 1 3 0 2 from Val (X) 344 and Val (X + 1) 342. The second command state value includes the N S output 3 9 2 and the V a 1 output 3 9 6 of the multiplexer 1 3 0 2. That is, the second instruction state includes the age selected from the multiplexer 1 302 from NS (X) 364 and NS (X + 1) 3 6 2 and the multiplexer 1 3 0 2 from Val (X) 344 And the valid bit selected in Val (X + 1) 342. The third instruction state value includes a value of 0 0 0, that is, the effective bit is 0 and the age is 0 0, which specifies the E-phase 225 of the integer pipeline 2 0 2. [0046] The multiplexer 2 30 4 inputs age-update 382 according to a two-bit selection, and selects one of the three instruction state values. Logic 3 2 2 will generate the signal age —update 3 according to the equation shown in Table 2 below according to signal PS 3 94, reset signal 374, signal 1 ^ \ —? 376 and 63 7 6_person signal 3 78. 8 2. In Table 2, the PS [0] and PS [1] bits are the two bits of the output of the multiplexer 1 3 02 said 5 tiger PS 394. age_update [1] = LdX—P | reset; age_update [0] = Gate—A 丨 PS [0] 丨 PS [1]; Table 2

1235331 SE 92129613 V. Description of the invention (16)

[0 0 4 7] True value LdX — p 3 76 indicates that the item X of the Μχυ instruction queue register 2 1 2 is loaded with instructions from the D phase 264, not already, and is located in the MXU instruction symbol. Instruction in column register 212. A true reset signal 374 indicates that the MXU instruction queue register 212 is being reset. The straight Gatej 3 78 series indicates that there is no pause in the integer pipeline 202. In the embodiment of FIG. 3, G a te-A 3 7 8 only indicates that there is no pause at the stage above the s-stage 2 2 6 of the integer pipeline 202. That is, in the embodiment of FIG. 3, the s_phase 226 f W-phase 22 7 will not pause, so that once the instruction reaches 彡 s phase m, it can be ensured that the instruction will become old in the next clock cycle. That is, the instruction will continue to W-stage 2 2 7 of the integer pipeline 2 02. Similarly, once the instruction reaches W-phase 22 7 ', it is guaranteed that it will be discarded. Although the control signal can be obtained from Gate_A 378, the pause or movement of MXU pipeline 206 is controlled by its own control signal instead of Gate-A 378.

[0 048] If a reset occurs or the instruction is loaded from the D-stage 2 64 of the Mxυ pipeline 2 0 6 into the item X of the MXU instruction queue register 212, the equation of Table 2 specifies the multiplexer 2 3 0 4 To select the third command state input. If the instruction is moving to the next integer pipeline stage 202 (that is, if the integer pipeline 2 has not stalled, as shown by the true Gate-A 3 78, or if the instruction has reached at least the integer official pipeline 2 0 2 S-Phase 2 2 6 as shown by ps 3 9 4 of these values of 〇1, 〇 or 丨 1) 'The multiplexer 2 304 will select the second command state input (including NS 3 9 2 and Val 3 9 6). Otherwise, the instruction will stall in the integer pipeline 202, that is, it will not continue to move down the integer pipeline 202; therefore. The multiplexer 2 304 will select the first command state (including ps 3 94 and vai 3 9 6). [0 0 4 9] The age portion 3 8 4 of the multiplexer 2 3 0 4 is used as the input of the age register 31 2. The output of the age register 31 2 is the signal

I Page 22 1235331-You 29613__year-month-day_Hi_ V. Description of the invention (17)

PS (X) 354 is used as the input of logic 322. The signal ps (x) 354 is also sent to the next lower item of the MXU instruction queue register 2 1 2 and becomes PS (X + 1) 3 5 2 of item X-1. Similarly, the signal NS (X) 364 will be sent to the next lower item of the MXU instruction queue register 2 1 2 and become the item 1 to 1 ^ (\ + 1) 362. Similarly, signals 781 and 344 are sent to the next lower item of the MXU instruction queue register 2 1 2 and become ¥ 31 (\ + 1) 342 of item X-1. In addition, the signals “1 (〇) 344 and? 8 (0) 3 54 of the lowest item (ie, item (31) 〇24 0) of the queue register 212 of the ^^ 11 instruction will be sent to G- in FIG. 2 Phase 2 6 5 and down through the remaining phases of the MXU pipeline 2 06. When the instruction reaches M-phase 2 6 9 of the MXU pipeline 2 06, the M-phase 2 6 9 will double check the relevant state and tragedy value 'To determine whether the instruction is valid, and in which stage of the integer pipeline 202, to determine whether to update the user-visible state of the microprocessor 200. [0050] The control logic 300 also includes a coupling The 4: 1 multiplexer up to multiplexer 2 304 is labeled as multiplexer 3 3 0 6. The multiplexer 3 3 0 6 is used to update the valid bit of the instruction in item X to its proper value. Multi Tool 3

3 0 6 receives four valid bit inputs. The first significant bit input is va 1 output 386 ', which is the significant bit portion of the output of multiplexer 2 30 4. The other three significant bit inputs are G-phase 2 2 4, E-phase 2 2 5 and S-phase 22 6 from the integer pipeline 2 0, which are marked as MmxValNxt_G 336, MmxValNxt-E, respectively. 334 and MmxValNxt-S 332. The output of multiplexer 3 306 is used as the input of valid bit register 308. [0051] The multiplexer 3 30 6 selects one of the four valid bit inputs according to a selection input, that is, the age portion 384 of the output of the multiplexer 2 304. Therefore, if the age of the instruction 3 8 4 is 0 0, the multiplexer 3 3 0 6 will start from

Page 23

1235331 Min: T _ Case No. 92129611 one by one ......... Leap year date 洎 Day 绦 _ V. Description of the invention (18) G stage 2 2 of integer pipeline 2 2 4 Select valid bit 3 3 6. This is because the instruction is loaded from the D stage 264 of the MXU pipeline 206 to the MXU instruction queue register 212, which is equivalent to loading the instruction from the G stage 224 of the integer pipeline 202. That is, since R 2-the existence of phase 2 6 2, Μ XU pipeline 2 0 6 will be shifted down by one phase relative to the integer pipeline 2 0 2, so the D phase 2 6 4 of the MXU pipeline 2 0 6 will be the same as the integer pipeline 2 0 2 The G stage 224 is adjacent; therefore, the effective bit of the instruction of the G stage 2 2 4 of the integer pipeline 202 is the corrected effective bit to be loaded into the effective bit register 3 0 8. [0052] If the age of the instruction 38 4 is 0 1, the multiplexer 3 3 0 6 will select a valid bit 334 from the E stage 225 of the integer pipeline 2 0 2. If the commanded stomach age 3 8 4 is 10, the multiplexer 3 3 0 6 will select the valid bit 332 from the S-phase 2 2 6 of the integer pipeline 2 0 2. Finally, if the age of the instruction is 384, the multiplexer 3 30 6 selects a valid bit 386 from the output of the multiplexer 2 30 4. That is, 'will keep the current significant bit value. Therefore, once the instruction passes the W-phase 2 2 7 of the integer official line 2 02 (that is, it is discarded by w-phase 2 2 7), the valid bit value will be retained because at this moment when the instruction is invalidated After that, no conditions or events will occur. [0053] The control logic 300 also includes a 2.1 multiplexer ' coupled to the multiplexer 3 306, designated as multiplexer 4 316. If an invalidation condition or event is generated when the instruction is in the integer tube, W-stage 2 2 7 of 002, the multiplexer 4 3 1 6 will be used to update the valid bit. The multiplexer 4 3 丨 6 will receive two valid bit inputs. The first round of input is from the output of the valid bit register 308. The second input is the output of AND gate 3 丨 4. AND gates 3 丨 4 are AND gates with two inputs. The first input of the AND gate 3 1 4 is the output of the valid bit register 308. And the second input of gate 314 is £ ^ 6 ^-reverse signal of Pei 338, 1235331 case No. 92119613 ί year library is amended V. Description of the invention (19) It is marked as "Except -W" in Figure 3 338 ". The true Ex cep t_W signal 338 indicates that when the instruction is in the W-phase 22 7 of the integer pipeline 202, an exception occurs and the instruction is invalidated. Therefore, if the instruction was previously invalid, or an invalidation exception occurred when the instruction was in the W-phase 2 2 7 of the integer pipeline 202, the AND gate 3 1 4 will produce a false value output. [0 0 5 4] The multiplexer 4 31 6 will select one of the valid bit inputs according to a selection input, which is the output of the comparator 3 1 8. The comparator 3 1 8 receives the age of the instruction from the output of the age register 3 1 2 and compares this age with the binary value 1 0, which is the w-stage 2 2 7 of the specified integer pipeline 2 0 2 'As mentioned before. If the age is 10, the comparators 3 and 8 will output a true value, so that the multiplexer 4 3 1 6 selects and the output of the brake 3 1 4. Otherwise, the comparator 3 1 8 will output a false value, and the multiplexer 4 3 1 6 selects the output of the valid bit register 3 08. The output of the multiplexer 4 316 is a Val (X) signal 344, which shows M) (IJ instruction The current valid bit M in the instruction X of the register 212 M: MXU [0055] In the manner just described, multiple The multiplexer 3 30 6 and the multiplexer 4 乂 6 can indeed keep the latest valid bit value of the instruction. This can be achieved by obtaining the valid bits 332, 334, and 336 from the integer two ^ 20 2 because if it is; When the = passes through the integer pipeline 2 02, any invalidation condition occurs :::: The processor m will update the valid bit of the instruction in the integer pipeline 2.2, J error is achieved by invalidating the instruction; or- Refers to the person: hanging ...- phase 227, by retaining a valid integer pipeline [00〇6] Now please refer to Figure 5, which is an example of the operation of Taisu Yueri. Figure 5 俜 Xiangan / \ ^ 的 图 2 Microprocessor 2 〇〇 .__ 相 "丁 歹" temporarily stores the initial state of Jie 212. Figure 5 goes further-step by step

Page 25 1235331

The downward flow chart, the operation of the next clock 2 1 2-fc tiger 9212 ^ 13 V. Description of the invention (20) Improper instructions based on the aforementioned initial conditions and other events, 2 integer pipeline 2 2 2 and MXU During the 212-hour cycle (referred to as clock 2) of the instruction queue register, the MXU instruction queue register is shaped. [0057] During clock 1, Figure 5 shows the MXU instruction queue temporary storage @ 212 item 3 (ie _ 243) marked as "^ rA" D = save = clock 1 period, lnstr The recording is located at the w_ stage 227 of the integer pipeline 202. The age of instr A stored in the age register 312 of FIG. 3 in item 3 is 10. That is, the PS (3) signal 354 of FIG. 3 has a value of 10, as shown in FIG. 5 as π =. Therefore, the logic 322 of Fig. 3 will generate the NS (3) value, as shown in Fig. 5. That is, in the clock theory, instr A is effective. Therefore, the value stored in the valid temporary storage for 308 is true, and the Val (3) signal 344 is also true, as shown in FIG. 5. ^ [〇〇58] During clock 2, because instr A is not loaded into the MXU instruction queue register 21 2, that is, instr A already exists in the MXU instruction queue register 212, so Ld2_P signal 3 The value of 76 is false, as shown in the figure. Moreover, during clock 2, because i n s t r A goes down through integer pipeline 2 02, that is, there is no pause in integer pipeline 202, so the value of Gate — # 3γ8 is true, as shown in the figure. Moreover, during the clock 2 period, the value of η 1 d 2-P signal 3 72 is false (as shown in the figure), which indicates that the bottom item of the instruction queue register 2 1 2 has been removed, so it is stored in The instruction in the MXU instruction queue register 2 1 2 item 3 will be shifted down to item 2. Furthermore, during the clock 2 period, the value of the Except_W signal 338 is true (as shown in the figure), which means that an event that invalidates i n s t r A has occurred. [0 0 5 9] Knowing these initial conditions and events,

1235331 _Case No. 92129613 Car month a 绦 正 5. Project description 2 of the invention description (21) and the MXU instruction queue register 212 and the control logic of Figure 3 control logic 3 0 0 will operate as follows. Because Ps (3) 354 has a value of 10, the comparator 3 1 8 will produce a true value output, and the multiplexer 4 3 丄 6 of item 3 will remotely select the output of the gate 3 1 4 (its value 〇, this is because insfr a is located at w-stage 2 2 7, an invalidation exception occurs). Therefore, during clock 2, a Val (3) signal 344 of false value will be generated to indicate that inst] r A is invalid. [0 0 6 0] because Η 1 d 2 — P 3 7 2 is false (meaning μ X U instruction queue is temporarily stored

Shift 2 1 2 forward and downward), so the MXU instruction queue register 2 1 2 multiplexer 1 30 2 of item 2 will select the value of "乂 +1", that is, select] ^ (3) 354 , NS (3) 364 and Val (3) 344, which are 10, ^, and 0, respectively. Since instr A will go down through the integer pipeline 202, which is represented by the true Gate_A 37 \, the multiplexer 2 3 0 4 of item 2 will select the N S output of the multiplexer i 3 002 3 9 2. Therefore, at the end of Clock 2, the new age of 113 "people stored in the age register 312 of item 2 will be 11, which shows that [151 ^ A has passed the W-stage of the integer pipeline 2 02 227. Because of the multiplexer 2 of project 2

The age output part 3 3 4 of 3 0 4 is 1 1 ′ as described above, so the multiplexer 3 30 6 of item 2 will select the Val output 386 of the multiplexer 2 30 4. Since Vai (3) 3 4 2 is 0 (as described above), the value of va 1 38 6 input to the multiplexer 3 3 6 of item 2 is 0, and the multiplexer 1 30 2 and more of item 2 The multiplexer 2 304 will select Val (3) 342 as the input to Val 386 of the multiplexer 3 30 6. Therefore, at the end of clock 2, the new valid bit stored in the valid register 3 0 8 will be 0 (meaning that instr A is now invalid) to inform the MXU pipeline 2 0 6 'The microprocessor 2 cannot be updated. 0 0 corresponds to the program state visible to users of instr A. [0 0 6 1] Although the present invention and its objects, features, and advantages have been described in detail

Page 27 1235331 Λ Amendment No. 5 5. Description of the Invention (22) Other embodiments described in the description may also be included in the scope of the present invention. For example, although the instructions and information as part of the MXU have been described in the present invention, the invention can also be applied to various other types of functional units, such as a stream SIMD extension (SSE) unit. Furthermore, although the present invention has been described with reference to the visible state of the user of the x86 processor, the present invention is still applicable to various processors. This =, although the processor described in the present invention is a functional unit that executes instructions or operations with integer pipelines, this issue ^, and also executes: the processing of other and / or additional functional units to perform effective functions is still appropriate Longer than two, although the present invention has described maintaining integer pipelines and μμχ pipelines == ::: consistency to know whether and when the MMX pipelines can be updated ?: by: see the purpose of the state 'but the present invention is generally: Separate status-consistency issues related to queued functional units. Because of the existence of non-synchronous queues between any different functional units, so that: 'for the problem, the present invention can be used to maintain the same state. " Status deviation In short, the above-mentioned one, when the present invention can not be limited: only the preferred embodiment of the invention, the patent range is made equal changes: the target range. Anyone who is within the scope of the application in accordance with the present invention is kindly requested to submit your trial and / or decoration, which should still belong to the second to the present prayer. Pei reviewer Ming Jian, and pray for accurate, is the

1235331 Case No. 9212961 $ Amendment Brief description of the drawing [Ο Ο 2 1] Figure 1 shows a conventional microprocessor, which has a function unit queue at the end of the integer pipeline. [0 0 2 2] FIG. 2 is a block diagram of a microprocessor of the present invention. [0 0 2 3] FIG. 3 is a block diagram of the logic for controlling the MXU instruction queue register of FIG. 2 according to the present invention. [0 0 2 4] FIG. 4 is a truth table of the next state value generated by the logic of FIG. 3 of the present invention. [0 0 2 5] FIG. 5 is an operation diagram of the microprocessor of FIG. 2 according to the present invention. The drawing numbers explain 100, 200 4-effect processors 102, 276, instructions 104,, 202 integer pipeline 106 queue 204 data cache memory 206 MXU pipeline 208 MXU data cache memory 212 MXU order queue queue register 214 Multiplexer 221, 261 R-Phase 222, 263 A-Phase 223, 264 D-Phase 224, 265 G-Phase 225, 266 E-Phase ❿

Page 29 J-Dagger1235331 Case No. 92119613 Brief description of the revised schema 2 2 6, 2 6 7: S-phase 2 2 7, 2 68: W-phase 262 269 274 300 302 304 306 308 312 314 316 318 332 334 336 338 342 344 352 354 362 364 R 2-Phase M-phase data bus 3 2 2: Logical multiplexer 1 Multiplexer 2 Multiplexer 3 Effective register Age register and gate multiplexer 4 Comparators

MmxVa1Nxt_G MmxValNxt_E MmxVa1Nxt_S Except —W signal Val (X + 1) Val (X) PS (X + 1) PS (X) NS (X + 1) NS (X)

Page 30 1235331 Case No. 92129613_Year_Month_Amendment

Schematic description 3 72: HldX 3 74: Reset signal 3 7 6 · · LdX_P 3 78: G a ΐ e — A signal 38 2 · · Signal age one-to-one update 384: Age output part 38 6: Val output 3 9 2: Output signal NS 3 94: Output signal PS 3 9 6: Output signal Val Page 31

Claims (1)

i cP m book or 1253331 case No. 92119613 amendment 6, the patent queue of the patent application type microprocessor queue register, including a plurality of first storage elements, each first storage element stores one by instruction, This instruction is also stored in a second function sheet, a first function unit, a second storage, a second storage, a second storage, a storage age, a coincidence age, such as power finger 3, such as' ^ 4, such as after the determination 5, and so on.如 化 6 · If the plural of the yuan, the second storage element of the instruction, the functional unit of the third storage element, the instruction is valid. The result of the patent application unit enables the application of the patent to be visible. The patent application stage register is received, so that the patent application conditions include one of the scopes of the patent application and one of the three storages for one year. The instruction has no scope, and the micro scope executes the line stage storage element to store the ages. The plurality of storage elements stores one of the valid bits, which is coupled to the first storage element age to indicate which stage of the line stage , Coupled to the first storage element, the valid first storage elements, the instructions in each corresponding one are stored in the one; and the first storage elements, the corresponding ones in each One of the median bits is used to indicate an instruction queue register of the first item of the instruction, wherein the first age and the valid bit are used to determine whether to be visible to a user of the microprocessor. The second item of the instruction queue register is used in a register file of the microprocessor. The instruction queue register of the first item, wherein a command in the pipeline stages of the second functional unit of the command, in which a condition for the validity of the command to be stored in the predetermined stage may occur. The instruction queue item of item 4 is an exception in one of the invalid processors. The instruction queue register of item 4 is invalid. Page 32 1235331 _Case No. 92119613_ Year Month Amendment_ Sixth, the scope of the patent application includes a branch instruction made by the microprocessor to predict the result of the error. 7. The register for registering instructions in item 4 of the scope of patent application, wherein the invalidation condition includes a pipeline operation stop in one or more of the first and second functional units. 8. For example, the instruction queue register of the scope of patent application, wherein the instruction queue register is removed from the second functional unit before an instruction discarding stage among the pipeline stages of the second functional unit. One of the pipeline stages receives the instruction. 9. If the instruction queue register of item 1 of the scope of patent application, the microprocessor may invalidate the instruction after the instruction is stored in the instruction queue register. 10. The instruction queue register of item 1 in the scope of patent application, wherein the second functional unit includes an integer unit. 1 1. The instruction queue register of item 1 in the scope of patent application, wherein the first functional unit includes a unit for executing a multimedia instruction. 12. The instruction queue register of item 1 in the scope of patent application, wherein the first functional unit includes a unit for executing a floating-point instruction. 13. The instruction queue register of item 1 in the scope of patent application, wherein the first functional unit includes a unit for executing the SSE instruction. 14. If the instruction queue register of item 1 of the patent application scope further includes: a control logic coupled to the second and third storage elements for updating the age and the valid bit. 1 5. If the instruction queue register of item 14 in the scope of patent application includes: Page 33 1253331 _ Case No. 921296 ... "-Two Qin" Amended on the 1st of January_ Sixth, an input terminal for patent application scope is coupled to the control logic for receiving a signal from the second functional unit, the The signal indicates whether the second functional unit is stalled or is causing the instruction to move along the pipeline stages, wherein the control logic responds to the signal and updates the age and the valid bit. 16. If the instruction queue register of item 15 of the scope of the patent application is used, if the second functional unit is moving the instruction along the pipeline stages, the control logic increases the age. 1 7. If the instruction queue register of item 14 in the scope of patent application includes: A plurality of input terminals are coupled to the control logic, and each input terminal is used to receive a signal from the second functional unit, and the signal indicates that one of the pipeline stages of the second functional unit is also stored. Whether the instruction is valid, wherein the control logic updates the valid bit according to the signal. 18. If the instruction queue register of item 14 of the scope of patent application, the control logic will move the instruction from one of the first storage elements to the instruction queue according to the instruction queue register. The other one of the first storage elements to update the age and the valid bit. 19. If the instruction in the patent application scope item 14 lists the register, if The instruction is being loaded into the instruction queue register, and the control logic updates the age to an initial age value. 2 0. If the instruction queue register of item 14 in the scope of patent application, further includes: an input terminal coupled to the control logic for receiving a signal from the second functional unit, the signal indicates when the When the instruction is stored in a predetermined pipeline phase of the pipeline phases of the second functional unit, a Page 34 1235331 MM 92129613 Amendment Whether the invalidation condition of the patent application scope has occurred. When the instruction is stored in the predetermined pipeline stage, if the invalidation condition occurs, the control logic updates the valid bit to an invalid value. 21. If the instruction in the scope of application for the scope of the patent application 20 is temporarily crying, the predetermined pipeline stage in the bean includes the second functional unit-the final stage, in which the invalidation condition may be prepared. 22. Such as The instruction in item i of p range is listed in Y register. The processor determines whether to update one of the microprocessor's users with the result of the instruction based on the age and the valid bit. A device used to maintain the consistency of a Gamma state in a microprocessor. The two instruction line registers between the 122 pipelines separate them instead of being in line because the -instruction device has N items. ^^, the instruction symbol is temporarily stored in the N instruction columns temporarily: ":: J", the device has corresponding editing elements including: N logical elements of the project 'each logical six 23 one Age register, age, the age is received from a valid register stored in one of the two pipelines, a valid bit, and a 2-year-old signal used to store one of the N instructions, and indicates that the instruction also The first stage of the pipeline; a signal used to store one of the N instructions selects a plurality of valid bit valid registers, and the valid bits correspond to a multiplexer stored in the plurality of stages, according to the One of the age signals to provide to the Yuanyuan signal indicates whether the instruction of the first tube of green Λ is valid. 1235331 _ Case No. 92119613_ year month day amendment _ 6. Application for patent scope 24. For the device with scope of patent application No. 23, in which the N logic elements are coupled together to form a queue to correspond to the instruction Queue the N items in the register. 25. The device according to item 24 of the scope of patent application, wherein the N logic elements are coupled together to form a series of rows, so that one of the N logic elements output from the age register is coupled. Go to the next input of the N logic elements. 26. The device according to item 24 of the scope of patent application, wherein the N logic elements are coupled together to form a column, so that one of the valid registers of the N logic elements is output. Coupled to the next one of the N logic elements. 2 7. The device according to item 24 of the scope of patent application, wherein the bottom logic element of one of the N logic elements is coupled to a predetermined stage of the second pipeline of one of the two pipelines, so that the age and the effective Bits are provided to the predetermined stage. 28. The device according to item 27 of the patent application range, wherein the second pipeline selectively updates a register file of the microprocessor with the result of the instruction according to the age and the valid bit. 2 9. If the device of the scope of patent application No. 27, each of the N logic elements further includes: a second multiplexer, coupled to an output of the previous one of the N logic elements, according to the Whether the instruction queue register is shifted to selectively maintain the age and the valid bit, or receive the age and the valid bit from the previous one of the N logic elements. Page 36 1253331 / _ Case No. 92129613_ > year, month, day amendment _ six, the scope of the patent application 30. For the device of the scope of the patent application No. 23, each _ logic element further includes: an update logic, coupled to The age register is used to update the age according to whether a pause occurs in the first pipeline. 31. The device according to item 30 of the scope of patent application, wherein the update logic also updates the age according to the age signal. 32. The device according to item 23 of the scope of patent application, wherein the multiplexer also receives a valid input selectively coupled from an output of one of the valid registers. 3 3. If the device in the scope of patent application No. 23, each of the N logic elements further includes: an invalidation logic, coupled to the valid register, in response to an abnormal signal, the instruction Invalidation, the abnormal signal indicates that when the instruction is stored in a predetermined stage of the first pipeline, an exception that invalidates the instruction occurs. 3 4. A microprocessor with a plurality of functional units and using pipeline operations, including: a first instruction pipeline, including a plurality of stages, for storing instructions A second instruction pipeline coupled to the first instruction pipeline to receive a first portion of the instructions from the first instruction pipeline and execute them; an instruction queue register for Storing a second part of the first part of the instruction until the second instruction pipeline is ready to execute the second part Page 37 1253331 ^ 3 n _ Case No. 92129613 Heart · υ # υ Month day amendment _ VI. Patent application scope part; and a control logic coupled to the instruction queue register to store the second A current state and a valid bit of each instruction of the part, the current state indicates which stage of the first instruction pipeline stage the instruction of the second part is stored in. 3 5. The microprocessor of claim 34, wherein the operation of the instruction queue register and the second instruction pipeline is asynchronous to the operation of the first instruction pipeline. 36. The microprocessor according to item 34 of the scope of patent application, further comprising: a multiplexer coupled to the instruction queue register and the second instruction pipeline to selectively bypass the first instruction pipeline The instruction queue register in the two instruction pipeline. 3 7. If the microprocessor of the 36th scope of the patent application, if the instruction queue register is empty, the multiplexer will bypass the instruction queue register. 38. If the microprocessor according to item 37 of the patent application scope, wherein if the second instruction pipeline is stalled, the multiplexer will not bypass the instruction queue register. 39. The microprocessor according to item 34 of the scope of patent application, further comprising: a data cache memory coupled to the first instruction pipeline for providing the data specified by the instructions, and a data frame. Row, coupled to the data cache memory, for storing the goods specified by the second part of the instruction. Page 38 1235331 _Case No. 92119613 Rev. _ VI. Patent application scope 40. For the microprocessor of patent application scope item 34, the current status also indicates whether the instruction has been removed from the first instructions Discarded in the pipeline phase. 4 1. A method for maintaining the consistency of instruction states between functional units in a microprocessor. The phases of the microprocessor are misaligned due to the existence of a queue. The method includes: storing an instruction in a first A functional unit in a pipeline phase; storing a first significant bit of the instruction in the pipeline phase; Store the instruction in a queue of a second functional unit until the second functional unit is ready to execute the instruction; Store a second significant bit of the instruction in the queue; Age of one of the instructions Stored in the queue, wherein the age indicates which pipeline stage of the first functional unit the instruction is stored in; receives a signal indicating whether the first functional unit pipeline has a pause; and The age and the second significant bit are updated according to the reception of the first significant bit and the signal. 4 2. The method according to item 41 of the scope of patent application, wherein the update action includes incrementing the age if the signal indicates that the first functional unit pipeline has not stalled. 4 3. The method according to item 41 of the scope of patent application, wherein the update action includes maintaining if the signal indicates that the first functional unit pipeline has paused, Page 39 1235331 _ Case No. 921296k. 0 January 1 January January Amendment _ 6. Scope of patent application This age. 4 4. The method according to item 41 of the scope of patent application, wherein the updating action comprises updating the second valid bit with the first valid bit. 4 5. The method according to item 41 of the scope of patent application, further comprising: receiving a signal indicating whether a condition for invalidating the instruction has been generated; and if the signal indicates that the condition for invalidating the instruction has been generated, A value is stored in the second significant bit to show that the instruction is invalid. 46. The method according to item 41 of the scope of patent application, wherein the pipeline stage of the first functional unit is located before a stage of discarding instructions in the first functional unit. 4 7. The method according to item 41 of the scope of patent application, further comprising: judging whether to update a visible state of a user of the microprocessor according to the second significant bit and the age. 4 8. The method according to item 41 of the scope of patent application, wherein the age also indicates whether the instruction has been discarded from the first functional unit. 4 9. An instruction queue register used in a microprocessor, including a plurality of first storage elements, each of which stores a command for execution by a first functional unit, and the command is also stored One of a plurality of pipeline stages of a second functional unit; and a plurality of second storage elements coupled to the first storage elements, each of the second storage elements is used to store the first storages An age of the instruction stored in a corresponding one of the components, the age indicating one of the pipeline stages of the second functional unit, where Page 40 Page 41