1234930 狄、發明說明 【發明所屬之技術領域】 本發明係提供一種時脈產生器，由指— 遲鎖相迴路。 種用杬準日守脈相位的多級延 【先前技術】 現今幾乎所有積體電路上都會應用到時脈訊號，其係用以 資麵“ ，器一)，會在一時脈訊號的正 edge)改變其狀態；相對地，大型IC /負、、彖（fallmg 其他需要時脈調校的K：，其包含械千奸式邏輯陣列或 _ d / 男乂丁上萬個獨立電路或是裝置。一私& 二時觀號係、由時脈腳位輸人，然後再逐—分送至複=而 2此=脈訊舰時脈聽輸人，錢逐漸傳遞給遠端與近端的裝置，秋 虽运端的裝置接收鱗脈訊號時，該時脈訊號已經遭受嚴重 ς 遲（propagation delay)所影響。 辱1 於下述說明中，1C之時脈輪入端戶斤於Λ AA 士 / 參考_REF—ακ，而最遠端的裴置所收輸入時脈或 FEED—CLK。參考時脈與回授義時脈 傳遞，並進-步地降低整體系統的運作速度。舉例來 茶考時脈所提供之時序來輸入至一 IC，而於 ’貝枓係依據 之時序由1C輸出。 U貝_依據回授時脈所提供 疋1C運細示準（st她rd)或額定（rated)操作環境，溫度與驅動電 1234930 麗而言，上述延遲並不會有顯著 而改變，例如：周遭環境的溫度變化Γ封裝溫度延=象也會因外部因素 广f準參考時龍F-M細受時脈FEE!) C:二字J有:應電塵’因此藉 因素對參考時《EF_CLK戶斤造成的傳遞延遲。延遲助於補償這些外部 loop)即為-種常用來校準訊號之時序的電路。，郷（Delay iock 延遲鎖相迴路接收該參考時脈ref Μ—〇UT’其相位係領先或延遲參考時脈勝生:輪出時服訊號 見’於下述說明中，所有延遲鎖相迴生了方便說明起 脈贬Μ所產生的，而不管該訊號實際上奴考^白被視為延遲參考時 前或是延遲。-延遲鎖相迴路使用 門^守脈《相位關係為提 其中該默_近似於以傳遞延遲所^遲輸^脈訊舰肅’ 的時間。因此，延遲鎖相迴路^之參考時脈所需 然爾即使用該參考時脈13 it °/私脈輸入腳位的裝置單元想當 3遲鎖相迴路所提供之輸_訊細―瞻，如 要時脈Λ號的裝置單元皆對準同一時序。 而 調士係藉由比較參考時脈REF—CLK與一回授時脈似 中Θ~ a卿―αΚ的延遲日销來產生輸㈣脈喊GLK-〇UT，其 係由二=if係為輸出時脈MJ)UT的延遲訊號。回授時脈FB-CLK 例來‘=士電路控制’而該回授延遲電路係模擬IC中之傳遞延遲，舉 二二、，1 兄之Ic的傳遞延遲時間相同或成正比，因此，當外部因素會對 、1延遲產生影響時，其亦會影響回授延遲電路所施加親遲時間。 原則上，日樣峨CLK—ουτ係為參考時脈ref—clk的延遲訊號，而時脈 rtCLK—爾所對應的延遲量係依據一延遲線加㈣⑽）之 1234930 延遲電路（forward delay circuit)所決定，例如一預定數目的緩衝器 (buffer)或反向器（inverter)以串聯方式前後連接，該延遲線之長度 係由參考時脈REF_CLK與回授時脈FB_CLK之比較結果所決定，且調整時脈 為虎CLK—0l|T之延遲罝以於時脈樹（clock tree)之末端驅使時脈訊號 CLK—0UT對背苓考時脈ref一CLK。因此，在一預定範圍的操作環境與參數下， ，於外部因素所造成的傳遞延遲變化並被加簡償，且時脈訊號之間 序亦會被校準。 、於設計延遲鎖相迴路時，需要在互相衝突的設計目標中取得協調。習知 鎖相迴路的第―设计目標係為提供—最大的^遲時間，使幾乎等於來 :脈REF—CLK的最長週期（亦即最低的操作頻率），以確保於最壞情形下 ^又正可運作無誤；第二設計目標係於鮮時脈職IK—時提供最高 的六Ιί度=即微小的時間增量（time in⑽ent)，W提升校準時脈訊號 路;^二’便可進一步地提升IC _算速度。為了在同一延遲鎖相迴 " 迷:設計目標’需要於一延遲線中設置大量的延遲級（delay s age ’而大量的延遲級便需要許多控制線路以及複雜的控制機制。 因=，習知技術所需的是—具備高解析度與少量㈣線路的延遲鎖 調敕顯,Γ哄遲鎖相迴路所需要的是少量的可程式位元，且具備-可 。正、、凋囪（sensing window)以快速地鎖定時脈相位。 【發明内容】 題 口此本發明之主要目的在於提供一多級時脈產生器，以解決上述問 含有專聰圍’細露—廳謝脈產生器，其包 訊號與延遲控制母—延遲單71依據前級延遲單元傳來的延遲時脈 汛唬產生一延遲訊號給後級延遲單元，其中第一級延遲單 10 1234930 一 “末接收外σ卩日守脈訊5虎，而每下一級延遲單元之延遲量都之小於目前 之遲單元之延遲量；一相位偵測器，用來依據該外部時脈訊號與一回授時 ^號產生鎖疋控制訊號；以及一控制單元，用來依據該鎖定控制訊號 產生該延遲控制訊號以程式化該延遲單元。 本發明乡級時脈產生!1係_於乡重鮮之制裝置，錢由使用較少 的控制位7L與自我校正程序，以克服各種環境變化的影響，例如製程偏差、 環境溫度與電壓偏移。 【實施方式】 叫芩閱圖一，其係為一多級時脈產生器100的示意圖。本發明多級時 氐產生时100包含有一由複數個延遲單元（deiay ceu) 1〇1、1〇2、103、 4所、=成的延遲線（制砂Hne)，一相位摘測器（咖％化如咖）i〇6， /工制單元1〇7，與一時脈配置網路（(：1〇(：^(^3计化此丨如此切〇成）1〇5。 概個延遲單元1(U、1G2、⑽、係在初始化之程序中進行規割而具有 =定解析度。第-級延遲單元m係用來接收—外部時脈訊號，然後輸 延遲況唬，而後續的延遲單元皆重複執行此一運作。每一延遲單元包 合有稷數個延遲量（delay咖），且每下—級延遲單元所 越來越小。 处里曰 請參閱圖二，-延遲線可細分為多搬落，用以減少延遲單元所需之控 的數量，該延遲線係依據解析度分割為複數個 L、中弟-級延遲單元1()1係、負責最大的延遲解析度咖， 整相位的變化，其最小的總延遲量必須大於—最大延遲目標量；缺後，第 可利用較小之延遲解析度203來調整相位；第^級延遲 =70 1 03 ’制方法與第二級延遲單元⑽相同，但是其延遲量更小。此 卜，延遲ϊ必須小於系統本身具有的時基誤差（jitter)， 的控制位元皆來自同一控制單元1〇7。 11 1234930 舍^劃^延遲量的演算法敘述如下。首先，確定控制位元的總數，本發明之 =苑例選擇16來作為控制位元的總數，下列算式係決定第一級延 處理範圍： (控制位兀總數）—1 .(最大延遲量）/(第-級延遲單元中每-延遲量 的大小）1234930 D. Description of the invention [Technical field to which the invention belongs] The present invention provides a clock generator by a finger-delayed phase-locked loop. A multi-level delay using a quasi-sunday pulse phase [prior art] Clock signals are currently applied to almost all integrated circuits, which are used to support the "", device one), which will be the positive edge of the clock signal ) To change its state; in contrast, large IC / negative,, 彖 (fallmg other K: need to be adjusted clockwise), which contains mechanical logic array or _ d / male 乂 thousands of independent circuits or devices .Private & two o'clock view system, input by clock feet, and then-one by one-distribution to complex = and 2 this = pulse signal ship clock pulse listening input, money gradually passed to the far end and the near end Although the device at the transport terminal receives the scale signal, the clock signal has been affected by a severe delay. In the following description, the chakras at the end of 1C weigh Λ AA. / Reference _REF_ακ, and the farthest Pei Zhi received input clock or FEED_CLK. Reference clock and feedback meaning clock pass, and further reduce the overall system operation speed. For example, come to tea The timing provided by the test clock is input to an IC, and the timing based on 'Bei' is based on 1C output. U Bay_According to the feedback clock provided by 运 1C operation standard (std) or rated operating environment, temperature and drive power 1234930 Li, the above delay will not change significantly, such as: the surrounding environment The temperature change of the package temperature delay = the image will also be wide due to external factors. The reference FM will receive the clock FEE!) C: The two characters J have: should be dusty. (Delay helps to compensate for these external loops) is a circuit commonly used to calibrate the timing of the signal. 郷 (Delay iock delay phase-locked loop receives the reference clock ref Μ—〇UT 'whose phase is leading or Delayed reference clock wins: See the signal in the rotation. 'In the following description, all delayed phase-reversion is convenient to explain the origin of the pulse and degenerate, regardless of whether the signal is actually a slave. Reference time or delay.-Delay phase-locked loop uses gate ^ guard pulse "Phase relationship refers to the time where the default _ is approximated by the time delay of the transmission delay ^ pulse signal 肃 '. Therefore, the delay phase-locked loop The reference clock is used as long as the reference is used. The device unit of the pulse 13 it ° / private pulse input pin wants to be the input provided by the 3-later phase-locked loop. If you want the device unit of the clock Λ to be aligned with the same timing. By comparing the reference clock REF_CLK with a feedback clock, the delayed day pin Θ ~ aqing-αK is used to generate the input pulse called GLK-〇UT, which is composed of two = if systems as the output clock MJ) UT The feedback clock FB-CLK is, for example, '= Shih circuit control', and the feedback delay circuit is a transfer delay in an analog IC. For example, the transfer delay time of Ic is the same or proportional. Therefore, when an external factor affects the delay, it also affects the delay time imposed by the feedback delay circuit. In principle, the Japanese sample clock CLK_ουτ is the delay signal with reference to the clock ref_clk, and the delay amount corresponding to the clock rtCLK_ is based on the 1234930 delay circuit (forward delay circuit) Determined, for example, a predetermined number of buffers or inverters are connected back and forth in series. The length of the delay line is determined by the comparison result between the reference clock REF_CLK and the feedback clock FB_CLK, and when adjusting The pulse is the delay of the tiger CLK-0l | T. The end of the clock tree (clock tree) drives the clock signal CLK-0UT to refract the clock ref-CLK. Therefore, under a predetermined range of operating environment and parameters, the change in the transmission delay caused by external factors is simplified and compensated, and the order of the clock signals is also calibrated. When designing a delayed phase-locked loop, coordination needs to be achieved in conflicting design goals. The first-design goal of the conventional phase-locked loop is to provide-the maximum delay time, which is almost equal to: the longest period of the pulse REF-CLK (that is, the lowest operating frequency), to ensure that the worst-case scenario is just right. The operation is correct; the second design goal is to provide the highest six Ιί degrees = fresh time pulse IK = hour, which is a small time increment (time inWent), W to improve the calibration clock signal path; ^ two 'can further improve IC _ calculation speed. In order to return to the same delay phase, the mystery: the design goal 'needs to set a large number of delay levels (delay s age) in a delay line, and a large number of delay levels requires many control lines and complex control mechanisms. Because =, Xi What is needed for the known technology is to have a high-resolution and a small amount of delay-locked modulation of the line. What Γ requires to delay the phase-locked loop is a small amount of programmable bits, and it has-can be. [sensing window] to quickly lock the clock phase. [Summary of the Invention] The main purpose of the present invention is to provide a multi-stage clock generator to solve the above problem. , Its packet signal and delay control mother-delay unit 71 generates a delay signal to the latter unit according to the delay clock from the previous unit delay unit, of which the first unit delay unit 10 1234930 is a "last received external σ 卩" Daily guard pulse 5 tiger, and the delay of each delay unit is less than the delay of the current delay unit; a phase detector is used to generate a lock based on the external clock signal and a feedback time ^ control And a control unit for generating the delay control signal based on the lock control signal to program the delay unit. The township clock of the present invention is generated! 1 is a device made by Yuxiang Zhongxian, which uses less money. Control bit 7L and self-calibration program to overcome the effects of various environmental changes, such as process deviation, ambient temperature and voltage offset. [Embodiment] It is called the first figure, which is a multi-stage clock generator 100 Schematic diagram of the present invention. The generation of the multi-stage time chirp 100 includes a delay line (sand making Hne) composed of a plurality of delay cells (deiay ceu) 101, 102, 103, 4 and a phase extraction test. Controller (such as coffee) i06, / industrial unit 1007, and a clock configuration network ((: 10 (: ^ (^ 3 counts this so cut into 0)) 105. A delay unit 1 (U, 1G2, ⑽, is defined in the initialization procedure and has a constant resolution. The first-order delay unit m is used to receive an external clock signal, and then input the delay condition. Subsequent delay units repeat this operation. Each delay unit contains several delays. (Delay coffee), and each lower-level delay unit is getting smaller and smaller. Please refer to Figure II,-the delay line can be subdivided into multiple removals to reduce the number of controls required by the delay unit, the delay The line system is divided into multiple L, middle-level delay units 1 () 1 based on the resolution, and is responsible for the maximum delay resolution. The change of the entire phase must have a minimum total delay amount greater than the maximum delay target amount. After that, the second phase can be adjusted with a smaller delay resolution 203; the second phase delay = 70 1 03 'is the same as the second phase delay unit 延迟, but its delay is smaller. Therefore, the delay ϊ must be The control bits smaller than the time base error (jitter) of the system are all from the same control unit 107. 11 1234930 The algorithm for rounding off the delay amount is described below. First, determine the total number of control bits. In the present invention, 16 is selected as the total number of control bits. The following formula determines the first-level extension processing range: (total number of control bits)-1. (maximum delay amount) / (The magnitude of each-delay amount in the -stage delay unit)
於第一級延遲單元來說，通常需要少數的延遲量便可達到所要的延遲 ，払里。為了確保進入鎖定狀況（移動目標時脈訊號進入鎖定範圍），第二 級延遲單凡的最小總延遲量需為第一級延遲單元之最大延遲量的1.5倍， 以處理較慢的她罐。假定第—級延遲單元的最大延遲量係為△泡， 故第=延遲單元的最小總延遲量係表示為Sy2nd=i 5x(Axist)，且第二級 延遲，元之每一延遲量係為（15X(Axlst))/16。同理可推，第三級延遲單 :的最小總延遲量Ey3rd係為第二級延遲單元之最大延遲量△χ2η(^〇ι·5 倍（2y3rd=l. 5XAx2nd)，此外，劃分其他級延遲單元之延遲量的規則都 與上述延遲單元相同。 明參閱圖二，圖二係為設定延遲量與校正延遲線的操作流程圖。當時脈 =置（clock distribution)之設計完成後，擷取出一外部時脈與一回授 時脈之間的時脈偏移（skew)，所以，便可得知延遲資訊，並進一步地控制鲁 忒延遲線。於時脈配置設計完成後，由於會嚴重影響延遲單元之操作正確 性的環境變數，諸如製程、供應電壓與溫度等因素仍存在，所以^述操作 便已完成校正延遲線的運作。多相時脈產生器在啟動後即進入一初始化設 疋。於步驟301中，一重置訊號（reset signal)會傳遞至一控制單元中 的延遲計數器（delay counter)，用以重置延遲線中第一級延遲單元的設 定值。於步驟302中，延遲計數器會送出一栓鎖訊號（latch signal)至 该第一級延遲單元，用以驅動該第一級延遲單元栓鎖其預設延遲量。於步 驟303中，-第-延遲單元可程式通道被選取，所以該第一級延遲單元便 輸出一延遲時脈訊號。於步驟304中，依據該第一級延遲單元的延遲量來 12 1234930 又疋相位感測_ (phase detecting winci〇w)。步驟305會執行一相位偵 =勺㈣。於步驟識巾，延遲量會被更新，SUb流程便可繼續處理於下 :級的延遲單元。步驟3〇7會判斷該第一級延遲單元是否成功鎖定該外部 4脈« ’若鎖定不成功，則朗步驟·，直到相對應之延遲量可鎖定該 外部時脈訊號為止。 ^ 、、及延遲單元板正完畢後，第二級延遲單元與後續延遲單元會被逐 ;撕又步& 308鎖定第-級延遲單元的延遲量。於步驟3〇9巾，一鎖定 =虎會傳遞至該延遲計數H ’財置該延遲計健賴第二級延遲單元的 二正運作。於步驟310中，—第二延遲單元可程式通道便會被選取，且該 =一=遲單元便輸出—延辦脈訊號。步驟3ιι係依據第二級延遲單元 步驟312執行一相位偵測的操作。步驟313 ^ -延】f里流程可繼續處理下一級延遲單元。步驟314會確定該 tH7! 貞定該外部時脈訊號，若敝不成功，則回到步驟 行，直到卜部日她_止。地_反覆進 :遲為止。所以，步驟315會判斷是否所有 日=5: 1靖細16㈣出—日_定訊號來 d已凡灿脈鎖疋#作；否則便會回到步驟期。此 ===線’由上述外部因素所造成的延遲偏移皆可由== 私序予以肩除來亚且增加相位鎖定的正確性。 圖。蝴^刺_示意 包含有複數個延遲單元衡、備、延=，其中該第一延遲線 ^ ^ 404 ^ 403 〇 411 元401、403、405 ’·而另一開關412約二（遲線中的母延遲早 =:二_ 單元二 額大感測窗的 ^强至6亥第一延遲線與延遲偏移單元 13 1234930 407 ’以及一第二相位偵柯器 侧。相位偵測器侧、，、甩連接至該第二延遲線與延遲偏移單元 (叫—_)，用㈣懒=有^個輸人端與—輪出端的正反器 態。 、貞暮_叫脈訊號鑛於超前、鎖定或是落後的狀 相位偵測器4〇9係接收兩時脈 " 值_對應同-邏輯值（則RBP =f：；數值拙。若數㈣與數 考時脈訊號。第-、第-延㈣）㈣疋相㈣脈訊號超前該參 相同的時脈網路鱼資it數量的可程式延遲單元，且對應 一延遲線之時_=：：二：：級延遲單元的鎖錢作時，該第 測窗，其係用於鎖定時:二^=^貧料網路會經由程式化來產生-感 ί〇 );相對地’當延遲偏移單元408施加，多 '罗Γ。41Π的終1!叉時脈訊號^領先原始的外部時脈訊號PC時，則相位偵 測"的輸出為1⑽=1)，此日槐為〇且RB為i即表示鎖」η 態而言，延遲的回授時脈訊號PD向左移_ _ 1; = ^遲的回授時脈《PD向右移而使得RB為0。在特 殊=下，洛後之時脈訊號的相位無法對準❹沒的左緣，献領先之時 位無法對準感測窗的右緣，此時對該可程式感測窗來說，數值 匕錢1 (領先《)或者均會等於G (落後狀態）。若利用現行 的感測固仍然無法達到鎖定狀態，則延遲偏移單元術、便會提供更多 的偏移量來延伸感測㈣寬度使其駭較易相。__窗變寬，時脈 訊號之相位便能輕易地落入感測窗的範圍中，如此一來即可完成鎖定的動 作。因域憾-可喊賴單元的解析度，所崎感測窗的寬度必須視 情形改變以確保鎖定的效率，然而’如果感測窗大於可程式延遲單元之延 遲量’則鎖定狀態會發生在感測窗之外（亦即，需要超過一個控制位元）， 14 1234930 一匕後、’只的延遲單元將然法鎖定；相對地，如果感測窗小於可程式延遲 早元之延遲量，則無法逹到鎖定狀態。 明茶閱圖五’圖五係為圖一所示之控制單元1〇7的示意圖。控制單元 使用較> 控制位兀以節省記憶體用量，控制單元谢包含有一個延 遲計數器500，其係電連接_位_器1〇6以減一鎖定控制訊號（1〇冰 :1〇1 Slgnal) ’並且輸出複數個延遲控制峨（delayc〇ntr〇1 signal) (2-! MUX) 520.521 ^ 522 ^ 524 ^ 20 ^ 521 ^ 22: 524係分別電連接至複數個栓鎖器51〇、5ii、5i2、5i4，其中每一多 係、私連接至-栓鎖器，並形成由延遲計數器關到每—延遲單元之可 的分支，其中—第—分支係經由多工器520與栓鎖器51G而自延 電連接至—第—級延遲單元的可程式通道5(31。多工器520係 认訊號中進行選擇：—輸入訊號對應一預設值（其值為G)，以及 ㈣一:訊號為對應第—級延遲單元的第—單元選蘀訊號，然後，多工器 ㈣1出—選取訊號至栓鎖器51G。當栓鎖器510從多工器52G收到該選取 2日，，其會栓鎖傳遞至第—輯單元可程式通道峰式化第—級延遲單 遲量數值’並且送出:第一單元鎖定訊號（具有第一鎖定值）給位 ;梢—^支之下一級延遲單元的多工器521，亦即由栓鎖器' 510輸出的第 係用來作為多工器521的_輸入值。此時，下一級延遲單元的内 =尚維持在最低位元，當第—級延遲單元確定完成鎖定時，相關 整對應第二延遲單元可程式通道5G2的感測窗大小。所有控 比？級接—級地重複使用，直騎有延遲單元之相對應控制位元 二本發明時脈產生器所具有的可程式控制特性允許只使用一延遲 彳數為的控制電路，如此可大幅降低電路複雜度。 以上所述僅為本發明之較佳 所做之均等變化與修飾，皆應屬 實施例，凡本發明申請專利範圍 本發明專利之涵蓋範圍。 15 1234930 【圖式簡單說明】 圖式之簡單說明 圖一係為本發明多級時脈產生器之一實施例的示意圖。 圖:係為本發明之實施例中不同延遲量的示意圖。 圖二係為本發明校正程序之一實施例的示意圖。 圖四係為本發明她_器之—實施例的示意圖。 圖五係為圖-所示之控制單元的放大示意圖。 圖式之符號說明 · ~-—- ----—— 延遲單元 ~" 10卜 102、103、104、4(Π、402、403、404、405、 406、407、408 配置網路 105 貞測器 ——一- 106 ^\β 107 ϋ里，級 201、203、205、207 #反器 409 、 410 開關 ~~-— 412、411 多工器 520、521、522、524 延遲計數器 ——-~——— 500 可程式通道 -——— 5(Η、502、503、504 栓鎖器 510 、 511 、 512 、 514 16For the first-level delay unit, a small amount of delay is usually required to achieve the desired delay. In order to ensure a locked state (moving target clock signal enters the locked range), the minimum total delay amount of the second-level delay unit needs to be 1.5 times the maximum delay amount of the first-level delay unit to process the slower her tank. Assume that the maximum delay amount of the first-order delay unit is △ bubble, so the minimum total delay amount of the = -th delay unit is expressed as Sy2nd = i 5x (Axist), and the second-stage delay, each delay amount of the element is (15X (Axlst)) / 16. Similarly, it can be inferred that the minimum total delay amount Ey3rd of the third stage delay sheet is the maximum delay amount of the second stage delay unit △ χ2η (^ 〇ι · 5 times (2y3rd = 1.5xAx2nd), and in addition, it is divided into other stages The rules of the delay amount of the delay unit are the same as those of the above-mentioned delay unit. Refer to Figure 2 for details. Figure 2 is a flowchart of the operation of setting the delay amount and correcting the delay line. After the design of clock distribution is completed, it is retrieved. The clock skew between an external clock and a feedback clock, so you can know the delay information and further control the Luan delay line. After the clock configuration design is completed, it will seriously affect The environmental variables of the correctness of the operation of the delay unit, such as process, supply voltage and temperature, still exist, so the operation has been completed to correct the delay line. The multi-phase clock generator enters an initial setting after startup. In step 301, a reset signal is passed to a delay counter in a control unit to reset the setting value of the first-level delay unit in the delay line. In step 302, the delay counter sends a latch signal to the first-level delay unit to drive the first-level delay unit to latch its preset delay amount. In step 303, the -th-delay The programmable channel of the unit is selected, so the first-stage delay unit outputs a delayed clock signal. In step 304, 12 1234930 and phase detection win (_phase detecting winci) are performed according to the delay amount of the first-stage delay unit. 〇w). Step 305 will perform a phase detection = spoon. At the step identification, the delay amount will be updated, and the SUb process can continue to process at the lower level delay unit. Step 307 will determine the first level Whether the delay unit successfully locks the external 4-pulse «'If the lock is unsuccessful, then step · until the corresponding delay amount can lock the external clock signal. ^, And after the delay unit board is completed, the second stage The delay unit and the subsequent delay units will be locked one by one; 308 Step-by-step delay unit locks the delay amount. At step 309, a lock = Tiger will pass to the delay count H 'to store the delay meter. Jian Lai Second Order Delay Order The second element of the element is operating. In step 310, the programmable channel of the second delay unit will be selected, and the = a = the delayed unit will output the delayed pulse signal. Step 3m is based on the second delay unit step 312. Perform a phase detection operation. Step 313 ^-delay] The process in f can continue to process the next delay unit. Step 314 will determine the tH7! To determine the external clock signal. If it is not successful, return to step Until Bu Bu Ri she_stops. Earth_repeated into: late. So, step 315 will determine whether all the days = 5: 1 Jing Xi 16 ——day _ fixed signal to d has Fan Can pulse lock 疋 # work; otherwise You will return to the step period. The delay offset caused by the above external factors of the === line can be removed by the == private sequence and the correctness of the phase lock can be increased. Illustration. The butterfly _ indicates that it contains a plurality of delay units, including balance, backup, and delay, where the first delay line ^ 404 ^ 403 403 411 yuan 401, 403, 405 ', and another switch 412 is about two (in the late line The mother delay is early =: 2 _ Units with two large sensing windows are as strong as 60 Hz, the first delay line and the delay offset unit 13 1234930 407 ′ and a second phase detector side. The phase detector side, ,, and the flip-flop is connected to the second delay line and the delay offset unit (called —_), use lazy = a flip-flop state with ^ input end and — round out end. Leading, locked, or trailing phase detectors 409 receive two clocks " value_corresponds to the same-logical value (then RBP = f :; the value is awkward. If the number of clocks and the number of clock signals are counted. -、 第-延 ㈣) The phase signal is ahead of the programmable delay unit of the same clock network fish source IT number, and corresponds to the time of a delay line. _ = :: 2 :: Level delay unit When the money is locked, the first measurement window is used for locking: two ^ = ^ lean materials will be generated through programming-sense ί)); relatively, when the delay offset unit 408 Plus, and more 'Lo Γ. The end of 41Π! When the leading clock signal is ahead of the original external clock signal PC, the output of phase detection is 1⑽ = 1). On this day, huai is 0 and RB is i. In other words, the delayed feedback clock signal PD is shifted to the left by _ _ 1; = ^ The late feedback clock PD is shifted to the right so that RB is 0. Under special =, the phase of the clock signal of Luohou cannot be aligned with the left edge of the oblivion, and the leading position cannot be aligned with the right edge of the sensing window. At this time, for the programmable sensing window, the value is Dagger money 1 (leading ") may be equal to G (backward). If the current state of the sensor is still unable to reach the locked state, the delayed offset unit technique will provide more offsets to extend the width of the sensor to make it easier to look at. The __ window becomes wider, and the phase of the clock signal can easily fall into the range of the sensing window, so that the locking operation can be completed. Due to the domain resolution-the resolution of the callable unit, the width of the sensing window must be changed to ensure the locking efficiency. However, if the sensing window is greater than the delay of the programmable delay unit, the locked state will Outside the sensing window (that is, more than one control bit is required), 14 1234930 after a dagger, only the delay unit will be locked; in contrast, if the sensing window is less than the delay amount of the programmable delay early element, You cannot reach the locked state. Mingcha Reading Figure 5 'Figure 5 is a schematic diagram of the control unit 107 shown in Figure 1. The control unit uses more control bits to save memory usage. The control unit contains a delay counter 500, which is electrically connected to the bit 10 to reduce the lock control signal (10 ice: 10). Slgnal) 'and output a plurality of delay control signal (2-! MUX) 520.521 ^ 522 ^ 524 ^ 20 ^ 521 ^ 22: 524 is electrically connected to a plurality of latches 51, 5ii, 5i2, 5i4, each of which is multi-line and privately connected to the latch, and forms a branch that can be turned off by the delay counter to each delay unit, wherein the first branch is connected to the latch via the multiplexer 520 The 51G device is connected to the programmable channel 5 of the first-stage delay unit (31. The multiplexer 520 is a selection signal:-the input signal corresponds to a preset value (the value is G), and ㈣ 1: The signal is the first unit selection signal corresponding to the first stage delay unit, and then, the multiplexer 1 outputs-selects the signal to the latch 51G. When the latch 510 receives the selection from the multiplexer 52G for 2 days , Which will be latched and passed to the first series of units. Programmable channel peaking of the first delay single delay. Value 'and send: the first unit lock signal (having the first lock value) to the bit; the multiplexer 521 of the first-level delay unit below the ^ branch, that is, the system output by the latch 510 is used as The _ input value of the multiplexer 521. At this time, the internal delay unit of the next stage is still at the lowest bit. When the first stage delay unit determines that the lock is completed, the correlation corresponds to the sense of the programmable channel 5G2 of the second delay unit. The size of the window. All control ratios? Cascaded-repetitively used in steps, the corresponding control bit of the delay unit is used directly. The programmable control characteristic of the clock generator of the present invention allows only one delay to be used. The control circuit can greatly reduce the complexity of the circuit. The above description is only the equivalent changes and modifications of the present invention, which should be included in the embodiment. The scope of the present invention is covered by the patent of this invention. 15 1234930 [Brief description of the diagram] Brief description of the diagram Figure 1 is a schematic diagram of an embodiment of a multi-stage clock generator according to the present invention. Figure: is a schematic diagram of different delay amounts in the embodiment of the present invention. Figure 2 It is a schematic diagram of one embodiment of the calibration procedure of the present invention. Fig. 4 is a schematic diagram of an embodiment of the device of the present invention. Fig. 5 is an enlarged schematic diagram of a control unit shown in Fig .. ~ ---- -------- Delay Unit ~ " 10, 102, 103, 104, 4 (Π, 402, 403, 404, 405, 406, 407, 408) Configure the network 105. -106 ^ \ β 107 ϋ 里, stages 201, 203, 205, 207 #inverters 409, 410 switches ~~ -— 412, 411 multiplexers 520, 521, 522, 524 delay counters --- ~ --- 500 Programmable channels --- 5 (Η, 502, 503, 504 latches 510, 511, 512, 514 16