1233636 玖、發明說明： 【發明所屬之技術領域】 本發明是關於一種致電與致冷結構及製造方法，特別是關於電子穿遂 式致電與致冷結構及製造方法。 【先前技術】 熱電交換機制之原理係將P型與N型熱電材料製成的線之端點焊接在 一起以形成連續迴路，當線之端點置於不同的溫度時，迴路會形成微小之 電壓差，稱之為Seedbeck效應。相反的，若對於此連續迴路提供電源時， 則會使得熱在一端點被吸收而在另一端點生成，即Peltier效應。1233636 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a telephone and cooling structure and manufacturing method, and more particularly to an electronic tunneling and cooling structure and manufacturing method. [Previous technology] The principle of the thermoelectric exchange mechanism is to weld the ends of wires made of P-type and N-type thermoelectric materials together to form a continuous loop. When the ends of the wire are placed at different temperatures, the loop will form a tiny loop. The voltage difference is called the Seedbeck effect. Conversely, if power is supplied to this continuous loop, heat will be absorbed at one end and generated at the other end, the Peltier effect.
Huffman將上述原理加入電子穿遂效應，提出therm〇-tunnel概念，進 而發展出電子穿遂紅致電姐冷晶H藉由穿遂電子祕輸能量。晶 片組包含發射端晶>{與接收端晶片，兩者之間需間隔極薄絕緣層，發射端 (熱端)之電子係吸收熱能脫離晶格束缚能，產生電子穿遂效應傳輸至接收 端（冷端），藉此傳輸趨勢即可產生電流。相反地，如於晶片組外加電動勢 驅動電子麟發射端，峨由絕緣層穿遂至接收端，啊帶走熱量，發揮 散熱功能。其巾之絕緣衫真空之健傳特性秘兩晶狀間設計真 空間距作為絕緣層，而晶格束戦係指發射端晶片表面材料之功函數，亦 即將電子由費来此階激發至真空所需的能量。為提升晶片組的致冷與致 電效果在原理上可藉由提升電子穿遂能量、縮短兩晶片間距與降低發射 端晶片表面材料之功函數等方式，使電子較祕脫束缚以發生穿遂效應。 但是在實際製程上要如何使兩晶片維持相#微小的間距非常困難，此外， 兩曰曰片之門距如㈣（程度，雖可增加穿遂錢，但是其散熱效率亦隨 5 093TW5047 06-930014 1233636 之降低而觸致冷的效果。目此如何使兩晶片轉適當的真㈣距以提供 電子穿遂距離，並以製程控制晶片表面平整度，為此技術之疏頸所在。 目前已商業化之電子穿遂式致電舆致冷之結構為英國β_^ khniW Umited公司所開發之致冷晶片（c〇〇i 與致電晶片⑼縦 ’如美國第6_〇號專利所述，其製程係以單晶材作為發射 端於基材上儿積厚度約-百奈米(nan〇meter，蘭)金屬薄層，再於薄金屬 層上沉積厚度約5微米之銅金屬層作為種子層，接著，以電化學方式於種 子層上成長麵相作為触端，伽機械方式分離此堆疊 層，並以液態氮去除基材表面之金屬薄層。即可得具有互補之幾何表面的 發射端與接收端，藉其互補表面逼近至電子穿遂雜區域的可工作距離， 降低晶片表面平整度的問題。此外，配合上述製程，B槪仏Huffman added the above principle to the electron tunneling effect and proposed the concept of thermo-tunnel, and developed the electron tunneling red to call the sister Leng Jing H to transfer energy through the tunneling electron. The chipset contains transmitting end crystals and {and the receiving end wafers, with a very thin insulating layer between them. The electronic system at the transmitting end (hot end) absorbs the thermal energy to escape the lattice binding energy, and generates an electron tunneling effect to transmit to the receiver. End (cold end), through which the transmission trend can generate current. Conversely, if an electromotive force is applied to the chipset to drive the transmitting end of the electron, the insulation layer passes through the insulating layer to the receiving end, which takes away the heat and exerts the heat dissipation function. The transmission characteristics of the vacuum of the insulating shirt of the towel are designed as a vacuum gap between the two crystals, and the lattice beam refers to the work function of the material on the emitting surface of the wafer, that is, the electrons are excited from Fei to this stage to the vacuum. Needed energy. In order to improve the cooling and calling effect of the chipset, in principle, the electrons can be unbound and the tunneling effect can be achieved by increasing the electron tunneling energy, shortening the distance between the two wafers, and reducing the work function of the surface material of the chip at the emitter. . However, it is very difficult to maintain a tiny distance between the two chips in the actual manufacturing process. In addition, the gate distance between the two chips is as large as possible (the degree can increase the pass through money, but its heat dissipation efficiency also varies with 5 093TW5047 06- 930014 1233636 reduces the effect of cooling. So how to make the two wafers turn to the proper true distance to provide the electronic tunneling distance and control the flatness of the wafer surface by the process. The structure of the electronic electronic call-to-call cooling is a refrigerating chip (c〇i and calling chip) developed by the British company β_ ^ khniW Umited, as described in the US patent No. 6_0, and its manufacturing process is A single crystal material is used as the emitting end to deposit a thin layer of metal of about -nanometer (blue) on the substrate, and then a copper metal layer of about 5 microns in thickness is deposited on the thin metal layer as a seed layer. The surface layer is grown electrochemically on the seed layer as a contact, the stack layer is separated mechanically, and the thin metal layer on the surface of the substrate is removed by liquid nitrogen. The transmitting end and receiving end with complementary geometric surfaces can be obtained. End Approximation to the complementary surface electrons through the working distance can then hybrid region, reducing the problem of the surface flatness of the wafer. In addition, with the above-described process, B Coming to Fo
Lmted紐展出真g間距定位技術’固紐射端，利崎插式穿遂顯微鏡 之探針技術，以壓電定位器移動接收端，以使發射端與接收端的真空間隙 可隨著操作溫度與外界震動的雜訊而調整。 另-種電子穿遂式致電與致冷結構為結合場發射原理，於發射端製作 尖端微結構，可使得真空間距不需控制至奈米尺度，藉由尖端結構可增強 電子脫離魏端的晶格轉能，使真^間距僅需大約維持在微米尺度。此 尖端結構可利用鑽石沉積、成長奈米碳管或奈米線、濕钱刻或乾侧等製 程來完成，應用相同原理，更可將尖端結構結合懸臂樑作為發射端，藉由 懸臂樑可精確控制尖端至接收端的距離。 因此，無論是何種結構皆亟待開發更具穩定性的製程，特別是商業化 6 093TW5047 06-930014 1233636 石夕晶圓之表面平整度約G.5微米，因此對於發射端與接收端之雜間距影 響甚矩。故當的製程與結構，麵低；表面平整颜要求，並維 持發射端與接收端之奈雜空間距，進而_較麵致«致冷效能。 【發明内容】 有鑑於此，本發明提供一種電子穿遂式致電與致冷結構及製造方法， 係應用轉體㈣财絲製糾具有敎真娜距之電子穿遂式致電與 、構並可藉由其製程的特性改良電子穿遂式致電與致冷結構的接 面，提升致電與致冷的效能。 為達述目的本發明的電子穿遂式致電與致冷結構之製造方法，其 乂驟已3 .百先’提供—基材；形成—黏結層於基材表面；形成第一金屬 層於黏層上，再於第—金屬層表卿成複數做撐絕雜；形成高分子 層於厚金屬層表面並覆蓋支揮絕緣墊與填滿其間隙；減薄高分子層至露出 支標絕緣墊的頂端，使兩者的厚度相# ;形成第二金屬層於高分子層與支 撐絕緣墊上；以熱解方式移除高分子層，使第一金屬層與第二金屬層之間 係間隔支觀緣錢藉其維制距，最後，移除基材與黏結層。 在半導體工業領域，為了對所使用的材料賦與某種特性，常在材料表 面上以各種方法形成具有特殊性質的被覆薄膜。進行薄膜沉積處理時，需 以原子或分子的層次控制材料粒子使其形成薄膜，因此，可以針對所需的 尺寸精4度及14飾成特定材f的薄膜。故本發明應用半導體的製程方法 可製作出㈣輸恤彻樣㈣距，繼其製程的特 性改良電子穿遂式致電與致冷結構的接面，本發明係利用高分子層來作為 093TW5047 06-930014 7 1233636 犧牲層*⑽子層由於本身分子間的空隙，使其具有奈米尺度之結構， 所以第二金屬層轉於高分子树，將會沿著奈米結構成形 ，進而使接面 產生微針大結構’此微針尖結構的局部場效應將增強電子的穿遂能力。 為使對本發明的目的、構造特徵及其功能有進一步的了解，兹配合圖 示詳細說明如下： 【實施方式】 、=舉—實蝴來零本伽之電子穿遂式致致冷結構之製造方 “考第1圖至第8圖’其為本發明實施例之製喊面示意圖。 如第1圖所示，首先，提供i基材⑽，並树基材表面形成二 氧化销_為層1Q1。本發明可藉由熱氧化等方法使雜材的表面形 、氧1^層$疋以化學氣相沉積法或物理氣相沉積法等方法使二氧化 矽層沉積於基材表面。 如第2圖所示，形成第一金屬層no於黏結層101上。第一金屬層110 〜 +氣拍’儿積法、物理氣相沉積法、電鑛或無電鑛法等半導體技術 來完成。 著如第3E圖所不，於第一金屬層11〇表面形成複數個支撐絕緣墊 H ^說月其製造程序，請參考第3A圖至第3E圖，其為以光微影方 : >邑緣塾之製程截面不意圖。如第3A圖所示，於第-金屬層11〇 /成、邑緣層111 ;如第3B圖所示，於絕緣層111上形成光阻層112 ;如 第3C圖戶斤- 一 不’曝光與顯影光阻層112以形成光阻層112醜；如第3D圖 所不猎由光阻層112目案的阻擔來侧絕緣層山以形成支樓絕緣墊 093TW5047 06-930014 8 1233636 m ;最後，如第期所示，去除光阻層112圖案。其支擇絕緣塾⑵之 材質可為奈米尺度二氧化矽或多孔二氧化石夕。 如第4圖所示，旋轉塗佈高分子層113於第—金屬層ιι〇表面以作為 犧牲層，並«支魏輕m並填滿其_。其高分子層ιΐ3具有較低 之熱解溫度以及奈米尺度結構。 如第5圖所示，拋光研磨高分子層113至露出支撑、絕緣塾⑵，使高分 子層113與支撐絕緣墊121具有相同奈米尺度的厚度。 如第6圖所示，於高分子層113與支撑絕緣塾m上形成第二金屬層 120。第二金屬層120可應用化學氣相沉積法、物理氣相沉積法、電鑛或無 電鑛法等半導體技術來完成。由於高分子層113本身分子間的空隙，使其 具有奈米尺度之結構，所以第二金屬層12G沉積於高分子層ιΐ3時，將會 沿著奈米尺度結構成形，進而使接面產生微針尖結構，此微針尖結構的局 部場效應可增強電子的穿遂能力。 如第7圖所*，於真空爐中熱解高分子層113使其揮發，使第一金屬 層no與第二金屬層120之間係間隔支撐絕緣塾121並藉其維持間距。 最後，如第8圖所示，以钱刻方式移除石夕基材1〇〇與黏結層ι〇ι，即形 成電子穿遂式致電無冷結構。因此，本發郷成―電子穿遂式致電與致 冷結構，其包括·· 一第一金屬層no，係為平板狀；-第二金屬層120，係 為平板狀並平行地與該第一金屬層11〇，•及複數個支撐絕緣墊⑵，係分 佈於該第金屬層110與該第二金屬層12〇間，使該第一金屬層m與該 第金屬層120相距在奈米距離内。由於本結構係兩金屬板間距為奈米距 9 093TW5G47 〇6.93〇〇14 ^233636 離内，所以可使得電子穿隧。 另外，更可在作為發射端 三五族之低功函數鑽石薄膜， 容易產生穿遂效應。 而其間距卩柯収撐絕轉隔離即可。 之第-金屬層或第二金屬層表面形成重推雜 以降低發射端之表面晶格束魏，使電子更 藉由本發明之製程可使第一金屬層與第二金屬層維持奈米尺度之間 3並且於巾彻讀絕雜與高分子層隔離兩金屬層避免其產生導 通短路的。本發明可藉由個高分子層作為犧牲層，㈣ 成微物树締卩侧，爾繼咖现彻 $數鑽石薄膜。因此，在具備奈米尺度之發射端與接收端之間隔的情形下， 還了八有用以降低發射端表面晶格束缚能之低功函數鑽石薄膜，以 及微針尖結構’使電子找胃產生穿遂聽，躺大幅提升電子穿遂式致 電與致冷結構之致冷賊電功效。 雖然本發明之較佳實施例揭露如上所述，然其並非用以限定本發明， 任何熟習相關技藝者，在不脫離本發明之精神和範圍内，當可作些許之更 動與潤飾’因此本發明之專利保護範圍須視本說明書所附之申請專利範圍 所界定者為準。 10 093TW5047 06-930014 1233636 【圖式簡單說明】 第1圖至第8圖為本發明實施例之製程截面示意圖；及 第3A圖至第3E圖為以光微影方法製造支撐絕緣墊之製程截面示意圖。 【圖式符號說明】 100 碎基材 101 黏結層 110 第一金屬層 111 絕緣層 112 光阻層 113 高分子層 120 第二金屬層 121 支撐絕緣墊 11 093TW5047 06-930014Lmted New Zealand exhibited the true g-pitch positioning technology, 'Guo Niu', the probe technology of Lizaki's insertion tunneling microscope, and moved the receiving end with a piezoelectric positioner, so that the vacuum gap between the transmitting end and the receiving end could follow the operating temperature Adjust with the noise of external vibration. Another type of electron tunneling and cooling structure is based on the combination of field emission principle, and the cutting-edge microstructure is made at the emitting end, so that the vacuum distance does not need to be controlled to the nanometer scale, and the tip structure can enhance the electrons to escape from the lattice of Wei end. Turn energy, so that the true distance only needs to be maintained on the micrometer scale. This tip structure can be completed using diamond deposition, growing carbon nanotubes or nanowires, wet money engraving or dry side processes. Using the same principle, the tip structure can also be combined with a cantilever beam as the launch end. Precisely control the distance from the tip to the receiving end. Therefore, no matter what kind of structure, there is an urgent need to develop a more stable process, especially for commercialization. 6 093TW5047 06-930014 1233636 The surface flatness of Shi Xi wafer is about G.5 microns, so for the confusion between the transmitting end and the receiving end The spacing effect is very momentous. Therefore, the current manufacturing process and structure have a low surface; the surface must be flat and smooth, and the space between the transmitting end and the receiving end must be maintained, so that the cooling performance is better. [Summary of the Invention] In view of this, the present invention provides an electronic through-type telephone call and cooling structure and manufacturing method, which is applied to an electronic through-type telephone call and communication system with a 敎 true nanometer distance by using a swivel wire. With the characteristics of its process, the interface between the electronic tunneling and the cooling structure is improved, and the performance of the calling and the cooling is improved. In order to achieve the stated purpose, the method for manufacturing the electronic punch-through telephone and the cooling structure of the present invention has been provided in 3.100 steps'-substrate; forming-a bonding layer on the surface of the substrate; forming a first metal layer on the substrate On the layer, the first metal layer and the surface layer are plurally doped; the polymer layer is formed on the surface of the thick metal layer and covers the insulating pad and fills the gap; the polymer layer is thinned to expose the supporting insulating pad. At the top of the two layers, forming a second metal layer on the polymer layer and the supporting insulating pad; removing the polymer layer by pyrolysis, so that the first metal layer and the second metal layer are spaced between each other. The Guanqian borrows its control distance, and finally, removes the substrate and the adhesive layer. In the field of the semiconductor industry, in order to impart certain characteristics to the materials used, a coating film having special properties is often formed on the surface of the material by various methods. When performing a thin film deposition process, it is necessary to control the material particles to form a thin film at the atomic or molecular level. Therefore, a thin film of a specific material f can be formed for a desired size of 4 ° and 14 °. Therefore, the method of applying a semiconductor process of the present invention can produce a complete sample of the gap, and following the characteristics of the process, it improves the interface between the electronic tunneling type and the cooling structure. The present invention uses a polymer layer as the 093TW5047 06- 930014 7 1233636 The sacrificial layer * ⑽ sublayer has a nano-scale structure due to the inter-molecular gaps, so the second metal layer is transferred to the polymer tree, and it will be formed along the nano-structure, which will cause the junction to produce Micro-needle large structure 'The local field effect of this micro-needle structure will enhance the electron tunneling ability. In order to further understand the purpose, structural features and functions of the present invention, detailed descriptions are given in conjunction with the illustrations as follows: [Embodiment], =-Example-manufacturing of electron tunnel cooling structure Fang "Examine Fig. 1 to Fig. 8 ', which are schematic diagrams of the call surface of the embodiment of the present invention. As shown in Fig. 1, firstly, i substrate is provided, and the surface of the substrate is formed with a doping pin. 1Q1. According to the present invention, the surface shape of the miscellaneous material and the oxygen layer can be formed by thermal oxidation and other methods. The silicon dioxide layer can be deposited on the surface of the substrate by methods such as chemical vapor deposition or physical vapor deposition. As shown in FIG. 2, a first metal layer is formed on the bonding layer 101. The first metal layer 110 to + is completed by semiconductor technology such as an airborne method, a physical vapor deposition method, an electric ore method, or an electroless ore method. As shown in FIG. 3E, a plurality of supporting insulating pads H are formed on the surface of the first metal layer 110. For manufacturing processes, please refer to FIGS. 3A to 3E, which are illustrated by photolithography: > The cross section of the process of Yiyuan is not intended. As shown in Fig. 3A, at the -metal layer 11〇 / 成, Yiyuan Layer 111; as shown in FIG. 3B, a photoresist layer 112 is formed on the insulating layer 111; as shown in FIG. 3C-the photoresist layer 112 is exposed and developed to form the photoresist layer 112; as shown in FIG. 3D The photoresist layer 112 is used as a barrier to the side insulation layer to form branch insulation pads. 093TW5047 06-930014 8 1233636 m; Finally, as shown in the issue, the photoresist layer 112 pattern is removed. Its options The material of the insulation can be nano-scale silicon dioxide or porous silica. As shown in Figure 4, the polymer layer 113 is spin-coated on the surface of the first-metal layer ιο as a sacrificial layer, and Wei Qingm and filled it with _. Its polymer layer ιΐ3 has a lower pyrolysis temperature and nano-scale structure. As shown in Figure 5, the polymer layer 113 is polished and polished to expose the support and insulation 塾 ⑵, so that The molecular layer 113 has the same nanometer thickness as the supporting insulating pad 121. As shown in FIG. 6, a second metal layer 120 is formed on the polymer layer 113 and the supporting insulating layer 化学. The second metal layer 120 can be applied with a chemical gas. Phase deposition method, physical vapor deposition method, electric ore or electroless ore, etc. The gap between the molecules of the polymer layer 113 itself has a nanometer-scale structure, so when the second metal layer 12G is deposited on the polymer layer ιΐ3, it will be formed along the nanometer-scale structure, which will cause microneedles on the interface. Structure, the local field effect of this microneedle structure can enhance the electron tunneling ability. As shown in Figure 7 *, the polymer layer 113 is pyrolyzed in a vacuum furnace to volatilize the first metal layer no and the second metal layer. The space between 120 supports the insulation 塾 121 and maintains the distance by using it. Finally, as shown in Figure 8, the Shi Xi substrate 100 and the adhesive layer ι〇ι are removed by means of money engraving to form an electron tunneling type The telephone has no cold structure. Therefore, the present invention has an electronic tunneling and cooling structure, which includes a first metal layer no, which is a flat plate;-a second metal layer 120, which is a flat plate and Parallel to the first metal layer 110, and a plurality of supporting insulating pads 分布, are distributed between the first metal layer 110 and the second metal layer 120, so that the first metal layer m and the second metal layer 120 is within nanometer distance. Because the structure of the two metal plates is within a nanometer distance of 9 093TW5G47 〇6.93〇14 ^ 233636, electron tunneling can be made. In addition, it can be used as the emitting end of the low work function diamond film of the three or five groups, which is easy to produce a tunneling effect. The distance between them can be isolated and isolated. The surface of the first-metal layer or the second metal layer forms a dopant to reduce the surface lattice beam at the emitting end, so that the electrons can maintain the nano-scale of the first metal layer and the second metal layer through the process of the present invention. In between, and thoroughly read the impurity and the polymer layer to isolate the two metal layers to avoid conduction and short circuit. According to the present invention, a polymer layer can be used as a sacrificial layer to form a micro-object tree, and a diamond film can be formed. Therefore, in the case of the gap between the transmitting end and the receiving end on the nanometer scale, eight low-work function diamond films are also used to reduce the lattice binding energy on the surface of the transmitting end, and the microneedle structure 'makes the electrons look through the stomach. Listening, lying down greatly improves the electrical efficiency of the electronic thief and cooling structure. Although the preferred embodiment of the present invention is disclosed as described above, it is not intended to limit the present invention. Any person skilled in the relevant arts can make some changes and retouching without departing from the spirit and scope of the present invention. The patent protection scope of the invention shall be determined by the scope of the patent application scope attached to this specification. 10 093TW5047 06-930014 1233636 [Brief description of the drawings] Figures 1 to 8 are schematic cross-sectional views of the process of the embodiment of the present invention; and Figures 3A to 3E are process cross-sections of the manufacturing of supporting insulating pads by photolithography schematic diagram. [Illustration of Symbols] 100 broken substrate 101 adhesive layer 110 first metal layer 111 insulating layer 112 photoresist layer 113 polymer layer 120 second metal layer 121 supporting insulating pad 11 093TW5047 06-930014