1233085 玖、發明說明： 【發明所屬技街領域】 技術領域 本發明係有關於利用有機電場發光(EL)元件等電容性 5發光兀件之發光面板顯示裝置，且有關於可改善對應於灰 p白值之發光冗度的灰階特性以提高晝質之發光面板顯示事 置。 〜 背景技術 10 利用有機EL元件等電容性發光元件之發光面板顯示裝 置可實現構造簡單且薄型化，又，由於設於像素之元件^ 身會發光’故可如液晶顯示面板，不需要背光，因此，在 成為薄型且低耗電量之顯示面板上是可期待的。 第1圖係習知電容性發光元件之發光面板顯示裝置的 15構造圖。該發光面板顯示裝置係記載於例如日本專利公開 公報特開2000 — 140037號、日本專利公開公報特開平u — 311978號。如圖所示，有機EL由電容組件及與該電容組件 並列之一極體特性組件所構成，一旦將直流發光驅動電壓 施加於元件之陽極(正極)與陰極（負極)之間，則可將電容組 20件充電，又，一旦電極間之施加電壓超過元件固有的發光 臨界值電壓’則電流會流向發光層並發光。 第1圖之發光面板顯示裝置包含發光元件All〜Ann配 置成矩陣狀之發光面板10、用以驅動發光面板之資料線 B1〜Bn之資料驅動電路2〇 ,及用以驅動發光面板之掃描線 12330851233085 发明 Description of the invention: [Technical field to which the invention belongs] TECHNICAL FIELD The present invention relates to a light-emitting panel display device using a capacitive 5 light-emitting element such as an organic electric field light-emitting (EL) element, and relates to an improvement corresponding to gray p The gray-scale characteristics of the whiteness of the light emission redundancy to improve the daylight quality of the light-emitting panel display. ~ Background Art 10 A light-emitting panel display device using a capacitive light-emitting element such as an organic EL element can have a simple structure and a low profile. In addition, since the element provided in the pixel ^ can emit light, it can be used as a liquid crystal display panel and does not require a backlight. Therefore, it is expected to be a thin and low power consumption display panel. FIG. 1 is a structural diagram of a light-emitting panel display device of a conventional capacitive light-emitting element. This light-emitting panel display device is described in, for example, Japanese Patent Laid-Open Publication No. 2000-140037 and Japanese Patent Laid-Open Publication No. Hei 31-1978. As shown in the figure, the organic EL is composed of a capacitor element and a polar body characteristic element in parallel with the capacitor element. Once a DC light-emitting driving voltage is applied between the anode (positive electrode) and the cathode (negative electrode) of the element, the Twenty capacitor units are charged, and once the applied voltage between the electrodes exceeds the element's inherent light emission threshold voltage ', a current will flow to the light emitting layer and emit light. The light-emitting panel display device of FIG. 1 includes light-emitting panels 10 in which light-emitting elements All to Ann are arranged in a matrix, data driving circuits 20 for driving data lines B1 to Bn of the light-emitting panel, and scanning lines for driving the light-emitting panel. 1233085
Cl〜Cn之掃描驅動電路3〇。資料驅動電路2〇具有用以將資 料線B1〜Bn分別驅動為接地或發光驅動電壓Vdl之開關 D1〜Dn。又’掃描驅動電路3〇具有用以將掃描線ci〜Cn分 別驅動為選擇位準之接地或非選擇位準之逆偏壓電壓乂3之 5開關S1〜Sn。根據第1圖所示之驅動電路内的開關狀態，掃 描線C1驅動為接地且為選擇狀態，除此以外之掃描線 C2〜Cn則驅動為逆偏壓電壓Vs且為非選擇狀態，而資料線 B1〜Bn則分別驅動為發光驅動電壓vdl。於該狀態下，資料 線B1〜Bn至發光元件All〜Ain，即，至掃描線(^之通路會 10有發光驅動電流流過，故，與選擇掃描線^相連接之發光 元件All〜Ain會發光。一旦掃描線C1中之發光驅動結束， 則將下一掃描線C2驅動為接地且使其為選擇狀態，除此以 外之掃描線Cl、C3〜Cn則驅動為逆偏壓電壓且為非選擇狀 態，並將發光驅動電壓Vdl施加於資料線B1〜Bn。 15 於各掃描線成為選擇狀態之掃描期間（水平同步期間） 内，發光驅動電壓Vdl施加於各資料線的動作係依照對應於 輸入圖像信號之灰階的時間來控制。即，用以施加控制資 料驅動電路20之發光驅動電壓vdl的控制脈衝具有對應於 圖像#號之灰階的脈衝頻寬，故可使該圖像信號灰階值對 20應於經脈衝頻寬調變之控制脈衝，並在對應於圖像信號灰 階值之時間内，將發光驅動電壓供給至資料線，使發光元 件發光。 第2圖係顯示第1圖之發光面板顯示裝置之資料驅動電 路的控制脈衝與發光波形的例子。於掃描期間（水平同步期 1233085 間）Hsync中，同時開始施加用以將資料驅動電路2〇之驅動 開關D1切換控制為發光驅動電壓vdl之控制脈衝CP1與對 驅動開關D2進行同樣動作之控制脈衝CP2，且在分別對應 於與發光元件All之灰階相對應之脈衝頻寬PW(All)、與發 5 光元件A12之灰階相對應之脈衝頻寬PW(A12)後，分別結束 控制脈衝CPI、CP2。如此一來，藉由經振幅調變之控制脈 衝，使輸入圖像信號之灰階發光，且使發光元件之發光時 間與圖像信號之灰階相對應，藉此，可進行符合圖像信號 之灰階的亮度顯示。此時，在施加控制脈衝CPI、CP2之期 10間内，發光元件All、A12係以如圖所示之發光波形發光。 第3圖係顯示習知的問題。第3(A)圖係顯示藉由控制脈 衝CP1將發光驅動電壓vdl施加於資料線B1之狀態，第3(B) 圖係顯示結束控制脈衝CP1以結束施加發光驅動電壓vdl 後之狀態。第3(A)圖之狀態中，所選擇之掃描線C1驅動為 15選擇位準之接地，而資料線B1驅動為發光驅動電壓Vdl， 因此，發光電流IL會流過發光元件All。又，非選擇掃描線 C2〜Cn驅動為非選擇位準之逆偏壓電壓vs，且發光元件 A21〜Anl之二極體組件成為逆偏壓，故其電容組件可藉由 逆偏壓電壓Vs與發光驅動電壓Vdl之差電壓（Vs —Vdl)來 20充電。從該狀態看來，如第3(B)圖所示，在資料驅動電路 20中，一旦結束施加控制脈衝CP1，且資料線⑴成為浮動 狀態’則在與資料線B1相連接之非選擇發光元件A21〜Anl 中充電之電荷會全部流向所選擇之發光元件Au，如此一 來，發光不會立刻結束，而會繼續發光一下子。因此，如 1233085 第2圖中引用文獻編號40所示，即使結束控制脈衝cpi、 CP2’發光元件A11之發紋形也會因上述電流而無法立即 消失。該對應性的不良情況會導致發光元件之灰階特性的 直線性低劣，即，導致發光時間較對應於圖像信號之灰階 5值之控制脈衝的脈衝頻寬長，且發光亮度會變大。在前述 控制脈衝施加結束後使資料線成為浮動狀態的理由是為了 使在發光元件中充電之電荷不要無用地放電。 為了解決上述問題點，於前述先行專利（日本專利公開 公報特開2000 — 140037號）中，在資料驅動電路2〇除了接地 10及發光驅動電壓Vdl以外亦設置第3電壓端子，且在結束將 發光驅動電壓Vdl施加於資料線B1後，並非使資料線Bi成 為浮動狀態，而是將資料線B1連接於第3電壓端子。而且， 該第3電壓V3成為與發光臨界值電壓vth之間可成立V3 < Vth的關係之電位位準。如此一來，在藉由發光驅動電壓vdi 15 施加於資料線B1使發光驅動電流IL供給至發光元件Al 1的 動作結束後之時點，可將資料線B1固定於第3電壓，使來自 其他發光元件之放電電荷不會流向發光元件All。 然而，根據上述驅動方法，從第2圖中結束施加控制脈 衝CPI、CP2後之時點至水平同步期間Hsync之結束時點， 20 必須以第3電壓V3來驅動資料線B1，因此，在低灰階驅動 時’會有消耗電流增加的問題，而且，必須將所有資料線 B1〜Bn驅動為第3電壓V3，如此一來，會消耗大量的消耗電 流。再者，在使用資料驅動電路20時需要用以產生第3電壓 之電壓產生電路，因此，資料驅動電路之電路規模會變大。 !233〇85 因此’本發明之目的在於提供可防止灰階特性之直線 性低劣之發光面板顯示裝置。 再者，本發明之另一目的在於提供可一面節省耗電量 一面防止灰階特性之直線性低劣之發光面板顯示裝置。 5 【發明内容】 發明之揭示 本發明之苐1方面係發光面板顯示裝置包含：（1 )發光面 板，具有多數掃描線、多數資料線及在前述掃描線及資料 線之交叉位置與該等資料線和掃描線相連接之電容性發光 10元件；（2)掃描驅動電路，係一面依序選擇前述掃描線一面 掃描，且於各掃描期間，將所選擇之掃描線驅動為選擇電 壓，並將非選擇之掃描線驅動為較前述選擇電壓高之非選 擇電壓；及(3)資料驅動電路，係於對應於各顯示灰階之發 光期間内，將發光驅動電流供給至前述資料線。而且，於 15前述掃描期間内，前述資料驅動電路在對應於前述發光期 間之各發光開始時點，開始將前述發光驅動電流供給至前 述資料線，並在同-發光結束時點，結束將前述發光驅動 電流供給至前述多數資料線。又，前述掃描驅動電路在前 述發光結束時點，將前述所選擇之掃描線維持在較前述選 2〇擇電壓高之發光結束電壓，使與前述選擇掃描線相連接之 發光元件的發光停止。 根據第1方面，可使所有發光元件之發光結束時點為同 -時點，且在該發光結束時點，使所選擇之掃描線上升至 較選擇電壓高之發光結束電壓，以避免將發光臨界值電壓 1233085 以上之電廢施加於發光元件，如此一來，可使發光停止， 藉此可改善灰階特性。又，由於可僅驅動選擇掃描線，故 可減少伴隨於此之耗電量。 5 10 15 20 於前述本發明之第1方面之較佳實施例中，前述資料驅 動電路在前述發光結束時點後，使前述資料線成為浮動狀 態，藉此，可不必驅動資料線，以節省耗電量。 圖式簡單說明 板顯示裝置的 第1圖係習知電容性發光元件之發光面 構造圖。 第2圖係顯示第1圖之發光面板顯示裝置之資料驅動電 路的控制脈衝與發光波形的例子。 第3圖係顯示習知之課題。 第7圖係顯示本實施形態中發光面板顯示裝 弟4圖係本實施形態中發光面板顯示裝置之構造图 第5圖係本實施形態中發光面板顯示裝置之構造固 第6圖係本實施形態中發光面板顯示裝置之構造日 波形例 置之驅動 第8圖係說明本實施形態中發光結束時點下之動作 第9圖係顯示實施形態之變形例的驅動波形圖。 第10圖係本實施形態中控制脈衝產生電路的圖。 第11圖係|員示實施形態之變形例(2)的驅動波形5 第12圖係_示實施形態之變形例(3)的驅動波形圖 第13圖係顯示實施形態之變形例(4)的驅動波 【實施冷式】 10 1233085 實施發明之最佳形態 以下，依照圖式來說明本發明實施形態。 第4圖、第5圖、第6圖係本實施形態中發光面板顯示裝 置之構造圖。於該等圖中分別顯示掃描期間中不同時間下 5 之驅動電路的開關狀態。第7圖係顯示本實施形態中發光面 板顯示裝置之驅動波形例。如第4圖〜第6圖所示，發光面板 顯示裝置具有與資料線B1〜Β η和掃描線C1〜C η之所有交叉 點相連接之發光元件A11〜Ann。再者，發光面板顯示裝置 具有用以產生控制脈衝CP1〜CPn之控制脈衝產生電路50， 10 藉由該控制脈衝，使資料驅動電路20内之資料線B1〜Bn與 發光驅動電壓Vdl相連接，且控制用以供給發光驅動電流之 開關D1〜Dn。關於該控制脈衝產生電路則留待後述。又， 掃描驅動電路30具有用以供給選擇電壓之接地端子GND、 非選擇電壓端子Vs及發光結束電壓端子Vsl，且具有用以將 掃描線C1〜Cn分別驅動為接地電位gnd、選擇電麼vs及發 光結束電壓Vsl之開關S1〜Sn。 根據本實施形態，於掃描期間内，資料驅動電路_ 同-發光結树點，_結束將發光_電流供給至多數 資料線B1〜B 並在IxJx光結束時點早發光期間Cl ~ Cn scan drive circuit 30. The data driving circuit 20 has switches D1 to Dn for driving the data lines B1 to Bn to ground or a light-emission driving voltage Vdl, respectively. The 'scan driving circuit 30' has five switches S1 to Sn for driving the scanning lines ci to Cn to ground or non-selected levels with reverse bias voltages 乂 3, respectively. According to the switching state in the driving circuit shown in FIG. 1, the scanning line C1 is driven to ground and selected, and the other scanning lines C2 to Cn are driven to reverse bias voltage Vs and non-selected. The lines B1 to Bn are respectively driven to the light emission driving voltage vdl. In this state, the data lines B1 ~ Bn to the light-emitting elements All ~ Ain, that is, to the scanning lines (^, there will be a light-emitting driving current flowing through the path 10, so the light-emitting elements All ~ Ain connected to the selected scanning line ^). Will emit light. Once the light emission drive in scan line C1 is completed, drive the next scan line C2 to ground and make it selected, and the other scan lines C1, C3 ~ Cn will be driven to reverse bias voltage and will be In the non-selected state, the light-emitting driving voltage Vdl is applied to the data lines B1 to Bn. 15 During the scanning period (horizontal synchronization period) in which each scanning line becomes the selected state, the operation of applying the light-emitting driving voltage Vdl to each data line corresponds to It is controlled at the time of the gray scale of the input image signal. That is, the control pulse for applying the light-emission driving voltage vdl of the control data driving circuit 20 has a pulse width corresponding to the gray scale of the image #, so that the The image signal gray level value pair 20 should be a control pulse that is modulated by the pulse bandwidth, and the light emitting driving voltage is supplied to the data line within a time corresponding to the image signal gray level value, so that the light emitting element emits light. This is an example of the control pulses and light emission waveforms of the data driving circuit of the light-emitting panel display device shown in Figure 1. During the scanning period (horizontal synchronization period of 1233085), Hsync starts to apply the drive switch for driving the data driving circuit 20 at the same time. D1 switching control is the control pulse CP1 of the light-emission drive voltage vdl and the control pulse CP2 that performs the same operation on the drive switch D2, and corresponds to the pulse width PW (All) corresponding to the gray scale of the light-emitting element All, and 5 After the pulse width PW (A12) corresponding to the gray scale of the optical element A12, the control pulses CPI and CP2 are respectively ended. In this way, the gray scale of the input image signal is illuminated by the control pulse with amplitude modulation And the light-emitting time of the light-emitting element corresponds to the gray scale of the image signal, so that the brightness display conforming to the gray scale of the image signal can be performed. At this time, within the period of 10 times when the control pulses CPI and CP2 are applied, The light-emitting elements All and A12 emit light as shown in the figure. Fig. 3 shows a conventional problem. Fig. 3 (A) shows that the light-emission driving voltage vdl is applied to the data by the control pulse CP1. The state of B1, Fig. 3 (B) shows the state after ending the control pulse CP1 to end the application of the light-emission driving voltage vdl. In the state of Fig. 3 (A), the selected scanning line C1 is driven to the 15 selection level The data line B1 is driven to the light-emission driving voltage Vdl, so the light-emitting current IL flows through the light-emitting element All. In addition, the non-selected scanning lines C2 to Cn are driven to the reverse bias voltage vs of the non-selected level, and the light-emitting element The diode component of A21 ~ Anl becomes reverse bias, so the capacitor component can be charged by the difference voltage (Vs-Vdl) between the reverse bias voltage Vs and the light-emission driving voltage Vdl. From this state, as shown in the figure As shown in FIG. 3 (B), in the data driving circuit 20, once the application of the control pulse CP1 is completed, and the data line ⑴ becomes a floating state, the electric charges charged in the non-selected light-emitting elements A21 to Anl connected to the data line B1 It will all flow to the selected light-emitting element Au. In this way, the light emission will not end immediately, but will continue to light. Therefore, as shown in reference number 40 of FIG. 1233085, even if the control pulse cpi is ended, the hairline shape of the light-emitting element A11 of CP2 'cannot disappear immediately due to the above-mentioned current. This poor correspondence will result in poor linearity of the grayscale characteristics of the light-emitting element, that is, the light emission time will be longer than the pulse width of the control pulse corresponding to the grayscale value of 5 of the image signal, and the light emission brightness will become larger. . The reason for making the data line floating after the application of the control pulse is to prevent the electric charges charged in the light emitting element from being discharged unnecessarily. In order to solve the above-mentioned problems, in the aforementioned prior patent (Japanese Patent Laid-Open Publication No. 2000-140037), a third voltage terminal is provided in the data driving circuit 20 in addition to the ground 10 and the light-emission driving voltage Vdl. After the light emission driving voltage Vd1 is applied to the data line B1, the data line Bi is not brought into a floating state, but the data line B1 is connected to the third voltage terminal. The third voltage V3 is a potential level at which a relationship of V3 < Vth can be established between the third voltage V3 and the light emission threshold voltage vth. In this way, when the light-emitting driving voltage vdi 15 is applied to the data line B1 and the light-emitting drive current IL is supplied to the light-emitting element Al 1, the data line B1 can be fixed to the third voltage to allow other light sources to emit light. The discharge charge of the element does not flow to the light-emitting element All. However, according to the above driving method, from the time point after the application of the control pulses CPI and CP2 in the second figure to the time point when the horizontal synchronization period Hsync ends, 20 must drive the data line B1 with the third voltage V3. Therefore, at a low gray level There is a problem of increased current consumption during driving, and all data lines B1 to Bn must be driven to a third voltage V3. As a result, a large amount of current consumption is consumed. Furthermore, when the data driving circuit 20 is used, a voltage generating circuit for generating a third voltage is required. Therefore, the circuit scale of the data driving circuit becomes large. ! 233〇85 Therefore, an object of the present invention is to provide a light-emitting panel display device capable of preventing the linearity of grayscale characteristics from being poor. Furthermore, another object of the present invention is to provide a light-emitting panel display device which can reduce the power consumption while preventing the linearity of the grayscale characteristics from being poor. [Summary of the Invention] Disclosure of the Invention The first aspect of the present invention is a light-emitting panel display device including: (1) a light-emitting panel having a plurality of scanning lines, a plurality of data lines, and the intersection of the foregoing scanning lines and data lines with such data Capacitive light-emitting 10 elements connected by lines and scanning lines; (2) Scanning driving circuit, which sequentially scans the aforementioned scanning lines while sequentially scanning, and drives the selected scanning lines to a selection voltage during each scanning period, and The non-selected scanning line is driven to a non-selected voltage higher than the aforementioned selected voltage; and (3) the data driving circuit is configured to supply a luminous driving current to the aforementioned data line during a light emitting period corresponding to each display gray level. Furthermore, in the foregoing scanning period, the data driving circuit starts to supply the light-emitting driving current to the data line at each light-emitting start point corresponding to the light-emitting period, and ends the light-emitting driving at the same-light emission end time. Current is supplied to most of the aforementioned data lines. In addition, the scan driving circuit maintains the selected scan line at a light emission end voltage higher than the selected voltage at the time point when the light emission ends, and stops the light emission of the light emitting element connected to the selected scan line. According to the first aspect, the light emission end points of all light-emitting elements can be made at the same time point, and at the light emission end point, the selected scanning line is raised to a light emission end voltage higher than the selected voltage to avoid the light emission threshold voltage Electrical waste above 1233085 is applied to the light-emitting element. In this way, the light emission can be stopped, thereby improving the grayscale characteristics. Also, since only the selected scanning line can be driven, the power consumption accompanying this can be reduced. 5 10 15 20 In the foregoing preferred embodiment of the first aspect of the present invention, the data driving circuit makes the data line float after the light emission end time, thereby eliminating the need to drive the data line to save power. Battery. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a light emitting surface structure diagram of a conventional capacitive light emitting device. Fig. 2 shows examples of control pulses and light emission waveforms of the data driving circuit of the light-emitting panel display device of Fig. 1. Figure 3 shows the known issues. FIG. 7 shows the structure of the light-emitting panel display device in this embodiment. FIG. 5 shows the structure of the light-emitting panel display device in this embodiment. FIG. 5 shows the structure of the light-emitting panel display device in this embodiment. FIG. 8 is a diagram illustrating driving of an example of a structure of a medium light-emitting panel display device. FIG. 8 is a diagram illustrating an operation at a point when light emission ends in this embodiment. FIG. 9 is a driving waveform diagram showing a modification of the embodiment. Fig. 10 is a diagram of a control pulse generating circuit in this embodiment. FIG. 11 | The drive waveform 5 of the modified example (2) of the embodiment 5 FIG. 12 _ The drive waveform diagram of the modified example (3) of the embodiment FIG. 13 shows the modified example of the embodiment (4) Driving Wave [Implementing the Cold Type] 10 1233085 Best Mode for Implementing the Invention The following describes the embodiment of the present invention with reference to the drawings. Figures 4, 5, and 6 are structural diagrams of the light-emitting panel display device in this embodiment. The switching states of the driving circuit 5 at different times in the scanning period are shown in these figures. Fig. 7 shows an example of driving waveforms of the light-emitting panel display device in this embodiment. As shown in FIGS. 4 to 6, the light-emitting panel display device has light-emitting elements A11 to Ann connected to all the intersections of the data lines B1 to B η and the scanning lines C1 to C η. Furthermore, the light-emitting panel display device has a control pulse generating circuit 50 for generating control pulses CP1 to CPn. By using the control pulse, the data lines B1 to Bn in the data driving circuit 20 are connected to the light-emission driving voltage Vdl, The switches D1 to Dn for controlling the light-emitting driving current are controlled. The control pulse generating circuit will be described later. In addition, the scan driving circuit 30 has a ground terminal GND for supplying a selection voltage, a non-selection voltage terminal Vs, and an end-of-light-emission voltage terminal Vsl, and also has a function to drive the scanning lines C1 to Cn to a ground potential gnd, and a selection voltage vs And switches S1 to Sn of the light emission end voltage Vsl. According to this embodiment, during the scanning period, the data driving circuit _ is the same as the light-emitting junction point, _ ends the light-emitting _ current is supplied to the majority of the data lines B1 to B, and the light is emitted early at the end of the IxJx light
間内，掃描驅動電 同一發光結束時點結束。X，於掃描期 路30將選擇掃描線ci驅動為選擇電壓 1233085Within a short period of time, the scanning drive ends at the same time as the end of the same light emission. X, the selected scanning line ci is driven to the selected voltage 1233085 in the scanning period 30
Vs ，且在發光結束時點，將所選擇之選擇掃描線C1驅動為 較選擇電壓Vs高之發光結束電壓Vsl。藉此，在發光結束時 點，發光7L件之發光會停止。即，在發光結束時點，設定 前述發光結束電壓Vsl，使施加於與選擇掃描線^相連接之 發光元件的電壓較發光元件之發光臨界值電壓Vth小。 10 15 以下，一面參照第4圖〜第7圖，針對本實施形態之發光 面板顯示裝置的動作加以說明。第7圖中，對應於各掃描線 之掃描期間的水平同步期間Hsync包含於垂直同步期間 Vsync内的數量為掃描線的數量。於最初的掃描期間出沖㈠ 中，在時間tio時，掃描線Cl與接地端子相連接且為選擇狀 悲，除此以外之掃描線C2〜Cn則全部驅動為逆偏壓電壓 Vs。該狀態下，資料線扪〜如設為接地電位或浮動狀態凡。 現在假設發光元件All之灰階值最高，而發光元件 A12〜Ain之灰階值較其低。因此，如第4圖所示，在時間U2 時，控制脈衝CP1成為Η位準，且資料線3丨驅動為發光驅動 電壓Vdl，並開始供給發光驅動電流IL。掃描時間Hsynci 開始至發光開始時點tl2為止的時間由最大灰階值(例如256) 減去發光元件All的灰階值所得到的值來決定。然後，在時 間tl2〜tl3之間繼續第4圖之狀態。 接著，如第5圖所示，在時間tl2後之預定時間tl3中， 控制脈衝CP2〜CPn成為Η位準，且資料線B2〜Bn驅動為發光 驅動電壓Vdl，並開始供給發光驅動電流IL。另，預定時間 tl3為對應於與各資料線B2〜Bn相連接之發光元件A12〜Ain 之灰階值的時點。時間tl3〜til之間維持第5圖之狀態。其 12 1233085 間，藉由供給發光驅動電流IL，使發光元件A11〜Aln發光， 而與非選擇掃描線C2〜Cn相連接之發光元件則分別依照逆 偏壓電壓Vs與發光驅動電壓Vdl之差電壓進行充電。即， 控制脈衝CP1〜CPn之脈衝頻寬PW對應於各發％元件之灰 5卩自值，且，控制脈衝之開始邊緣為對應於各發光元件之灰 階值的時點tl2、tl3，而控制脈衝之結束邊緣在所有發光元 件為同-時點tll。另，對應於非發光元件之資料線則維持 接地電位或浮動狀態。 然後，如第6圖所示，在發光結束時點tu中，控制脈 10衝產生電路50將所有控制脈衝cpi〜(：1>11設為]1位準，且結束 將發光驅動電壓Vdl及發光驅動電流几供給至所有資料線 、Bn即’開關D1〜Dn成為高阻抗狀態，而資料線 成為浮動狀態FL。再者，在發光結束時點tn中，所選擇之 掃描線C1藉由掃描驅動電路3峨接地電位驅動至較高之發 15光結束電壓Vs卜藉此，與選擇掃描線相連接之發光元件的 發光會停止。 第8圖係說明本實施形態中發光結束時點下之動作。第 8(A)圖係顯示發光結束時點m下之狀態，且開關di因為控 制脈衝CP1之L位準而成為關閉狀態，又，資料線⑴成為浮 動狀態。然後，非選擇掃描線仏^全部驅動為非選擇位 準之逆偏壓電壓Vs，且選擇掃描線C1驅動為發光結束電壓 Vs卜如第8(B)圖所示之波形圖所示，發光結束電壓Μ設定 為使所選擇之發光元件A11不會發光之電壓位準，以避免如 虛線所示之非選擇狀態之其他元件A21〜Anl至選擇狀態^ 13 1233085 元件All之充電電流造成繼續發光。即，發光結束電壓vsi 設定為不會施加所選擇之發光元件A11發光時所需的臨界 值電壓以上之電壓位準。 具體而言，發光時，資料線81驅動為發光驅動電壓 5 Vdi ’而非選擇掃描線(32〜〇11則驅動為逆偏壓電壓。然 後，在發光結束時點，將資料線B1設為浮動狀態，且 選擇掃描線C1驅動為較選擇電壓GND高之發光結束電壓 Vsl。因此，所選擇之發光元件An的電容與非選擇狀態之 發光το件A21〜Anl之並列電容成為在逆偏壓電壓从8與發光 10結束電壓Vsl之間直列連接之狀態。因此，差電壓Vs_Vsl 會與選擇發光元件A11的電容值和非選擇發光元件 A21 Anl之並列電容值成反比而施加於各電容。伴隨於 此會發生第8(A)圖中虛線所示之若干電荷移動的情形。 I7如第8(B)圖所示之虛線Vsl所示，當發光結束電壓Vsl 15之位準較發光驅動電壓W1低時，料狀態之資料線則會 因應電容值而上升至逆顯電壓％。X，如實線所示，當 發光結束電壓Vsl較發光驅動電壓蘭高時，浮動狀態之資 料線B1也日因應電谷值而上升。但，無論何種狀況，即使 電谷1之電#移動，只要施力σ於發光元件mi之電壓未超過 20其4光臨界值電壓，則不會發光。為了成為該狀態，故設 定發光結束電壓ysl。 毛光…束電壓Vsl在使與發光驅動電壓之差不超過 I光^界值電壓Vth上成為一個標準。又，若發光結束電壓 Vsl與非選擇掃描線之逆偏壓電塵的差較發光臨界值電 1233085 壓Vth小’則不會將發光fer界值電壓以上之電壓施加於所選 擇之發光元件All。 如此一來，在同時結束將發光電流供給至與選擇掃描 線相連接之發光元件的發光結束時點，藉由將選擇掃描線 5 C1驅動為較接地電位高之發光結束電壓vsi，可使非選擇掃 描線與選擇掃描線之間的電壓差(Vs — Vsl)較習知例(vs ~ GND)小，因此，不會如過去發生大的電荷從非選擇發光元 件移動至所選擇之發光元件，如此一來，可避免發光結束 時點後，所選擇之發光元件繼續發光。 10 回到第7圖，從時間t20開始下一掃描期間HSync，且將 下一掃描線C2驅動為接地電位，並將業已選擇之掃描線C1 從發光結束電壓VsL驅動為非選擇位準之逆偏壓電壓vs。其 他非選擇掃描線C3〜Cn則維持在逆偏壓電壓vs。然後，在 對應於發光元件之灰階值的發光開始時點，開始將發光驅 15動電流供給至各資料線，且在發光結束時點t21，停止將發 光驅動電流供給至所有資料線。 如此一來，根據本實施形態，由於不須在發光結束後 將所有資料線驅動為第3電壓，且僅將丨條選擇掃描線從接 地電位驅動至接地電位與下一非選擇電位之逆偏壓電壓之 2〇間的發光結束電壓Vsl，故不會浪費消耗電流。 第9圖係顯示上述實施形態之變形例（1)的驅動波形 °與弟7圖之不同點僅在於發光結束時點til時，所選擇 之知描線C1係驅動為非選擇位準之逆偏壓電壓vs。如此一 來，藉由將選擇掃描線C1從選擇位準之接地電位驅動至非 15 1233085 選擇位準之逆偏壓電壓Vs，可透過逆偏壓電壓Vs使所選擇 之發光元件All的電容與非選擇之發光元件A21〜Anl的並 列發光元件短路，如此一來，在成為浮動狀態之資料線B1 與選擇掃描線Cl之間不會出現發光元件All之發光臨界值 5 電壓以上的電壓。 第10圖係本實施形態中控制脈衝產生電路的圖。控制 脈衝產生電路包含：計數器501，係回應用以控制掃描期間 的開始之水平同步信號Hsync，開始計數時脈CLK; 一致電 路502,係比較計數值與最大灰階值256減去輸入灰階值DIN 10後所得的值，且在相同的時點產生開始脈衝ST ;及正反器 503 ’係回應開始脈衝ST，使控制脈衝CP開始，且回應對 應於水平同步信號Hsync之結束的結束脈衝END，使控制脈 衝CP結束。 第10(B)圖顯示其動作波形。計數器5〇1係回應水平同 15步信號Hsync的上升邊緣，開始計數時脈CLK。然後，當計 數值成為最大灰階值256減去輸入灰階值DIN之值時，則產 生開始脈衝ST，且控制脈衝cp變成H位準。然後，控制脈 衝cp係回應與發光結束時點一致之結束脈衝END而變成l 位準。如此一來，控制脈衝cp之脈衝頻寬會成為對應於輸 20入灰階值DIN的長度，而輸入所有資料線之控制脈衝CP會 同時變成L位準。另，時脈CLK的頻率係設定為在水平同步 信號Hsync之脈衝頻寬期間内時脈數成為最大灰階值乃6 者。 如此一來，藉由使用第10圖之控制脈衝產生電路5〇, 16 1233085 可使與選擇掃描線相連接之所有發光元件的發光結束在同 時點’而且，可使各發光元件僅發光對應於輸入灰階值 DIN的時間。 第11圖係顯示實施形態之變形例(2)的驅動波形圖。於 5該驅動方法中，與第7圖之驅動方法的不同點係在發光結束 時點tU時將選擇掃描線C1驅動為發光結束電壓Vsi後，在 下一掃描期間Hsync2開始前的時間tl4，將所有掃描線 C1〜Cn驅動為基準電位之接地電位，同時，所有資料線 B1〜Bn亦驅動為接地電位。藉由將該等所有掃描線與所有 10資料線驅動為接地電位，可使所有發光元件之電容放電， 並全部重設。因此，將用以使資料線B1〜Bn連接於接地之 控制脈衝(未圖示)供給至資料驅動電路2 〇。 第12圖係顯示實施形態之變形例(3)的驅動波形圖。該 例子與第11圖的例子相同，在下一掃描期間Hsync開始之 15前，將所有發光元件之電容全部重設。但，用以進行該全 部重設之基準電壓為掃描線之非選擇位準VS。即，為了進 行全部重設，會將所有掃描線驅動為非選擇位準Vs，且所 有資料線亦驅動為同一電壓Vs。藉此，可透過電壓源^吏 所有發光元件的電容短路並放電。 20 第13圖係顯示實施形態之變形例(4)的驅動波形圖。該 變形例在發光結束時點tll將選擇掃描線C1驅動為發光結 束電壓Vsl，而業經發光驅動之資料線B1則維持施加發光驅 動電壓Vdl。但，此時，必須使發光結束電壓^^丨與發光驅 動電壓Vdl之差電壓不超過發光元件之發光臨界值電壓 17 1233085 vth，即，Vsl_Vdl<Vth。藉由維持該電壓關係，發光中 之發光元件可回應選擇掃描線C1驅動為發光結束電壓 Vsl，而同時停止其發光。 10 15 20 另，在上述例子的情況下，若掃描期間VSync2間有完 全不發光之發光元件，則與其對應之資料線會維持接地電 位或浮動狀態。當資料線維持在接地電位時，即使將選擇 掃描線C1驅動為發光結束電壓Vsl，該發光元件亦僅成為逆 偏壓，而不會發光。又，當資料線維持在浮動狀態時，該 等浮動之> 料線會成為依照選擇發光元件之電容與非選擇 發光元件之並列電容來分割非選擇掃描線之逆偏壓電壓Vs 與選擇掃描線之接地電位的電位。從該狀態看來，若在發 光、、、σ束時點til將選擇掃描線C1驅動為發光結束電壓， 對應於此，浮動之資料線的電位也會變化。如此-來，即 使電位有變化，為了使與該資料線相連接之發光元件不發 光，必須將發光結束時點Vsl設定在適#的位準，或者，亦 y在發光結束時點m將非發光資料線驅動為發光驅動電 β、此時選擇掃描線C1的電壓由於發光結束電壓Vsl 設定編-Vdl<vth，故該非發光之發光元件不會發光。 在第13圖之驅動方法中，於發光結束時點til時，亦可 不將選擇掃描㈣驅動為發光結束電壓Vsl，而驅動為非選 擇位準之逆偏壓電壓Vs。此時，必須成為Vs-Vdl<Vth之 哥二彳非k擇位準Vs在與發光驅動電壓W1之關係中， 係設定㈣選擇掃描線之發光料全部成為逆偏壓之電 屋。因此，藉由如此地驅動，選擇掃描線之所有發光元件 18 1233085 會與非選擇掃描線之發光元件同樣成為逆偏壓狀態。 根據以上所說明之本實施形態，由於同時結束將發光 驅動電流供給至所有資料線，且與此同時，在發光結束時 點，僅將選擇掃描線驅動為發光結束電壓或非選擇位準， 5故相較於習知例，可節省驅動電流。 產業上之可利用性 根據本發明，藉由同時結束將發光電流供給至與同一 選擇掃描線相連接之發光元件，且，此時，將選擇掃描線 驅動為發光結束電壓Vsl或非選擇位準之逆偏壓電壓Vs，可 10防止發光中之發光元件不必要地繼續發光，以改善灰階特 性。 【囷式簡單說明】 第1圖係習知電容性發光元件之杳光面板顯示裝置的 構造圖。 第2圖係顯示第1圖之發光面板顯示裝置之資料驅動電 &的控制脈衝與發光波形的例子。 第3圖係顯示習知之課題。 第4圖係本實施形態中發光面板顯示裝置之構造圖。 第5圖係本實施形態中發光面板顯示裝置之構造圖。 第6圖係本實施形態中發光面板顯示裝置之構造圖。 第7圖係顯示本實施形態中發光面板顯示裝置之驅動 波形例。 第8圖係說明本實施形態中發光結束時點下之動作。 第9圖係顯示實施形態之變形例的驅動波形圖。 1233085 第ίο圖係本實施形態中控制脈衝產生電路的圖。 第11圖係顯示實施形態之變形例(2)的驅動波形圖。 第12圖係顯示實施形態之變形例(3)的驅動波形圖。 第13圖係顯示實施形態之變形例(4)的驅動波形圖。 5 【圖式之主要元件代表符號表】 10···發光面板 20···資料驅動電路 30…掃描驅動電路 50···控制脈衝產生電路 501···計數器 502·.· —致電路 503···正反器 DIN···灰階值 ST…開始脈衝 END···結束脈衝 CLK…時脈 All〜Ann···發光元件 B1〜Bn···資料線 C1〜Cn· · ·知"描線 Vdl···發光驅動電壓 Vsl···發光結束電壓端子 D1〜Dn、S1〜Sn…開關Vs, and at the time point at which the light emission ends, the selected selection scan line C1 is driven to a light emission end voltage Vsl which is higher than the selection voltage Vs. Thereby, the light emission of the light-emitting 7L piece will stop at the point when the light emission ends. That is, at the point when light emission ends, the light emission end voltage Vsl is set so that the voltage applied to the light emitting element connected to the selected scanning line ^ is smaller than the light emission threshold voltage Vth of the light emitting element. 10 15 Hereinafter, operations of the light-emitting panel display device of this embodiment will be described with reference to FIGS. 4 to 7. In FIG. 7, the number of scanning lines in the horizontal synchronization period Hsync corresponding to the scanning period of each scanning line is included in the vertical synchronization period Vsync. During the initial scan period, at time tio, the scan line C1 is connected to the ground terminal and is selected. The other scan lines C2 to Cn are all driven to the reverse bias voltage Vs. In this state, the data line 扪 ~ is set to ground potential or floating state. Now suppose that the light-emitting element All has the highest grayscale value, and the light-emitting elements A12 to Ain have lower grayscale values than it. Therefore, as shown in FIG. 4, at time U2, the control pulse CP1 becomes the Η level, and the data line 3 is driven to the light-emission drive voltage Vdl, and the light-emission drive current IL is started to be supplied. The time from the scanning time Hsynci to the point t12 at the start of light emission is determined by a value obtained by subtracting the grayscale value of the light-emitting element All from the maximum grayscale value (for example, 256). Then, the state of FIG. 4 is continued between time t12 and t13. Next, as shown in FIG. 5, at a predetermined time t13 after time t12, the control pulses CP2 to CPn become the threshold level, and the data lines B2 to Bn are driven to the light-emission driving voltage Vdl, and the light-emission driving current IL is started to be supplied. The predetermined time t13 is a point in time corresponding to the grayscale values of the light-emitting elements A12 to Ain connected to the data lines B2 to Bn. The state of FIG. 5 is maintained between time t13 and til. Between 12 and 1233085, the light-emitting elements A11 to Aln are made to emit light by supplying the light-emitting driving current IL, and the light-emitting elements connected to the non-selected scanning lines C2 to Cn are respectively based on the difference between the reverse bias voltage Vs and the light-emitting driving voltage Vdl. Voltage for charging. That is, the pulse width PW of the control pulses CP1 to CPn corresponds to the gray value of each gray element, and the start edge of the control pulse is the time points t12, t13 corresponding to the gray level value of each light-emitting element. The ending edge of the pulse is at the same time point tll at all the light emitting elements. In addition, the data lines corresponding to the non-light-emitting elements are maintained at a ground potential or a floating state. Then, as shown in FIG. 6, at the time point tu when the light emission ends, the control pulse 10 pulse generating circuit 50 sets all the control pulses cpi ~ (: 1 > 11 to) 1 level, and ends the light emission driving voltage Vdl and light emission. The driving current is supplied to all the data lines, Bn, that is, the switches D1 to Dn are in a high impedance state, and the data lines are in a floating state FL. Furthermore, at the point tn at the end of the light emission, the selected scanning line C1 is scanned by the driving circuit The 3 A ground potential is driven to a higher light emission end voltage Vs of 15 to thereby stop the light emission of the light emitting element connected to the selected scanning line. Fig. 8 illustrates the operation at the point when light emission ends in this embodiment. 8 (A) shows the state at the point m at the end of the light emission, and the switch di is turned off due to the L level of the control pulse CP1, and the data line ⑴ becomes a floating state. Then, the non-selected scanning line 仏 ^ is driven all Is the reverse bias voltage Vs at the non-selection level, and the selected scanning line C1 is driven to the light emission end voltage Vs as shown in the waveform diagram shown in FIG. 8 (B), and the light emission end voltage M is set to make the selected light emission Component A11 will not The voltage level of the light emission to avoid the non-selected state of other elements A21 ~ Anl to the selected state as shown by the dotted line ^ 13 1233085 The charging current of the element All causes the continuous light emission. That is, the light emission end voltage vsi is set so that the selected state will not be applied The voltage level above the threshold voltage required for the light-emitting element A11 to emit light. Specifically, when the light-emitting element A11 emits light, the data line 81 is driven to a light-emission driving voltage of 5 Vdi 'instead of selecting a scanning line (32 to 〇11 is driven inversely) Bias voltage. Then, at the end of light emission, the data line B1 is set to a floating state, and the selected scanning line C1 is driven to a light emission end voltage Vsl higher than the selection voltage GND. Therefore, the capacitance of the selected light-emitting element An is The parallel capacitors of the light emitting το pieces A21 ~ Anl in the selected state are in a state of in-line connection between the reverse bias voltage from 8 and the end voltage Vsl of the light emitting 10. Therefore, the difference voltage Vs_Vsl will be equal to the capacitance value and non-selection of the selected light emitting element A11. The parallel capacitance value of the light-emitting element A21 Anl is applied to each capacitance in inverse proportion. As a result, some charges move as shown by the dotted line in FIG. 8 (A). I7 is shown by the dashed line Vsl shown in Figure 8 (B). When the level of the end-of-lighting voltage Vsl 15 is lower than the light-emission driving voltage W1, the data line of the material state will rise to the reverse display voltage% according to the capacitance value. X, as shown by the solid line, when the light emission end voltage Vsl is higher than the light emission driving voltage blue, the data line B1 in a floating state also rises in response to the electric valley value. However, no matter what the situation, even the electric valley 1 ’s electricity # Move, as long as the voltage applied to the light-emitting element mi does not exceed 20 and its 4 light threshold voltage, it will not emit light. To achieve this state, the light-emission end voltage ysl is set. Hair light ... beam voltage Vsl is driving the light It becomes a standard that the voltage difference does not exceed the threshold voltage Vth. In addition, if the difference between the light emission end voltage Vsl and the reverse bias electric dust of the non-selected scanning line is smaller than the light emission threshold value 1233085 and the voltage Vth is small, a voltage equal to or higher than the light emission fer threshold voltage will not be applied to the selected light emitting element All . In this way, at the same time when the light emission end of supplying the light-emitting current to the light-emitting element connected to the selected scanning line is ended at the same time, by driving the selected scanning line 5 C1 to a light-emission end voltage vsi higher than the ground potential, non-selection can be made. The voltage difference (Vs — Vsl) between the scanning line and the selected scanning line is smaller than the conventional example (vs ~ GND). Therefore, the large charge does not move from the non-selected light-emitting element to the selected light-emitting element as in the past. In this way, it is possible to prevent the selected light-emitting element from continuing to emit light after the light emission end time. 10 Returning to FIG. 7, the next scanning period HSync is started from time t20, and the next scanning line C2 is driven to the ground potential, and the selected scanning line C1 is driven from the light emission end voltage VsL to the inverse of the non-selection level. Bias voltage vs. The other non-selected scanning lines C3 to Cn are maintained at the reverse bias voltage vs. Then, at the point in time when the light emission corresponding to the gray-scale value of the light-emitting element is started, the light-emitting driving current is started to be supplied to each data line, and at the time point t21 when the light-emitting ends, the supply of the light-emitting driving current is stopped to all the data lines. In this way, according to this embodiment, since it is not necessary to drive all data lines to the third voltage after the light emission is completed, and only one selection scanning line is driven from the ground potential to the reverse bias of the ground potential to the next non-selected potential Since the light-emission end voltage Vsl between the voltage and voltage is 20, the current consumption is not wasted. Fig. 9 shows the driving waveform of the modification (1) of the above embodiment. The difference from Fig. 7 is that at the point til at the end of the light emission, the selected known drawing line C1 is driven to a non-selection level reverse bias. Voltage vs. In this way, by driving the selection scan line C1 from the ground potential of the selection level to a value other than 15 1233085, the reverse bias voltage Vs of the selection level can make the capacitance of the selected light-emitting element All and the The parallel light-emitting elements of the non-selected light-emitting elements A21 to Anl are short-circuited. As a result, a voltage greater than the light-emitting threshold value 5 of the light-emitting element All does not occur between the data line B1 and the selected scanning line C1 that are in a floating state. Fig. 10 is a diagram of a control pulse generating circuit in this embodiment. The control pulse generating circuit includes: a counter 501, which responds to the horizontal synchronization signal Hsync used to control the start of the scanning period, and starts counting the clock CLK; a coincidence circuit 502, which compares the count value with the maximum grayscale value 256 minus the input grayscale value The value obtained after DIN 10, and the start pulse ST is generated at the same time point; and the flip-flop 503 'responds to the start pulse ST to start the control pulse CP and responds to the end pulse END corresponding to the end of the horizontal synchronization signal Hsync, The control pulse CP ends. Figure 10 (B) shows its operation waveform. The counter 501 responds to the rising edge of the 15-step signal Hsync and starts counting the clock CLK. Then, when the count value becomes the maximum grayscale value 256 minus the input grayscale value DIN, a start pulse ST is generated, and the control pulse cp becomes the H level. Then, the control pulse cp becomes the l level in response to the end pulse END which coincides with the point at which the light emission ends. In this way, the pulse width of the control pulse cp will become a length corresponding to the input gray level value DIN, and the control pulse CP input to all data lines will become the L level at the same time. In addition, the frequency of the clock CLK is set to a value in which the number of clocks reaches the maximum grayscale value during the pulse width period of the horizontal synchronization signal Hsync, which is six. In this way, by using the control pulse generating circuit 50, 16 1233085 in FIG. 10, the light emission of all light-emitting elements connected to the selected scanning line can be ended at the same time. Moreover, each light-emitting element can emit light only corresponding to Enter the time for the grayscale value DIN. Fig. 11 is a driving waveform diagram showing a modification (2) of the embodiment. In this driving method, the difference from the driving method of FIG. 7 is that the selected scanning line C1 is driven to the light emission end voltage Vsi at the point tU at the end of light emission, and the time t14 before the start of the next scanning period Hsync2 is set to t1. The scanning lines C1 to Cn are driven to the ground potential of the reference potential, and all the data lines B1 to Bn are also driven to the ground potential. By driving all the scanning lines and all the 10 data lines to the ground potential, the capacitances of all the light emitting elements can be discharged and reset all. Therefore, a control pulse (not shown) for connecting the data lines B1 to Bn to the ground is supplied to the data driving circuit 20. Fig. 12 is a driving waveform diagram showing a modification (3) of the embodiment. This example is the same as the example in Fig. 11. Before the start of Hsync in the next scanning period, the capacitances of all light-emitting elements are reset. However, the reference voltage used for this full reset is the non-selection level VS of the scan line. That is, in order to perform a full reset, all scan lines are driven to the non-selection level Vs, and all data lines are also driven to the same voltage Vs. Thereby, the capacitors of all the light emitting elements can be short-circuited and discharged through the voltage source. 20 FIG. 13 is a driving waveform diagram showing a modification (4) of the embodiment. In this modification, the selected scanning line C1 is driven to the light emission end voltage Vsl at the point t11 at the end of the light emission, and the data line B1 subjected to the light emission driving maintains the application of the light emission driving voltage Vdl. However, at this time, the difference voltage between the light emission end voltage ^^ 丨 and the light emission driving voltage Vdl must not exceed the light emission threshold voltage 17 1233085 vth of the light emitting element, that is, Vsl_Vdl < Vth. By maintaining the voltage relationship, the light-emitting element in light emission can be driven to the light-emission end voltage Vsl in response to the selection of the scanning line C1, while stopping its light emission. 10 15 20 In the case of the above example, if there are no light-emitting elements between VSync2 during scanning, the corresponding data line will maintain the ground potential or floating state. When the data line is maintained at the ground potential, even if the selected scanning line C1 is driven to the light emission end voltage Vsl, the light emitting element is only reverse biased and does not emit light. In addition, when the data line is maintained in a floating state, the floating > material lines will become the reverse bias voltage Vs and the selective scanning of the non-selected scanning line according to the capacitance of the selected light-emitting element and the parallel capacitance of the non-selected light-emitting element. Ground potential of the line. From this state, if the selected scanning line C1 is driven to the light-emission end voltage at the time of the light emission, the light beam, and the sigma beam, the potential of the floating data line changes accordingly. In this way, even if the potential changes, in order to prevent the light-emitting element connected to the data line from emitting light, the point Vsl at the end of light emission must be set to an appropriate level, or the non-emission data at point m at the end of light emission. The line drive is the light-emission drive voltage β. At this time, the voltage of the selected scanning line C1 is set to -Vdl < vth because the light-emission end voltage Vsl is set, so the non-light-emitting light-emitting element does not emit light. In the driving method of FIG. 13, at the point til at the end of the light emission, the selective scanning frame may not be driven to the light emission end voltage Vsl, but may be driven to the reverse bias voltage Vs of the non-selection level. At this time, Vs-Vdl < Vth must be the second non-k-selective level Vs in the relationship with the light-emission drive voltage W1, which is set to select all the luminescent materials of the scan line to be reverse biased. Therefore, by driving in this way, all the light-emitting elements 18 1233085 of the selected scanning line become reverse biased like the light-emitting elements of the non-selected scanning line. According to the embodiment described above, the supply of the light-emission drive current to all data lines is ended at the same time, and at the same time, only the selected scanning line is driven to the light-emission end voltage or non-selection level at the time of light-emission end. Compared with the conventional example, the driving current can be saved. INDUSTRIAL APPLICABILITY According to the present invention, the supply of the light-emitting current to the light-emitting elements connected to the same selected scan line is ended simultaneously, and at this time, the selected scan line is driven to the light-emitting end voltage Vsl or a non-selection level. The reverse bias voltage Vs can prevent the light-emitting element during light emission from continuing to emit light unnecessarily, thereby improving grayscale characteristics. [Brief description of the formula] FIG. 1 is a structural diagram of a conventional panel display device of a capacitive light emitting element. Fig. 2 shows an example of control pulses and light emission waveforms of the data driving circuit & Figure 3 shows the known issues. FIG. 4 is a structural diagram of a light-emitting panel display device in this embodiment. Fig. 5 is a structural diagram of a light-emitting panel display device in this embodiment. Fig. 6 is a structural diagram of a light-emitting panel display device in this embodiment. Fig. 7 shows an example of driving waveforms of the light-emitting panel display device in this embodiment. FIG. 8 illustrates the operation at the point when light emission ends in this embodiment. Fig. 9 is a driving waveform diagram showing a modification of the embodiment. 1233085 The diagram is a diagram of a control pulse generating circuit in this embodiment. Fig. 11 is a driving waveform diagram showing a modification (2) of the embodiment. Fig. 12 is a driving waveform diagram showing a modification (3) of the embodiment. Fig. 13 is a driving waveform diagram showing a modification (4) of the embodiment. 5 [Representative symbol table of main elements of the drawing] 10 ··· Light-emitting panel 20 ··· Data driving circuit 30 ·· Scan driving circuit 50 ··· Control pulse generating circuit 501 ··· Counter 502 ·· —Caution circuit 503 ··· Inverter DIN ··· Gray level value ST ... Start pulse END ·· End pulse CLK ... Clock All ~ Ann ·· Light emitting element B1 ~ Bn ·· Data line C1 ~ Cn ·· Know " Drawing line Vdl · ·· Light emission driving voltage Vsl · ·· Emission light end voltage terminals D1 ~ Dn, S1 ~ Sn ... Switch
Vs...逆偏壓電壓Vs ... reverse bias voltage
Vs···非選擇位準 Vs...選擇電壓 Vs...電壓源 Vs···非選擇電壓端子 Hsync…掃描期間、水平同步 期間 CP 1〜CPn · · ·控制脈衝 PW···脈衝頻寬 Vth···發光臨界值電壓 V3...第3電壓 IL···發光驅動電流 GND···接地電位、接地端子 FL…浮動狀態 t...時間 20Vs ... Non-selection level Vs ... Selection voltage Vs ... Voltage source Vs ... Non-selection voltage terminal Hsync ... During scanning and horizontal synchronization CP 1 to CPn ... Control pulse PW ... Pulse Bandwidth Vth ... Light emission threshold voltage V3 ... 3rd voltage IL ... Light emission drive current GND ... Ground potential, ground terminal FL ... Floating state t ... Time 20