1232429 玫、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明) 【一、發明所屬之技術領域】 本發明係關於語音資料解碼的技術領域，尤 指一種應用於語音解碼記憶體系統之資料簡併 方法。 【二、先前技術】 一般語音資料為節省儲存空間，常以一可適 性差分脈衝碼調變（Adaptive Differential Pulse Code Modulation， ADPCM)將語音資料先 行處理後再予以儲存，圖1顯示一可適性差分脈 衝碼調變裝置，其中，輸入之8位元語音訊號忒〃) 係先與先前之語音訊號兴〃）相減，以得到一 8位元 之誤差訊號，此誤差訊號 經由一量化器 1 0 0量化後產生4位元之訊號以輸出儲存 之，且該4位元訊號並經由一遲延器110之延 遲後，再與一 4位元之步階裝置（step)120相乘而 得到一 8位元之訊號兴〃），以供與下次輸入之語音 訊號〆幻相減來產生下次之誤差訊號e(w)，，藉 此，可僅儲存對該量化後之誤差訊號，而達 到節省儲存空間之目的。 6 1232429 該經由ADPCM編碼之4位元之訊號係儲存 於一記憶體中，如欲使用該訊號，則如圖2 所示，該訊號先與一 4位元之步階裝置 (s t e ρ ) 2 0 0經由一乘法器2 2 0相乘而得到一 8位元 之訊號力>)，此8位元之訊號經由一加法器230 與訊號sO — 1)相加後即可得到一 8位元之訊號 ，由訊號^(w)便可求出原來之語音訊號， 此訊號經由一遲延器2 1 0後產生一 ^(w)訊 號，。由於此種8位元語音訊號一般係使用 在比較低階產品上，為了價格考量，甚少使用圖 2中所示之乘法器2 2 0，而係使用一處理器以查表 方式而獲得該8位元之語音訊號兴w)，其中，該4 位元之訊號係如圖3所示為以二個一組而存 放在一位元組（b y t e )中，處理器則執行如圖4之 指令，以獲得儲存在低4位元處之該語音訊號$(w) 之指標（ρ 〇 i n t e r )，依據該指標而由一事先設計 好的表格查出該語音訊號利w)，再執行如圖5之指 令，以獲得儲存在高4位元處之該語音訊號之 指標（ρ 〇 i n t e r)，依據該指標而由該表格查出另 一語音訊號咖）。 1232429 然而，採用此種對ADPCM壓縮訊號解碼時， 會佔用許多處理器的資源，同時該等處理器由於 成本考量，根本沒有提供乘法指令，更沒有提供 Barrel Shift指令（一次可同時向右或向左移動 η位元指令），如該等處理器欲執行向右要移動4 位元指令，仍須如圖5所示分成4次向右移動1位 元，因此，習知處理器之ADPCM壓縮訊號解碼的 方法仍有諸多缺失而有予以改進之必要。 發明人爰因於此，本於積極發明之精神，亟 思一種可以解決上述問題之「應用於語音解碼記 憶體系統之資料簡併方法」，幾經研究實驗終至 完成此項發明。 【三、發明内容】 本發明之目的係在提供一種應用於語音解 碼記憶體系統之資料簡併方法，可避免習知技術 需使用乘法指令或B a r r e 1 S h i f t指令，以節省處 理器的資源，同時程式碼更簡潔，而達到提升解 碼效率之目的。 依據本發明之一特色，係提出一種應用於語 音解碼記憶體系統之資料處理方法，該系統包含 一非揮發性記憶體，其具有複數個2N位元之字 組，用以儲存已編碼之複數筆語音資料、複數個 步階大小及一表格，每一筆編碼之語音資料具有 N位元，其中奇數語音資料0[N-1 :0]與偶數筆語 1232429 曰貝料Ε[Ν〜1··〇]係交錯排列成2N位元 EnmOn-!…Eq〇g而儲存於該非揮發性記憶體之一字 組，该步階大小s [ N- 1 : 〇 ]係間隔排列成2N位元 SnmO…S〇0而儲存於該非揮發性記憶體之一字 組’该表格係儲存已解碼之差分語音資料，該方 法主要包括下列步驟：（A)由該非揮發性記憶體 中讀取一字組之已編碼語音資料；（B)對該筆語 音資料進行邏輯運算，以得到一索引值；（c)依 據该索引值以由該表袼中擷取對應之已解碼差分 語音資料；以及（D)將由該表格中擷取之差分語音 資料與先前之語音資料進行加法運算，以得到一 實際之語音資料。 依據本發明之另一特色，係提出一種應用於 語音解碼記憶體系統之資料處理方法，該系統包 含一非揮發性記憶體，其具有複數個2 N位元之字 組’用以儲存已編碼之複數筆語音資料、複數個 步階大小及一表格，每一筆編碼之語音資料具有 N位元’其中奇數語音資料〇[N—丨：〇]與偶數筆語 音資料E [ N - 1 ·· 〇 ]及步階大小係先離線運算後而 儲存於該非揮發性記憶體之字組χ2Ν_ιΧ2Ν_^·· XlXo 中’ s 中 ’ X2i = 0i ㊉ Si’ X2i + 1 = Ei ㊉ Si，0$i$N -1， 该步階大小S [ N - 1 ·· 0 ]係以重複位元之方式排列 成2N位元SnmSn-^·· S〇S〇而儲存於該非揮發性記憶 體之一字組，該表格係儲存已解碼之差分語音資 1232429 料，該方法主要包括下列步驟：（A)由該非揮發 性記憶體中讀取一字組之已編碼語音資料’（β) 對該筆語音資料進行邏輯運算，以得到一索引 值；（C)依據該索引值以由該表袼中擷取對應之已 解碼差分語音資料；以及（D)將由該表格中操取之 差分語音資料與先前之語音資料進行加法運 算，以得到一實際之語音資料。 由於本發明設計新穎，能提供產業上利用’ 且確有增進功效，故依法申請發明專利。 【四、實施方式】 圖6顯示本發明之應用於語音解碼記憶體系統 之資料簡併方法的流程圖，其中，語音解碼記憶體 系統包含有一非揮發性記憶體，如圖7所示，非 揮發性記憶體具有複數個2 Ν位元之字組7 0 0，用 以儲存已編碼之複數筆語音資料7 〇 1、複數個步 階大小7 0 2及一表格7 0 3，為方便說明，非揮發性 記憶體之字組7 0 0長度為8(Ν = 4)，亦即，每一字 矣且7 〇 〇為一位元組（byte)700’而該等已編碼語音 資料7 0 1係由處理器8 0 0依序讀出以進行解碼。 前述每一筆已編碼之語音資料7 0 1為一半位 元組（nibble)，亦即，每一筆語音資料701具有N =4位元，而一位元組70 0中具有奇（Odd)、偶 (Even)兩筆語音資料0[3:0]及E[3:0]，當中，奇 數語音資料0 [ 3 : 0 ]與偶數語音資料E [ 3 : 0 ]係交 10 1232429 錯排列成一位元組to3…Eg0。以儲存於該非揮發 性記憶體之一位元組70 0中；每一步階大小^2 具有4個有效位元s[3:〇]，其係以間隔排列成8 位元S: s〇o 憶 一位 元組700 ;該表格70 3則係儲存有相應於已編碼語 音資料7 0 1的已解碼差分語音資料。 再請參照圖6所示，本發明之方法首先由該處理 器8 0 0自該非揮發性記憶體中讀取一字組（即位 元組）之語音資料E3〇3…ΕοΟ。（步驟S601)，於步驟 S602中，處理器800對該讀取之語音資料中的奇數 及偶數語音資料分別進行邏輯運算，以得到一筆 該奇數語音資料之索引值及一筆該偶數語音資 料之索引值’如圖8所示，前述邏輯運算係先對 該語音資料E3〇3…EoOo進行與01…〇11)之邏輯及 (AND)運算以得到〇〇3…〇〇。，再與一步階大小進行 邏輯或（OR)運算以得到S3〇3"n，此即為該奇 數語音資料之索引值；同時，如圖9所示，前述 邏輯運亦對該語音資料進行向右移丨位元後，將 之與01…01b進行邏輯及（AND)運算而得到 0Ε3···0Ε。，再與一步階大小進行邏輯或（〇R)運 算，以得到該偶數語音資料之索引值S3E3··· &Ε。。 於步驟S603中，該處理器80 0依據該索引值 s3〇3…Sq〇〇及s3e3…s〇E〇以分別由該表格7〇3中擷 取相對應之已解碼差分語音資料；於步驟S6〇4中， 該處理器800將該由表袼70 3中所擷取之差分語音 1232429 資料與先前之已完成解碼之奇、偶數語音資料分 別進行加法運算，以分別得到實際之奇、偶數語 音資料。 於步驟S605中，檢查是否仍有待解碼之語音資 料，若有則重回步驟S601中，若無，則結束處理過程。 圖1 0係本發明另一實施例之語音解碼記憶體系 統的記憶體配置圖，其與前一實施例之不同處在 於奇數語音資料0 [ N- 1 : 0 ]與偶數語音資料 E [ N- 1 : 0 ]及步階大小係先離線運算後而儲存於 非揮發性記憶體之2N位元字組X2NMX2N-2…XiXo 中，當中，X2i = 〇i ㊉ Si，X2i + 1 二EieSi，0$i$N- 1， 於本實施例中，N=4，X〇 = 〇〇eS〇、XpEoeSo、X2 = Ch ㊉ Si、X3 = El ㊉ Si、㊉ S2、X5 = E2 ㊉ S2' X6 = 〇3 ㊉ S3、 Χ7 = Ε3θ S3,又每一步階大小7 0 2之有效位元s[3:0] 係以重複位元之方式排列成8位元S3S3…S〇Sg而 儲存於該非揮發性記憶體之一位元組7 0 0。 以本實施例之記憶體配置，本發明之方法的 執行步驟係相同於圖6所示，惟在步驟S602中，如 圖11所示，處理器8 〇 〇係將讀取之語音資料 X ?X6…ΧιΧο與〇1…〇1 b進行邏輯及（AND)運算以得 到OX6··· OX〇，再與一步階大小進行邏輯互斥或 (X 0 R)運鼻以得到§3 〇3…S 〇 0。’而得到奇數語音資 料之索引值；同時，如圖1 2所示，處理器8 0 〇亦 對該語音資料進行向右移1位元（成為X。X 7…X 2 χ ^ 後’將之與01…〇lb進行邏輯及（AND)運算而得到 12 1232429 0E?…0E!，再與一步階大小進行邏輯互斥或（x〇R) 運算，以得到偶數語音資料之索引值S3E3〜 S()E。。 由上述之說明可知，本發明係將語音資料以 特定之方式排列於記憶體中，而可在以ADPCM解 碼來讀出資料時，無需像習知技術需使用乘法指 令或Barrel Shi ft指令，故不會佔用許多處理器 的資源，同時程式碼更簡潔，而達到提升解碼效 率之目的。 系不上所陳，本發明無論就目的、手段及功 效’在在均顯示其迥異於習知技術之特徵，實為 一極具實用價值之發明，懇請貴審查委員明 二、、’=曰賜准專利，俾嘉惠社會，實感德便。惟 ^ I二的疋，上述諸多實施例僅係為了便於說明 =:圍已所本發明所主張之權利範圍 圍所述為準’而非僅限於上述實施例。 【五、圖式簡單說明】 圖1 ·:ι知之可適性差分脈衝瑪調變_如^^ 圖2 ·署係—習知之可適性差分脈衝瑪▲ 置。 馬调變（ADPCM)解碼裝 圖3 ··係—雙 知可適性差分脈衝螞 不意圖。 免、、扁螞訊號d>〇儲存 13 1232429 圖4 :係一習知ADPCM編碼訊號低4位元c〇z — 1)解碼程式 碼。 圖5 :係一習知ADPCM編碼訊號高4位元解碼程式碼。 圖6 :係本發明之ADPCM編碼訊號解碼之流程圖。 圖7 :係本發明之ADPCM編碼訊號之儲存示意圖。 圖8 :係本發明之ADPCM編碼訊號之低4位元解碼之示意 圖。 圖9 :係本發明之ADPCM編碼訊號之高4位元解碼之示意 圖。 圖10 :係本發明另一實例之ADPCM編碼訊號之儲存示意 圖。 圖11 :係本發明另一實例之ADPCM編碼訊號之低4位元解 碼之示意圖。 圖12 :係本發明另一實例之ADPCM編碼訊號之高4位元解 碼之示意圖。 【圖號說明】 量化器 100 步階裝置 120 遲延器 210 加法器 230 遲延器 110 步階裝置 200 乘法器 220 處理器 8001232429 Description of the invention (The description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings) [I. The technical field to which the invention belongs] The present invention relates to the technical field of speech data decoding , Especially a data degenerative method applied to a speech decoding memory system. [II. Prior Technology] In order to save storage space for general speech data, an adaptive differential pulse code modulation (ADPCM) is often used to process the speech data before it is stored. Figure 1 shows an adaptive difference Pulse code modulation device, in which the input 8-bit voice signal 忒 〃) is first subtracted from the previous voice signal to obtain an 8-bit error signal, and this error signal passes a quantizer 1 0 After 0 quantization, a 4-bit signal is generated for output storage, and the 4-bit signal is delayed by a delay device 110, and then multiplied by a 4-bit step device 120 to obtain an 8 The bit signal is used to generate the next error signal e (w) by subtraction from the next input voice signal, so that only the quantized error signal can be stored to achieve The purpose of saving storage space. 6 1232429 The 4-bit signal encoded by ADPCM is stored in a memory. If you want to use the signal, as shown in Figure 2, the signal is first connected to a 4-bit step device (ste ρ) 2 0 0 is multiplied by a multiplier 2 2 0 to obtain an 8-bit signal strength>), and the 8-bit signal is added to the signal sO through an adder 230-1) to obtain an 8-bit signal Yuan signal, the original voice signal can be obtained from the signal ^ (w), and this signal passes through a delay device 2 10 to generate a ^ (w) signal. Because this 8-bit voice signal is generally used on lower-order products, for price considerations, the multiplier 2 2 0 shown in Figure 2 is rarely used, and it is obtained by using a processor to look up the table. The 8-bit voice signal is w), where the 4-bit signal is stored in a byte as two groups as shown in FIG. 3, and the processor executes as shown in FIG. 4 Instruction to obtain the index (ρ 〇inter) of the voice signal $ (w) stored in the lower 4 bits, and find out the voice signal from a pre-designed form according to the index, and then execute as The command of FIG. 5 is to obtain the index (ρ INTER) of the voice signal stored in the upper 4 bits, and another voice signal is found from the table according to the index). 1232429 However, when using this type of decoding of ADPCM compressed signals, it will consume many processor resources. At the same time, due to cost considerations, these processors do not provide multiplication instructions at all, nor do they provide Barrel Shift instructions. Move n-bit instructions to the left). If these processors want to execute 4-bit instructions to the right, they must still be divided into 4 times to move to the right by 1 bit as shown in Figure 5. Therefore, the ADPCM compression of conventional processors is known. There are still many shortcomings in the signal decoding method and it is necessary to improve it. Because of this, the inventor, in the spirit of active invention, is desperate for a "data reduction method for speech decoding memory system" that can solve the above problems. After several research experiments, this invention has been completed. [III] Summary of the Invention The purpose of the present invention is to provide a data degenerate method applied to a speech decoding memory system, which can avoid the need for the conventional technology to use multiplication instructions or Barre 1 S hift instructions to save processor resources. At the same time, the code is more concise and achieves the purpose of improving decoding efficiency. According to a feature of the present invention, a data processing method applied to a speech decoding memory system is proposed. The system includes a non-volatile memory with a plurality of 2N-bit words for storing the encoded complex number. Pen speech data, multiple step sizes, and a table, each encoded speech data has N bits, of which the odd speech data 0 [N-1: 0] and the even stroke phrase 1232429 曰 贝 料 Ε [Ν〜1 · · 〇] are staggered into 2N bits EnmOn-! ... Eq〇g and stored in a block of the non-volatile memory. The step size s [N-1: 〇] is spaced into 2N bits SnmO … S00 and stored in a block of the non-volatile memory 'The table stores decoded differential voice data. The method mainly includes the following steps: (A) reading a block from the non-volatile memory The encoded speech data; (B) performing a logical operation on the speech data to obtain an index value; (c) extracting the corresponding decoded differential speech data from the table according to the index value; and (D) ) Differential voice data to be extracted from the form It is expected that an addition operation is performed with the previous voice data to obtain an actual voice data. According to another feature of the present invention, a data processing method applied to a speech decoding memory system is proposed. The system includes a non-volatile memory having a plurality of 2 N-bit words' for storing coded data. A plurality of speech data, a plurality of step sizes, and a table, each encoded speech data has N bits' of which the odd speech data 〇 [N— 丨: 〇] and the even speech data E [N-1 ·· 〇] and step size are stored offline in the non-volatile memory χ2Ν_ιχ2Ν _ ^ ... X1Xo 's in X2i = 0i ㊉ Si' X2i + 1 = Ei ㊉ Si, 0 $ i $ N -1, the step size S [N-1 ·· 0] is arranged in a repeating bit manner into 2N bits SnmSn- ^ ·· S〇〇 and stored in a block of the non-volatile memory The form stores the decoded differential voice data 1232429. The method mainly includes the following steps: (A) reading a block of coded voice data from the non-volatile memory '(β) for the voice data Perform a logical operation to obtain an index value; (C) according to the The index value is obtained by extracting the corresponding decoded differential voice data from the table; and (D) adding the differential voice data manipulated from the table to the previous voice data to obtain an actual voice data. Since the present invention has a novel design, can provide industrial utilization ', and has indeed enhanced efficacy, it has applied for an invention patent in accordance with the law. [Embodiment] FIG. 6 shows a flowchart of a method for degenerating data applied to a speech decoding memory system according to the present invention. The speech decoding memory system includes a non-volatile memory, as shown in FIG. The volatile memory has a plurality of 2 N-bit characters 7 0 0 for storing a plurality of coded speech data 7 0 1, a plurality of step sizes 7 0 2 and a table 7 0 3, for convenience of explanation. The length of the non-volatile memory block 7 0 0 is 8 (N = 4), that is, each word 矣 and 7 000 is a byte 700 'and the encoded speech data 7 0 1 is read sequentially by the processor 8 0 0 for decoding. Each of the previously encoded speech data 7 0 1 is a nibble, that is, each speech data 701 has N = 4 bits, and a byte 70 0 has odd (Odd), even (Even) Two pieces of voice data 0 [3: 0] and E [3: 0]. Among them, the odd-numbered voice data 0 [3: 0] and the even-numbered voice data E [3: 0] are intersected by 10 1232429. The tuple to3 ... Eg0. It is stored in a byte 70 0 of the non-volatile memory; each step size ^ 2 has 4 significant bits s [3: 〇], which are arranged at intervals into 8 bits S: s〇o Recall one byte 700; the table 703 stores decoded differential speech data corresponding to the encoded speech data 701. Please refer to FIG. 6 again. In the method of the present invention, the processor 800 first reads a word (ie, a byte) of voice data E3 03 ... EοO from the non-volatile memory. (Step S601) In step S602, the processor 800 performs logical operations on the odd and even voice data in the read voice data to obtain an index value of the odd voice data and an index of the even voice data. The value 'is shown in FIG. 8. The aforementioned logical operation first performs an AND operation on the voice data E3 03 ... EoOo with 01 ... 〇11) to obtain 〇03 ... 〇〇. , And then perform a logical OR operation with the step size to obtain S3 03 " n, which is the index value of the odd-numbered voice data; at the same time, as shown in FIG. 9, the aforementioned logic operation also performs After shifting to the right by 丨 bits, perform logical AND operation with 01 ... 01b to obtain 0E3 ... 0E. , And then perform a logical OR operation with the step size to obtain the index value S3E3 of the even voice data & E. . In step S603, the processor 800 retrieves the corresponding decoded differential voice data from the table 703 according to the index values s303, Sq00, and s3e3, s0E0. In S604, the processor 800 adds the differential voice 1232429 data retrieved from Table 703 and the previously decoded odd and even voice data to add operations to obtain the actual odd and even numbers respectively. Voice data. In step S605, it is checked whether there is still speech data to be decoded, and if there is any, the process returns to step S601. If not, the process ends. FIG. 10 is a memory configuration diagram of a speech decoding memory system according to another embodiment of the present invention. The difference from the previous embodiment lies in the odd-numbered speech data 0 [N-1: 0] and the even-numbered speech data E [N -1: 0] and step size are stored offline in non-volatile memory in 2N byte X2NMX2N-2 ... XiXo, where X2i = 〇i ㊉ Si, X2i + 1 and EieSi, 0 $ i $ N-1, in this embodiment, N = 4, X〇 = 〇〇eS〇, XpEoeSo, X2 = Ch ㊉ Si, X3 = El ㊉ Si, ㊉ S2, X5 = E2 ㊉ S2 'X6 = 〇3 ㊉ S3, χ7 = Ε3θ S3, and the effective bits s [3: 0] of each step size 7 0 2 are arranged as 8-bit S3S3 ... S〇Sg in a repeating manner and stored in the non- One byte of volatile memory is 7 0 0. With the memory configuration of this embodiment, the execution steps of the method of the present invention are the same as those shown in FIG. 6, but in step S602, as shown in FIG. 11, the processor 800 is the voice data X to be read. X6 ... Xιχο performs logical AND operation with 〇1 ... 〇1 b to get OX6 ... OX〇, and then performs a logical mutual exclusion with the step size or (X 0 R) nose to get §3 〇3 ... S 0. 'And get the index value of the odd voice data; at the same time, as shown in Figure 12, the processor 800 also shifts the voice data to the right by 1 bit (becomes X. X 7 ... X 2 χ ^ The result is logically ANDed with 01 ... 〇lb to get 12 1232429 0E? ... 0E !, and then performed a logical mutual exclusion or (x〇R) operation with a step size to obtain the index value S3E3 of the even voice data ~ S () E ... As can be seen from the above description, the present invention arranges the voice data in the memory in a specific way, and when reading the data by ADPCM decoding, there is no need to use multiplication instructions or The Barrel Shi ft instruction will not occupy many processor resources, and at the same time, the code is more concise, and the purpose of improving decoding efficiency is achieved. Not surprisingly, the present invention shows its no matter its purpose, means and efficacy. The characteristics that are quite different from the conventional technology are really an invention of great practical value. I ask your reviewing committee to make clear the patents, '= said to grant a quasi-patent, to benefit the society, and to have a sense of morality. But ^ I 2's 疋, above Many embodiments are just for ease of explanation =: The scope of the claimed rights of the present invention shall prevail and is not limited to the above-mentioned embodiments. [Fifth, a brief description of the drawings] Figure 1: Applicable differential pulse pulse modulation known as ^^^ Figure 2 · Department—Knowledgeable adaptive differential pulse setting ▲ Horse modulation (ADPCM) decoding equipment Figure 3 ·· Department—Double knowledge adaptive differential pulse not intended. Free, flat signal d > 0 storage 13 1232429 Figure 4: The lower 4 bits of the conventional ADPCM encoding signal coz — 1) decoding code. Figure 5: A conventional 4-bit decoding code for ADPCM encoding signals. FIG. 6 is a flowchart of decoding the ADPCM coded signal according to the present invention. FIG. 7 is a schematic diagram of storing an ADPCM coded signal according to the present invention. FIG. 8 is a schematic diagram of decoding the lower 4 bits of the ADPCM coded signal of the present invention. FIG. 9 is a schematic diagram of decoding the upper 4 bits of the ADPCM coded signal of the present invention. FIG. 10 is a schematic diagram of storage of an ADPCM coded signal according to another example of the present invention. FIG. 11 is a schematic diagram of decoding the lower 4 bits of an ADPCM coded signal according to another example of the present invention. FIG. 12 is a schematic diagram of decoding the upper 4 bits of an ADPCM encoded signal according to another example of the present invention. [Illustration of figure number] quantizer 100 step device 120 delay device 210 adder 230 delay device 110 step device 200 multiplier 220 processor 800
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