TWI232031B - Quadrature gain and phase imbalance correction in a receiver - Google Patents

Abstract

The present invention offers a low cost, reliable, on chip implementation that takes advantage of circuitry already present in receivers to calibrate and correct for gain and phase errors in a transceiver device. The present invention employs a digital signal processor along with multiple phase shifters and all pass networks to ensure proper levels of quadrature signals within the transceiver. An internally generated double sideband suppressed carrier signal is created to produce the calibration signals used by the digital signal processor.

Description

Ι23203Ϊ

V. Description of the invention (1) 1. The technical field to which the invention belongs A method for correcting a receiver The present invention relates to the gain and phase of a square path. 2 · Prior technology 隹 Wireless m is used to reduce the frequency spectrum required for communication and thus maximize the communication capacity of the communication system.

The modulation method usually involves the conversion of the communication signal into a separate form, while the modulation signal is typically a reduced frequency spectrum. One method of transmitting communication signals in a separated form is through the use of quadrature modulation. In quadrature modulation, the binary data stream of the encoded k signal is divided into bit pairs (bits). This kind of bit pair is used to make the phase shift of the Rp carrier signal according to the value of the individual bit pair of the coded signal to increase or decrease, for example, plus or minus 7Γ / 4 diameter or plus or minus 7Γ / 4 diameter. The phase shift is achieved using a binary data stream containing bit pairs in a pair of mixing circuits. The sine component of a carrier signal is added to the input of a first mixing circuit, and the cosine component of a carrier signal is added to the input of a second mixing circuit. The sine and cosine components of the carrier signal have 90 degrees to each other. The phase relationship 'is also called phase quadrature. A father

Page 5 1232031 V. Description of the invention (2) The generator is used to generate and add the sine and cosine components of the carrier signal to the first and second mixing circuits of the mixing circuit pair, respectively. This generates a so-called inphase (I) signal and a quadrature (QUadratlre) " Q " signal. The I and Q signals are then filtered and adjusted for gain, and finally transmitted to a digital signal processor chip to retrieve communication data. There are two sources of I and Q signal errors in this type of receiver. First, I and Q gain and phase errors are formed by the down-converter to the fundamental or intermediate frequency [F], which is due to the mixing circuit. The variation of the frequency-dependent I and Q gains and phase errors is due to the pass band of the channel filter. The error of this type is because the gain and phase are located between two orthogonal receivers after the down-conversion. Mismatch (for example: between the low-pass filters of I and q and between the gain control block of q). Therefore, the Q error that needs to be adjusted and corrected is: (IQ gain error (combined with the system and frequency (Relevant), (b) system's IQ phase error, and (c) frequency-dependent iq phase error. Previous techniques have used highly tolerable components in an attempt to avoid phase and / or peak imbalances between 丨 and 〇 components. (Imbalance). This scheme and There is a large cost impact and the problem may still not be positioned correctly. Li's previous technical solutions attempted to counteract the imbalance by predicting and removing this error. One of such solutions is described in US Patent No. 5,3 96,656. The case was awarded to Jasper et al. On May 7, 1995, entitled "A Method for Determining the Required Components of a Signal for Quadrature Modulation." This is shown in this prior art

Page 6 1232031 V. Description of the Invention (3) The first picture of the technique. Among them, a closed-loop feedback technique is used to continuously update the estimation of an unbalanced component to determine an error signal until the magnitude of the error signal is negligible. This prior art circuit includes standard components such as an antenna 301, a mixing circuit 302, an A / D converter 303, and a digital signal processing chip (DSP) 304. The DSP 304 includes mixing circuits 305 and 306 and a phase shifter 307. This signal is then added by an adder 3 08 and then low-pass filtered by components 30 9. The signal is then sampled by the sampler 31. The size of the components is estimated, and the imbalance of the I and q signals is determined by components 31 and 314. The final error correction procedure is completed by the desired component determiner 3 1 5 connected to Dsp. The disadvantage of this technology is that all the feedback components 3 1 0 ~ 3 1 5 must add additional components in addition to the necessary components in the I and Q receivers. This adversely affects the cost and increases the complexity of the device. And even with all this extra circuit components, the desired error compensation has not been fully realized. So 'traditional I and Q correction circuits rely on providing additional components to minimize errors. Other correction devices such as a separate pLL and vc are too expensive to provide in addition. Therefore, a solution is needed that takes into account the aforementioned problems and limitations of the quadrature imbalance correction circuit and does not require additional expensive circuits. 3. DISCLOSURE OF THE INVENTION ... This invention clearly generates a receiver calibration signal for measuring the errors commonly found in Q receivers. The invention then corrects the errors in the calibration mode. particular

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correct. The phase errors of the system of I and Q shunts are calibrated and corrected, and the gain errors of 1 and 0 are calibrated and the phase errors are calibrated and corrected. And the frequency phase is corrected.进 进 ίί 成 = 上 目 & ′ The present invention utilizes a digital signal processor to control the second order. An embodiment of the present invention includes HL, I and gain control devices included in the IQ circuit. This embodiment further includes a multiplier and a DSP and is used to determine a phase error between the chirped components. Tong Ming further provided several embodiments for the error calibration and correction of each type. For example, the system phase error can be corrected using a comparison table (100k_up table) or a digital signal processor trialer (iterativeiy) to correct the frequency-dependent phase error. A phase shifter or an all-pass (a 丨 i_pass) can also be used. ) Circuit correction. This invention provides a low-cost, reliable, on-chip method to take advantage of existing existing circuits to detect and correct all kinds of errors found in IQ quadrature receiver circuits. 4. Embodiment Figure 2 shows a preferred embodiment of the present invention. Figure 2 shows the communication device 1 〇 suitable for receiving and correcting! And (2 (in-phase and quadrature-phase) signals. The device 10 has two main parts, the path of the received signal and the signal path of the signal used for the received signal. In this embodiment, the received signal

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The $ control includes a low noise amplifier, two mixers, two and three, and two light amplifiers: valleyrs 14 and 15, and two filters 16 and 17. The final signal path includes gain amplifiers 18 and 19, and the received signals are input to the A / D converters 20 and 20 for processing by the digital signal processor 22. The mixed wave signal is generated by using the local oscillators 23 and 24, a phase locked loop 25 and 26, a phase shifter 27, and a mixed wave 28. ^ In the received signal path, LNA1 (11) is a low noise amplifier, usually used to amplify low power high frequency signals. The incoming RF signal and LNA1 come from an antenna (not shown). The received signal will use the mixing circuit M (12) and M2 (13) and the phase adjustment circuit? 1 (29) is divided into orthogonal formations. The outputs of Ml and M2 will become base band signals. For example, if the incoming signal has a bandwidth of 20MHz, each I and Q branch will be a signal with a bandwidth of 10mHz. For example, in a traditional orthogonal circuit, the capacitor sC1 & C2 (14 and 15) is used for The DC component of any received signal is blocked, and f 1 and F 2 (j 6 and 17) are used to further filter out unwanted signals. Before any quadrature modulation is performed, it is important that the receiver is accurately calibrated. To generate a reliable calibration tone (tone) in the mixed signal path, the local α 卩 oscillator l 1 (2 3) is mixed with a low-frequency fundamental frequency generated by L 2 (2 4). An example of this frequency would be L1 at 5GHz (Gigahertz) and L2 at 5MHz. The local oscillator L1 is also used in combination with a phase-locked loop PLL1 (25) and a filter F3 (26). These two signals are multiplied by a mixing circuit M4 (28). The resulting multiplication of two sine waves of different frequencies results in two signals, where

Ϊ232031 V. Description of the invention (6) The sine waves formed are at different frequencies. For example, cos (A) x cos (b) 2 + B ^ + C0S (^ B \. At this point, the mixer M4 generates two types of signals for calibration processing procedures. As mentioned earlier, it is important to distinguish -And λ ^ ^ ^ ^ No technology does not use this kind of circuit or signal for the purpose of generating signals. The standard prior art method uses only one base frequency for board alignment purposes, but the present invention uses two base frequencies. In this example, the frequency is 5GHZ + 5MHZ and 5GHZ-5MHZ. It should be noted that the dual side-band compressed carrier signal (DSBSC) can be coupled at the input of the LNA or the output of the lna to the RF of the receiver. .

These two kinds of calibration fundamental frequencies are fed to the mixers M1 and ... for orthogonal processing procedures. The use of two fundamental frequencies for calibration will present a problem for the prior art circuits. In this method, the in-phase shunt will be a clear signal but the quadrature phase will be zero. To overcome this difficulty, a phase shifter P2 is used. The phase shifter p2 adds an angle of 0 to the frequency of the calibration baseband signal. For example, when P2 is placed

Zero 'VI (t) is Cos (ot) and VQ (t) is zero. When P2 is set at 90 degrees, the VI (t) signal is not present and VQ (t) is ⑶ with ω1;). The calibration procedure using the phase shifter P2 (27) will be as follows. P2 is adjusted to obtain the maximum value of the signal at the VI (t) branch. The adjustment of P2 is performed by the digital signal processor chip (22). The maximum signal level is measured and stored by a base band processor chip 22. The maximum level of the Q branch is also measured and stored in the baseband processor chip 22. Once the maximum value of each of these shunts is known, the baseband processor chip performs a gain imbalance calibration. This gain imbalance calibration can be performed by amplifiers G1 and G2 (18 and 19) or at the fundamental frequency

Page 10 1232031 V. Description of the invention (7) The analog to digital signal converter (A / D) in the processor 22 is implemented. It should be noted that G1 and G2 can perform gain adjustment for the receiver together. It should also be noted that G1 and 〇2 are controlled together (as opposed to separate control). The I and Q gains are therefore made equal to avoid any sideband and distortion of the desired signal. The invention also allows the gain imbalance calibration to be performed by adjusting G1 and G2 at any level of gain. Regarding the calibration of the IQ phase error, P 2 should be set to a value to simply multiply the two signals together so that we can detect the relative phase of the I and Q branches. The product of this sine and cosine signals should be zero. The mixing circuit jj3 (31) completes the multiplication of the I and Q signals and outputs this signal to the filter F 4 (30). If this is not the case, it is assumed that the I and Q branches are not exactly 90 degrees as different phases as expected, and a phase error will occur. This signal is fed back to the phase shifter P1 via an amplifier and filter EF, and the phase shifter will compensate its error. Ideally, the phase difference between the I and Q branches should be 90 degrees. Therefore, with appropriate gain control adjustment P2 and adjustment P 1, an optimal phase imbalance treatment can be obtained. It should be noted that if p 1 is desired, it may be in the RF path instead of the local oscillator path. In a second embodiment, the phase shifter P2 can be used in another way of the above. In this embodiment, the phase shifter changes the phase shift angle quantitatively. For example, the angle Θ starts from zero and increases quantitatively. When the amount of phase shift changes, the in-phase and quadrature signals will change in magnitude (amp 1 it ude). At a certain 0 value, the rain signal all exists 6 and the other 0 values form only one of the two signals. As in the aforementioned embodiment, the peak value of each in-phase and quadrature signal is measured by the DSP crystal 22. This allows another method to detect the need for gain compensation

1232031 ----- 5. The maximum value of invention description (8). Fig. 3 of the present invention shows how an embodiment of the phase shifter 27 (as shown in Fig. 2) can be used. In addition to the actual phase shifting device 32, the device 27 for magnifying the field of view includes the following components: an amplifier 33, a feedback loop including: a force, a detector 34, a loop filter 35, and a gain amplifier. If the magnitude of Λ is critical in the calibration procedure, it is important that P2 does not modify the signal strength in phase f2. It must therefore be guaranteed that no gain or loss will be provided within any phase shifted one. In the present invention, the output has a certain size regardless of the phase shift. A limited or automatic gain control device γ is used to ensure its constant output voltage level. Figure 3 shows the use of a power detection (3 4) to determine the power of the calibration signal. The detected power is compared with a set value. If this signal has some kind of misalignment, an error signal is generated to compensate for this fact, a loop wave; ^ and: the loop gain amplifier 36 assists in keeping the output of all phase shift circuits constant. This allows P2 to output a signal value of a certain value as expected without adversely affecting the calibration process. In another preferred embodiment of the present invention, the systematic and frequency-dependent I Q gain and phase error within the receiver are calibrated using a circuit as shown in FIG. 4. The wireless transceiver in Fig. 4_ is similar to the one shown in Fig. 2 with two receiving signal paths and a mixing / calibration signal generating path. Receiving signal

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5. Description of the invention (9). The signal is sent through a low noise amplifier (LNA) 59 first. After passing through the LNA, the signal is coupled to the band-pass filter 58 by the switch 57. The downconverter 64 = 65 further processes the signal in the conventional manner to generate I and Q shunts. !! And 卩 $ are then filtered and amplified by components 66, 67, 70, and 71. The variable capacitors ^ and 69 are coupled with a conventional automatic gain control part of a receiver as a signal. All-pass network (a 11-pass) 72 and 74 are adjusted by one of the DSPs% Tiger 73 to ensure the correct phase relationship between the I and Q branches. The operation and control of an exemplary embodiment of an all-pass network of a phase error correction method and device will be described in detail below. For calibration procedures, a DSP 40 with an RF tone on the path of the transmitter is generated in the center of the receiver's pass band frequency. This is achieved by supplying a DC signal from the generator 44 to the FM inputs of the fundamental frequencies I and q of the transmitter. This RF fundamental frequency passes through a band-pass filter 51, a programmable phase shifter 53, and is then applied to a sine wave in a low-frequency Fbb multiplier 55. This generates a DSB-SC (double side band, suppressed carrier) modulation signal. fbb is the desired fundamental frequency, where the frequency-dependent IQ error calibration of the receiver is completed. For frequency-dependent 1 (3 errors, FBB is in an IEEE80 2. Ua WLAN wireless transceiver is in the range from 0Hz to about 8.5MHz. RF phase shifter 53 can be regarded as a "DSB-sc phase shifter", by It effectively changes the phase of the DSB-SC modulation signal to suppress the carrier. A variable gain control amplifier 5 4 ensures that the phase adjustment circuit 5 3 does not change its signal strength. The DSB-SC calibration signal generated by the DSP is then coupled by a coupling switch 5 Face

Page 13 V. Description of the invention (10) # ㈣ 机 before entering S frequency reduction.纟 After the frequency is reduced to the base frequency and the low-pass filtering is performed, the ί and ^ output signals of the receiver are at the ‘frequency’ because the local oscillator frequencies for the transmitter and receiver remain the same. ▲, the RF fundamental frequency of the transmitter is 5ίη (ωκι? 1 :), and the basis of the modulation with a fundamental frequency is Sin (6; BBT). After multiplication in the mixer 55, the signal of the DSB —% modulation Sin (0RFt) Sin (ωΒΒΐ). After that, the DSB-SC signal switch 57 is injected into the receiver's RF shunt, reduced to 1 and (3 fundamental frequency, low wave, and then appears at the output of the receiver with all the aforementioned JQ errors. Formula 1 and 2 describe the j-branch found in the circuit in Figure 4 with the error included. ~ I (t) = A (1 + AG / 2) Sin (ωΒΒΐ + Δ ^ BB / 2) Cos (6 > RF) (1) Q (t) = Α (1-AG / 2) Sin (ωΒΒΐ- Δ ^ > BB / 2) Sin (^ RF Δ ^ RF) A = constant △ G — fbb (including system and frequency dependent) IQ gain imbalance ~ error 1 0 ΒΒ = frequency-dependent fundamental frequency IQ frequency 0RF in the receiver at frequency Fbb — full integration in the calibration key path before injection into the receiver ) RF phase error, "? I2320TT V. Description of the invention (11) △ 9 RF = IQ phase error of the system in the receiver ωΒ = 2 7Γ Fbb The right receiver fundamental frequency IQ output is DC coupled to]) sp crystal square 4〇 之A / D, DC f-bit errors also need to be removed. This error can be averaged over the I and Q signals over a period exactly 1 / FBB. Use AC coupling when calibrating, _3dB car parent = the frequency is kept at least less than 10 times to ensure that any asymmetry and 0 path = ^ frequency shift away (r〇1 i-〇ff) asymmetry does not impact the IQ gain error. # 丄 In order to implement other embodiments of the present invention described later, a DC error 'is removed before the I Q gain error calibration is performed. sequence. Df ^^ n will use the formulas 1 and 2 listed above to realize its error I correction range error quasi-benefit imbalance calibration, refer to Figure 7, Figure 7 shows a gain error of 1 point and the way / the most \\ At step 702, DSP4 adjusts the DSB-SC phase shifter 53 so that: η Λ in this case, c0s) = ι, that is, at step 706; after the precise measurement of the branch-signal value ,

~) = 1, that is, two = In this case, the signal of Sin ('is then divided by DSP4R ^ D7 " / RF. At step 710, Q is the level of the two rms signals = relative to Fbb IQ gain imbalance = 2 IQ gain imbalance can be measured by ^^ "to ensure the value of 2: here and then mixed with the head sheep FBB in very small thousand two clear shape, after passing the frequency (for example, iEEE8〇2] la Page 151232031 V. Explanation of the invention (12) The average gain imbalance after passing 0 to 8MHz can also be 2. The IQ gain imbalance is covered by the DSP ^ A / D conversion =. T. This choice is relatively The time domain (time domain) is reduced by j ^ today, irrelevant to the frequency of the rain frequency. After this correction, it is reached at 8 4 ^ (negligible. After the long dagger correction, the M term of formulas 1 and 2 becomes meaty t When the gain is significantly changed, the IQ gain error prism needs to be made in the entire gain range of the receiver. Rabbits; ^ etch & ^ ncR or ^ In order not to overload the receiver, the voltage level of the injection must be adjusted with the base Increase of the frequency gain control === decrease y. Therefore, a programmable attenuator 75 is required to achieve the 2nd of the 8_Tor signal ^ can be achieved at the _ rate, but the better is still at the base Frequency, that is, 'base == signal Cos (WBBt) or Sin (the magnitude (ampiitude) can be η, however, when this magnitude becomes very small', the DC leakage current through the mixer's unadjusted fundamental frequency may become Significant and even larger than DSB-SC. J Good 'When the receiver is AC-coupled (capacitors 68 and 69), this unmodulated fundamental frequency becomes down-converted to 0Hz and has been removed. This guarantees the fundamental frequency of the receiver The shunt is not overloaded or saturated. ^ Once the gain is calibrated and corrected by the DSP 40, the 10 phase error calibration of the system can be performed in another embodiment of the present invention. Using the following techniques, the phase error calibration of the IQ system is not The choice of k in the pass frequency, that is, FBB does not need to be close to OHz. The appropriate Fbb is selected by DSP4 0 (such as the highest pass frequency of the low-pass filters 66 and 67)

Page 16 1232031 V. Invention description (half of (13)), and I Q gain calibration is done first using the frequency of the previous method. The IQ gain calibration signal is: I (t) = Sin (ωΒΒΐ + A qBB / 2) Cos (0RF) Q (t) = Sin (ωΒΒΐ-Δ (pBB / 2) Sin (0RF-Δ φπ) Refer to Figure 8 (A), Figure 8 (A) is the IQ phase error calibration flow chart. At step 802, the gain calibration is completed. At step 804, the 0RF (using the DSB-SC phase shifter 53) is converted to a range greater than 7Γ / 2 and Record the maximum I and Q rms voltage levels within this 0RF range.

LaxO ^ iASirK ωΒΒΐ + △ φΒΒ / 2) and < 9rf = 0 QmaxCt) = ASin (ωΒΒΐ- Δ φ ^ / 2)

After 0RF = 7r / 2 + A pRF, the two should be equal after gain calibration, that is, Imax (rms) = Qraax (rms) = A / / " 2 In step 806, adjust the DSB-SC phase shifter 53 so that I And the rms signal level of Q is equal at the same time and the corresponding rms voltage level is measured.

Cos (0rf) -Sin (9rf)-ΑΔ Prf (3)

P.171232031 V. Description of the invention (14) In step 8 08, the DSP should then use the maximum rms levels imax (rms) and (^ (rms), also gp A // " 2 normalization (normai ize) and q ·.

Inns / UxUmsXosC 0RF) ΑΔ 0RF

QnnS / Qmax (rms) = Sin (< 9rf-△ ~) = α △ pRF At step 810, the DSP uses the normalization level a △ 仏 f to find the corresponding IQ phase error in the comparison table. The comparison table is basically listed The solution of formula (3) should be stored in the internal memory of DSP40. In step 812, it is determined whether Imajrms) ~ Qmax (rms) is equal to A // ~ 2. If not, go back to step 504, adjust Θ RF ′ and repeat the calibration procedure. If yes, the calibration is complete. Another different scheme and embodiment are described below to achieve the correction of the system phase error by using Fig. 8 (B). To correct this, the receiver 41 should allow the system phase error a pRF to be adjusted to zero (the relative phase of the IQ is adjusted in the RF path or in the local oscillator path). When the system phase error is removed, △ p rf = 〇, and by formula (3) C 〇s (< 9RF)-Sin (< 9RF-△ pRF) = a △ pRF = 1 / / " 2 ( Exactly). △ Both PRF and 0RF are repeatedly adjusted by the DSP to obtain the pole by formula (3)

Page 18 Ϊ232031 、、 、 V. Description of the invention (15) " ~ "-Optimize the result of A △ pRF = 1 / / ~ 2 (exactly). Therefore, for the initial setting of △ pRF, first, in step 814, complete the gain calibration, and in step 816, adjust the standard tone of the DSB-SC phase shifter 53 (9RF makes the rms levels of 1 and Q equal and goes to step 81 8. Check whether formula (3) is exactly ΔΔφκρ = 1 / / 2. If step 820, change the value of ΔpRF in small steps and adjust DSB-sc phase shifter & gain to make the rms levels of I and Q equal. Finally, Step 822, check the public RF formula (3) to see if it is exactly A △ pRF = 1 / / 2. If not, repeat this procedure until exactly ΔΔρι ^ = 1 / 2. Using this method, the IQ phase error of the system can be determined by DSP40 is calibrated independently of the frequency-dependent IQ phase error. '' As described in the background of the invention, the frequency-dependent IQ phase error must also be calibrated and corrected. As implemented by another embodiment of the present invention, the frequency-dependent j Q phase error It can be calibrated in the way shown in Figure 8 (C). Since the filter error in the fundamental frequency paths 6 6 and 6 7 ϊ q phase error is calculated at the frequency FBB. For the fundamental frequency calibration in the transmitter sin (ωΒΒΐ) , In contrast, the received signal is ISin (t) = A (l + A G / 2) Sin (ωΒΒΐ + Δ (pBB / 2) Cos (0RF) QSin (t) = A (l ~ AG / 2) Sin (ωΒΒΐ- Δ < pBB / 2) Sin (0Rp-

I23203T V. Description of the invention (16) Where: A = constant △ G = unbalanced JQ gain in the receiver △ PBB = frequency-dependent fundamental frequency IQ phase error in receiver of ωΒΒ 0RF = in the calibration fundamental frequency path All (adjustable) RF phase shifts △ IRF phase error of the system in the PRF two receivers For Cos (t) of the fundamental tone of the transmitter's fundamental frequency calibration, the corresponding receiver signal is: IC0S (t) = A (l + AG / 2) Cos (ωΒΒΐ + Δ < ^ BB / 2) Cos (0RF) Qc〇s ^ t) ~ A (l- AG / 2) Cos (ωΒΒΐ- Δ ^ BB / 2) Sin ( 0RF- Δ φ ^) Calibration step 830 'First complete the gain calibration. In step 832, the DSP40 starts to adjust to approximately 7Γ / 4, and in step 83 4 so that

Cos (and Sin (△ ~)% 1 / (that is, j and ^ signals are roughly equal in size). Once this step is completed ', at step 836, a signal, 3111 ((^ 〇 calibrates the tone with the fundamental frequency in the transmitter) Transmission. At step 838, Dsp then captures the relative IQ §fl numbers as Isin (t) and Qsin (t). Then at step, dsp sends Cos (wBBt) as the fundamental frequency calibration tone in the transmitter and captures the relative

1232031 V. Description of the invention (17)-The I and Q signals are Icos (t) and Qcos (t), respectively, and remain constant (at approximately 7Γ / 4). Time (t) for these two cases is measured under different architectures, and t = 0, that is, the acquisition is started after the transmission fundamental frequency tone Sin (ωΒΒΐ) or Cos (ωΒΒΐ) in many cycles. Any transient interference in the receiver's low-pass filter ^ has been significantly attenuated. Calculate Isin (t) Qcqs (t)-IC () S (t) Qsin (t) by the captured signal DSP. It is better to pass any period of ωΒΒ to average out any noise. The following formula (4) represents this Error: ^ sin (^) Qc〇s (t)-Ic〇s (t) Qsin (t)

-Kl [Sin (ωΒΒΐ + △ pBB / 2) Cos (wBBt- Δ ρΒΒ / 2) -Cos (ωΒΒΐ + Δ (/ > BB / 2) Sin (ωΒΒΐ- Δ > Β / 2/2)] [Cos (^ RF) Sin (Δ φκρ)] = K2Sin (Δ 9BB) [Cos (0RF) Sin (0RF- Δ φκρ)] = K3Sin (Δ φΒΒ) which is constant and related to Δ pBB (4) DSP40 then step 844 , Adjust the Δ pBB in the receiver and minimize the | Isin (t) Qc〇s (t) _ Ic〇s (t) Qsin (t) calculated from the captured data.

So once the frequency dependent errors are calibrated, they can be corrected. Normally the frequency-dependent IQ phase error changes linearly with frequency, starting at 0 degrees at 0 Hz, and may reach a few degrees at the band edge. Most of this is due to the mismatch between the I and Q low-pass filters and the cutoff frequencies of the wave filter. Frequency dependent IQ phase error is fully adjustable in the I and q fundamental frequency signal path

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Network 72 and 74 corrections. This all-pass network will be under the control of DSp40. An example of an all-pass network is shown in Figure 5. This network includes resistors ri, R2, R3, and R4, W, a capacitor C1, and an operational amplifier. With this model, the network passes signals at all frequencies without gain changes. Although the use of capacitor C1 does introduce a slight phase shift at the signal output. This is what you want. Because of a relative phase mismatch, two such circuits can be introduced by setting the network at slightly different frequencies from each other. The frequency of this network (f 0-MHz) is defined as =, where R1 is ohm and 0 is microfarad. Creating a phase mismatch between all-pass networks allows IQ phase error compensation, as described below. The relative phase mismatch effects between such a network are shown in Figure 6 and are shown with various relative frequency mismatches. This figure shows a network centered at a normal value of 20 MHz. For example, between the two circuits, the mismatched dark frequency f 0_MHz value is 19 & 21MHz for the two networks. R1 and / or C1 of each j channel is adjusted to introduce a relative frequency mismatch at a particular FBB (see Figure 6) to form a specific Δ 丨 q phase mismatch. DSP40 adjusts the value of R1 and / or [丨 and minimizing the calculated from captured data in the receiver ’s all-pass network] Isin (t) Qcos (t)-lc〇s (t) Qsin (t) | . In this case, the frequency-dependent IQ relative phase error is corrected in the transmitter. Most errors that cover linear changes in the frequency range allow I and 卩 phase errors to be corrected. For example, if the I and q branches are 85 degrees out of phase, the all-pass, and cycle frequencies are adjusted by D S P 4 0 to provide an extra 5 degrees shift to provide true

1232031 V. Description of the invention (19) Positive orthogonal signal (that is, 90 divisions of one work, this naturally guarantees phase tantalum again. Moreover, when the fundamental frequency FBB operates at a lower frequency, the difference will be smaller at lower frequencies. The advantage of Zexingli L Wangtong Zhoulu is that they do not attract any frequency-dependent 1 Q imprint imbalances and are possessed by other circuits such as low-pass filters. Therefore, any phase error generated in the RF path can be fully pass by DSP40. The frequency adjustment of the circuits 72 and 74 is compensated. Therefore, the present invention automatically determines and corrects the system gain and phase error, and the frequency-dependent phase error common to the IQ orthogonal plough wireless transceiver. Because the present invention does not depart from its essence or The important features can be realized in many ways, and it should also be understood that the above embodiments are not limited by any of the above details, but should be broadly interpreted in their essence and field of vision as defined by the scope of patent applications, so all fall into the application Changes and modifications within the limits of the patent scope, or equivalent substitutions within the boundaries should be included in the scope of patent application of the present invention.

Page 23 Brief Description of Drawings 5 · Brief Description of Drawings · Figure 1 (prior art) shows a quadrature imbalance correction circuit. Figure 2 shows a circuit of the present invention. Figure 3 shows the phase shifter P2 as shown in Figure 2. FIG. 4 shows another embodiment of the present invention. Figure 5 shows an all-pass network that can be used in a preferred embodiment of the present invention. Figure 6 shows the phase-to-frequency comparison of this all-pass network. Figure 7 is the gain error calibration flowchart. ® Figure 8 is the I Q phase error calibration flowchart. Explanation of symbols: 1 〇 communication device 1 2, 1 3 mixer 16, 17 filter 20, 21 A / D converter 23, 24 local vibrator 2 6 filter 28 mixer 30 filter F4 32 phase shift Device 34 Power detector 36 Gain amplifier 11 Low noise amplifier W, 15 Coupling capacitor 1 8, 1 9 Gain amplifier 22 Digital signal processor 25 Phase-locked loop M phase shifter 29 Phase adjustment circuit pi 31 Mixing circuit M3 3 3 amplifiers 35 loop filters 4 DSP cubes

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Brief description of the diagram 41 receiver 43 D / A 4 5 low-pass crossing wave 47 switch 48 mixer 5 0 mixer 52 VGA + PA drive 5 4 variable gain control amplifier 5 7 switch 58 band-pass filter 60 PLL 62 oscillator 64 downconverter 6 6 low-pass filter 68 variable capacitor 70 amplifier 72 all-pass 74 all-pass 300 prior art circuit 3 0 1 antenna 303 A / D converter 3 0 5, 3 0 6 mixer circuit 3 0 8 adder 3 1 0 sampler

42 A / D 44 DC signal generator 4 6 Low-pass crossover 4 9 9 0 0 Phase shifter 5 1 Bandpass filter 5 3 Programmable phase shifter 5 5 Low-frequency FBB multiplier 59 Low noise amplifier (LNA) 61 Low-pass filter 63 Adjuster 6 5 Downconverter 6 7 Low-pass chirp 69 Variable capacitor 71 Amplifier 73 Adjust 75 Attenuator 3 0 2 Mixing circuit 3 0 4 Digital signal processor chip 307 Phase shifter 3 0 9 Low-pass filter 311 Attenuation component estimator

Page 25 1232031 Brief description of the diagram 312 Matching component estimator 313 First desired determiner 314 Unbalanced estimator 315 Desired component determiner

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Claims (1)

1232031 VI. Scope of patent application 1. A method for changing the phase error of signals received in the in-phase and quadrature components, including at least the following actions: Adjusting the in-phase components of the received signals The phase angle determines the amplitude of a peak (small); the phase angle of the positive component of the received signal is determined to adjust the phase angle of the in-phase and quadrature components of the received signal to set a large value; adjustment The first phase angle thus makes the received phase of the received phase of the yoke yue y in the same phase and quadrature components are 90 degrees out of phase. ^ 1 & X Μ 2 · As the method of the scope of the patent application Wherein, the second phase angle is adjusted by using a look-up table (10k-up table). 3. The mathematical solution of the formula (2) of the patent application scope. The third item of the patent scope is a digital signal processor chip book, in which the first phase w day and month is repeatedly adjusted. 5. If the input end face of the third patented noise amplifier of the patent scope is combined, the Fang Qu ’further includes the action on a low RF path. Double-sided ▼ Suppresses the plant wave signal to a receiver Page 27 · 1232031 VI. Scope of Patent Application 6 · —A communication device for correcting the imbalance between signals in the same phase and quadrature, at least: a first mixer (m 1 xer) for Multiplying the low frequency signal and high frequency signal to generate a side-band suppression carrier signal; a second and third mixer for generating in-phase and quadrature components of the received signal from the double sideband suppression carrier signal ; And a digital signal processor controls both cal ibration and correction modes for determining and correcting phase errors of signal paths within the communication device. 7. The communication device according to item 6 of the patent application scope, further comprising a means for coupling a double-sideband suppression signal to the RF path of the communication device at the input of a low-noise amplifier. 8. If the communication device of the patent application item 6 ^ ^ Se) & Q ((luadrature) signal phase is adjusted by a gain. 9 · If the patent application scope of the 8th processor changes the I and Q branch Signal 10 · If the ninth processor of the patent application scope is used as the communication device of the item after the calibration mode, the digital signal level is equal to each other. The communication device of the item, wherein the digital signal correction mode. ^ 23 ^ 31 VI. Scope of patent application " — π · If the communication device of the scope of patent application item 10, the digital signal processor accesses a lookup table to correct the phase error imbalance between the I and Q branch signals. 1 2 · If the communication device of the scope of patent application No. 10, the digital signal processor adjusts the phase difference between the I and Q branch signals trial and error until there is no phase error. 13. · A method for correcting the imbalance between the in-phase and quadrature components of the received message 5 tiger, including at least the following actions: Generate I and Q branch calibration signals, where the I branch signal is determined by I (t) = A (l + AGmSinC ωΒΒΪ + △ ^ / 2) (: 〇3 ('), and the Q branch signal is represented by Q (t) = A (l_ Δ0 / 2) 3ίη (ωΒΒί- △ hB / 2) Sin (~ Factory △ ~) represents; Change the gain of I and Q branches until △ 〇 = 〇; Change 0rf in the range greater than; r / 2 and record the maximum I and Q signal levels within this range of θκρ; Adjust the DSB-SC phase shift so! The signal level is exactly equal at the same time and the corresponding root mean square (rms) level is measured so that c0s (~) = sin (心 广 Δ Φρρ) = ΑΔ ^ > RF 'Look up the corresponding JQ in the table Phase error of measured A △ pRF △ PRF; and Page 29 1212031-VI. Patent Application Range The received signal has the same phase and quadrature component of 90 degrees. This is based on the phase error in the relative phase of the multi-movement relative phase stored in the lookup table. 14 · The method according to item 13 of the scope of patent application, wherein the signal is generated by a calibration tone (for example, a pair of sideband suppression M h knife path suppressed) carrier signal. i e band 15 · As in the method of claim 13 of the scope of patent application, the basin processor changes the gain of the I and Q branches. Digital signal bluffing \ 6. If the method of the scope of the patent application is No. 13, one of the digital signal processors controls a phase shifter to change θκρ 〇 As the method of the scope of the patent application No. 16, one of the digital signal processing benefits A second phase shifter is adjusted by the amount determined by the lookup table to adjust ΔM. 18 · —A kind of wireless transceiver, including at least an antenna; a positive father receiver for receiving a signal and converting the received signal into an in-phase base band and an orthogonal base frequency signal; a digital signal processing The device is used to perform the following tasks; decide to test the signal in-phase and the imbalance between the quadrature signals under different conditions in the quadrature receiver; Conditions; and adding one or more correction factors to the phase and quadrature fundamental frequency signals between subsequent receptions to minimize the imbalance between the subsequent phase reception and quadrature fundamental frequency signals according to a current condition. 19. The wireless transceiver of item 18 in the scope of patent application, wherein one of the changing conditions is a changing gain of a baseband signal. 20. The wireless transceiver according to item 19 of the patent application scope, wherein one of the changing conditions is changing the phase relationship between the fundamental frequency signals. Page 31