1231097 玖、發明說明： 【發明所屬之技術領域】 本發明係有關於一種頻率人+壯职 剌田„.. 旱^成裝置及方法，特別是有關於 利用一延遲線振盪器，配合 ^ ^, 直接數位合成技術和相鎖迴路來達 到南解析、低相位雜訊的一種頻 、手口成衣置和頻率合成方法。 【先前技術】 ㈣-些寬頻帶粗調頻率合成輸出為達到高解析、低相位 ::之特性’㊉以多個低雜訊、窄頻帶電壓控制振盪器(v⑶) 、刀換除了木構複雜外，並需使用相鎖迴路（pll)控制每一 頻率源來達到頻率精準。 般而a ’低相位雜訊頻率合成裝置之電路架構如下：^ 才^貞迴路+低相位雜訊輸出之電壓控制振盡器，2·低相位雜訊參 頻率源+見頻相鎖迴路，以達到抑制輸出電壓控制振盈器之相 位雜訊。帛1圖表示習知之頻率合成裝置之方塊圖，如第i圖 所不’頻率合成裝置包括直接數位合成器3G、混波器⑽、可程 式除法為2G、第-低通濾波器5G、第二低通濾波器刚、第一 =位k心4G、第：相位檢測器9()、電壓控制振6〇、除頻 器曰1 ίο卩及電壓控制振盈模組12〇。其中；相位雜訊的抑制方 法疋以參考頻率源電壓控制振盪模組為關鍵，電壓控制振盈模 組之需求為-寬頻、高頻率、以及低相位雜訊，然❿，一般以 單-個電壓控制振盪並不易達成，而需要多個電壓控 來構成多個頻段組合，而具有寬頻、高頻率、以及低相位雜訊 =能之電壓控制振|模組12G ’並配合由直接數位合成器ι〇、 此波态80、可程式除法器2〇、第一低通濾波器5〇、第二低通濾 波器1〇〇、第一相位檢測器4〇、第二相位檢測器9〇、電壓控制 1231097 器6〇、以及除頻器110所構成之迴路，達到頻率合成及抑 制相位㈣的功能，然而；此電路架構複雜且由多個電壓 振器所組成之電壓控制振盪模έ 12 到上述功能。 ⑶於❹上需經切換才可達 因此，為了簡化電路架構及降低成本，於高頻跳頻之頻率 5成輸出運用上’本發明使用單—振以（以高q值和延遲線為 共振腔），配合直接數位合成技術和相鎖迴路來達到高解析、低 相位雜訊之頻率合成輸出，更可改善電壓控制振盈器本身之相 位雜訊問題，由於架構簡單、容易實現，於模組化後可廣泛應 用於各種需要頻率合成輸出之裝置，更具有經㈣益。、〜 【發明内容】 有鑑於此’本發明主要目的係為提供—種頻率合成裝置和 員率成方法’利用一延遲線振虚器，配合直接數位合成技術 達到高解析、低相位雜訊的-種頻率合成裝置和 為達到上述目的，本發明提出一種頻率合成裝置，包括一 輸入端用以接收一給人^士妹 堆 ^ 輸入唬、一弟一壓控振盪器輸出對應一第 頻第—信號（S|)，第-頻率係依據第—壓控振盈器所接 接控㈣號的電a位準而變化、—可程式除法器麵 出一：頻吕二卢：以將第一信號之第-頻率除以一特定倍數而輸 <5號N,、—直接數位合成器依據輸人信號，產生一對 參考頻率的參考信號SR、一第-相位檢測器將 =頻W與參考信號進行相位之比較，並產生對應於兩者相位 ，之第—控制信號C2、一第一低通濾波器耦接第二控制信 I，用以濾除高頻成分並且將第二控制信號輸出。 1231097 -第二壓控振盪器耦接第二控制信號，輪 T第二亀)，第二頻率係依據第二控制信號的;上 、二，«器用以產生步階共振信^叫並輸出其 中之，v 振分別對應步階共振頻率（fI〜fn)，共振頻率 彼此間具有既定之頻率間隔作«〇、_混波器用以將第一信 號和延遲線振1器所輸出之共振信號進行混波，而產生一混波 信號M,、-第二相位檢測器將混波信號與第二信號進行相:之 比較’並產生對應於兩者相位差之信號，作為第—控制信號 -第二低通濾波器耦接第一控制信號’用以濾除高頻成分U並將 第-控制信號輸出至第一壓控振盈器’使第一壓控㈣器依據 弟-控制信號之電壓位準而調整第一頻率，並壓制第一信號的 相位雜訊。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下 文特舉若干實施例，並配合所附圖式，做詳細說明如下。 【實施方式】 實施例一： 第2圖表示本發明之第一實施例頻率合成裝置之方塊圖， 如第2圖所示，頻率合成裝置包括一輸入端In、一第一壓控振 盪器10、一可程式除法器20、一直接數位合成器3〇、一第一相 位檢測器40、一第一低通濾波器50、一第二壓控振盪器60、一 延遲線振盪70、一混波器80、一第二相位檢測器9〇、以及一 第一低通〉慮波裔10 0。 本實施例頻率合成裝置之工作原理如下所述。輸入端L用 以接收一輸入信號Ii、第一壓控振盪器10(高頻壓控振盪器）輸 出對應一第一頻率fHB之一第一信號S1，第一頻率fHB係依據第 1231097 一壓控振1器ίο所接收之—第—控制信號匕的電壓位準而變 化、可程式除法器2G Μ接第—信號&，用以將第—信號^之 第一頻率fHB除以-特定倍數而輪出—除頻信號％、直接數位 合成器30依據輸入信號In，產生_對應除頻信號&之一 頻率的參考信號〜、第一相位檢測器4〇將除頻信號&財考 以SR進行相位之比較’並產生對應於兩者相位差之—第二於 制信號c2、第-低通渡波器5〇輕接第二控制信號c2,用以^ 除雜汛並且將第二控制信號C2輸出。 心 C2輸出一對應一第二頻率fLB之第二信號S2,第二頻 依據第二控制作·获rf茂 lb糸 第一眚" 2的電尾位準而變化，第3圖表示本發明之 =魏例延遲線振盈器之電路圖，如第3圖所示，延遲線振 盪窃70包括一考畢子（colpitts)振盪器7〇2 、’ 、 產生步階共振信號fstep並輸出其中：一，*中二 7〇2包括—電晶體。、一電容c耦接在電晶體 : ;L 〇 間、一電感"麵接在電晶體㈣-端和 _ 1之控制ii而之間 '以及一壓變電容vc耦 之控制端和電晶，n 势 電日日體Q】 體Q,之控二:： 間，而延遲線7°4耗接在電晶 控電源〜_電晶體一^ 一，步階址振作;\ 、產生步产白共振信號fstep並輸出其中之 第4圖所ΐ ΓΓ 麟㈣㈣^㈣關率圖，如 乐Ώ所不’共振頻率彼此間具有既定 頻率間隔（fWn_fn ,)大體介於 4MHz〜8MHz。日，Mfs =fn-fn·,)， 第5圖表示本發明之第一實施例延遲線之示意圖，如第5 1231097 圖所示延遲線（共振腔）之阻抗&為無限大、 波傳播速度、A :波長，則共振腔長度L·之運算式如下： 共振腔長度·· Ζ = „χ；ι/2 延遲時間：r = Z/v 並聯共振頻率：y^v/A^xvQL 共振頻率間隔 jfs :乂=乂+1-乂 =ν/2Ι；=：1/27Γ 如上述之運算式，則可經由共振頻率間隔而決定該共振 之長度L 〇 心、又 再請參照第2圖，混波器80用以將第一信號\和延遲線 振盈器70所輸出之步階共振信號^其中之一進行混波，而產 生一混波信號Mi、第二相位檢測器9〇將混波信號馗1與第二俨 唬S2進行相位之比較，並產生對應於兩者相位差之信號，作為 第一控制信號、第二低通濾波器100耦接第一控制信號Ci， 用以濾除雜訊並將第一控制信號Ci輸出至第一壓控振盪器 1 〇使第一壓控振盪器1 〇依據第一控制信號c!之電壓位準= 调整第一頻率fHB，並壓制第一信號S1的相位雜訊。 其中，第一壓控振盪器10、第二壓控振盪器60、延遲線 振盪1§ 70、混波器80、第二相位檢測器9〇、以及一第二低通濾 波裔1〇〇係構成一第一相鎖迴路PLL1(頻寬較大），而可程式除 法器20、直接數位合成器3〇、第一相位檢測器4〇、以及第一低 通滤波器、50係配合第-相鎖迴路pLL1而構成一第二相鎖迴路 PLL2(頻寬較小），且於第一相鎖迴路pLL1中第一頻率“於回 授後之結果係等於步階共振信號匕邮和第二頻率f⑶之和 (fHB=fstep+fLB);因步階共振信?虎匕叫以及第二頻率U之頻率為 低相位雜汛且比中第一頻率之相位雜訊低很多，所以第二 壓控振盪器10之相位雜訊可達到抑制改善之目的(於第一相鎖 1231097 坦路PLL1頻見内)。而第二相鎖迴路pLL2中 授後之結果係與參考錢Sr(高解析精確頻率源）之頻率== 倍關係(依除數而定)，所以第—壓控振盪器ι〇之頻率&可達 到高解析精確頻率之目。 第6圖表示本發明之第一實施例頻率合成裝置之相位雜訊 抑制圖、’如第Μ圖所示’可得知本發明使用延遲線振盈器％， 在第-迴路頻寬BW1和第二迴路頻寬BW2之間，比習知電麼 控制振盪器模組120更具有良好的相位雜訊抑制能力。 實施例二： 本貫施例為應用上述頻率合成裝置進行頻率合成之方 法，其圖㈣明參照第2圖，頻率合成方法方法包括如下步驟·· 由第壓控振盪器丨〇(高頻壓控振盪器）產生對應一第一頻率 fHB之一第一信號S1，第一頻率fHB係依據第一壓控振盪器10 所接數之第一控制k號C!的電壓位準而變化，將第一信號Si 麵接至了私式除法态20，用以將第一信號s丨之第一頻率 除以一特定倍數而得出一除頻信號Νι，提供一輸入信號&、使 用一直接數位合成器3〇依據輸入信號In，產生一對應一參考頻 率之參考#唬SR，透過一第一相位檢測器4〇，將除頻信號Νι 與參考信號SR進行相位之比較並產生對應於兩者相位差之一第 一控制k號C2， 將上述第二控制信號c2耦接至一第一低通 濾波器50,用以濾除雜訊並由第一低通濾波器5〇將第二控制信 號輸出。 將上述第二控制信號C2耦接至一第二壓控振盪器60(低頻 壓控振盪器），以輸出一對應一第二頻率fLB之第二信號S2，第 二頻率fLB係依據第二控制信號C2的電壓位準而變化，使用一 延遲線振盪器70用以產生步階共振信號並輸出其中之一， 1231097 ，分別對應步階共振頻率fi〜fn’共振頻率彼此 線：盪-二之頻率間隔I D，將第一信號S|和上述延遲 所輸出之步階共振信號〔“中之—進㈣ 4:;: :ΓΓΜι’透過一第二相位檢測器90將混波信號％ 於，：：2進行相位之比較，並產生對應於兩者相位差之信 虎作為弟一控制信號（^。 除雜控制信號C1㈣至—第二低通渡波11⑽，用以渡 二並將弟—控制信號Cl輸出至第-壓控振盪器10,使第一 :纖盈器1。依據第一控制信號Cl之電壓位準而調二 率fHB，並壓制第一信號S1的相位雜訊。 如上述之實施例可知本發明較習知具有 較使用多段電塵控制振盈器和延遲線振盡器之結果炎如表= 不 · — -------- 方式 1--也- 頻率需求 j_ 特性 習知技術 多段電壓 精準 架構複雜 控制振蘯 且多段電 器組成迴 壓控制振 路 盪器需切 — 一_ 換 本發明 延遲線振 穩定 ------— 架構簡 盪器 單、採用單 一電壓控 制振盪器 Q值 中 (30 〜40) (200〜3〇〇) 12 1231097 圍内，當可做更動和潤飾，因此本發明之保護範圍當視後附之 申請專利範圍所界定者為準。1231097 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a kind of frequency person + strong job field… .. Drying device and method, especially about using a delay line oscillator to cooperate with ^ ^ , Direct digital synthesis technology and phase-locked loop to achieve south resolution, low phase noise, a frequency, hand-to-mouth clothing placement and frequency synthesis method. [Previous technology]-Some wide-band coarse-tuned frequency synthesis output is to achieve high resolution, low Phase :: Features' ㊉ In addition to multiple low noise, narrow-band voltage controlled oscillators (v⑶), knife replacement, in addition to complex wooden structures, and the use of phase-locked loop (pll) to control each frequency source to achieve frequency accuracy The general circuit structure of a 'low-phase noise frequency synthesizer is as follows: ^ Cai ^ Zhen circuit + low-phase noise output voltage control oscillator, 2. Low-phase noise reference frequency source + frequency phase-locked loop In order to achieve the suppression of the phase noise of the output voltage control oscillator, Figure 1 shows a block diagram of a conventional frequency synthesizer. As shown in Figure i, the frequency synthesizer includes a direct digital synthesizer 3G, a mixer ⑽, Programmable division is 2G, the first low-pass filter 5G, the second low-pass filter just, the first = bit k center 4G, the first: phase detector 9 (), voltage control oscillator 60, frequency divider 1 ίο 卩 and voltage-controlled vibration surplus module 12. Among them, the phase noise suppression method is based on the reference frequency source voltage-controlled oscillation module as the key. The requirements of voltage-controlled vibration surplus module are-broadband, high frequency, and low Phase noise, of course, is generally difficult to achieve with a single voltage-controlled oscillation, and requires multiple voltage controls to form multiple frequency band combinations, and has wide-band, high-frequency, and low-phase noise = capable voltage-controlled oscillation | Module 12G 'and cooperate with direct digital synthesizer ι〇, this wave state 80, programmable divider 20, first low-pass filter 50, second low-pass filter 100, first phase detection The circuit formed by the detector 40, the second phase detector 90, the voltage control 1231097, and the frequency divider 110 achieves the functions of frequency synthesis and suppression of phase chirp. However, this circuit structure is complex and consists of multiple voltages. Voltage controlled oscillation mode composed of vibrator 12 to up Function. (3) It can be reached by switching on ❹. Therefore, in order to simplify the circuit structure and reduce the cost, 50% of the frequency of the high frequency hopping output is used. The present invention uses single-vibration (with a high q value and a delay line). (Resonant cavity), combined with direct digital synthesis technology and phase-locked loop to achieve high-resolution, low-phase noise frequency synthesis output, can further improve the phase noise problem of the voltage control oscillator itself, because the structure is simple and easy to implement, After modularization, it can be widely used in various devices that require frequency synthesis output, and it is more beneficial. [Summary of the Invention] In view of this, the main purpose of the present invention is to provide a frequency synthesis device and a staffing method. 'Using a delay line vibrator, combined with direct digital synthesis technology, to achieve a high-resolution, low-phase noise-a frequency synthesis device and in order to achieve the above purpose, the present invention proposes a frequency synthesis device including an input terminal for receiving a Give people ^ Shimei heap ^ input, one brother, one voltage-controlled oscillator output corresponds to a first frequency-signal (S |), the first frequency is based on the first voltage-controlled oscillator The level of the electrical a of the connected control signal changes,-a programmable divider shows one: frequency Lu Erlu: to divide the-frequency of the first signal by a specific multiple and enter < 5 number N, ——— The direct digital synthesizer generates a pair of reference frequency reference signals SR according to the input signal. A phase detector compares the phase of the frequency W with the reference signal and generates a phase corresponding to the two. The control signal C2 and a first low-pass filter are coupled to the second control signal I to filter out high-frequency components and output the second control signal. 1231097-The second voltage-controlled oscillator is coupled to the second control signal, wheel T is the second one), the second frequency is based on the second control signal; upper and second, «is used to generate step resonance signals and output them In other words, the v vibrations respectively correspond to the step resonance frequencies (fI ~ fn), and the resonance frequencies have a predetermined frequency interval between each other as «〇, _ the mixer is used to perform the first signal and the resonance signal output from the delay line oscillator 1 The second phase detector generates a mixed signal M, and the second phase detector compares the mixed signal with the second signal: and generates a signal corresponding to the phase difference between the two, as a first control signal Two low-pass filters are coupled to the first control signal 'to filter out the high-frequency component U and output the -control signal to the first voltage-controlled oscillator', so that the first voltage-controlled amplifier is based on the voltage of the -control signal Level to adjust the first frequency and suppress the phase noise of the first signal. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, several embodiments are given below and described in detail with reference to the accompanying drawings. [Embodiment] Example 1: FIG. 2 shows a block diagram of a frequency synthesizing device according to the first embodiment of the present invention. As shown in FIG. 2, the frequency synthesizing device includes an input terminal In and a first voltage-controlled oscillator 10. , A programmable divider 20, a direct digital synthesizer 30, a first phase detector 40, a first low-pass filter 50, a second voltage controlled oscillator 60, a delay line oscillation 70, a hybrid A waver 80, a second phase detector 90, and a first low-pass filter 100. The working principle of the frequency synthesizing device of this embodiment is as follows. The input terminal L is used to receive an input signal Ii, and the first voltage-controlled oscillator 10 (high-frequency voltage-controlled oscillator) outputs a first signal S1 corresponding to a first frequency fHB. The first frequency fHB is a voltage according to 1231097. The voltage level of the first control signal received by the vibrator 1 is changed, and the programmable divider 2G is connected to the first signal & to divide the first frequency fHB of the first signal ^ -specific Multiples are rotated out—the frequency division signal%, the direct digital synthesizer 30 generates a reference signal corresponding to one of the frequency division signals & according to the input signal In, the first phase detector 40 will divide the frequency division signals & Calculate the phase comparison with SR 'and generate the phase difference corresponding to the two—the second control signal c2, the first-low pass wave waver 50, and then lightly connect the second control signal c2 to remove miscellaneous floods and change the first Two control signals C2 are output. The heart C2 outputs a second signal S2 corresponding to a second frequency fLB, and the second frequency changes according to the second control operation to obtain the electrical tail level of rfma lb 糸 first 眚 " 2. FIG. 3 shows the present invention Zhi = Wei Example circuit diagram of the delay line oscillator, as shown in Figure 3, the delay line oscillator 70 includes a colpitts oscillator 702, ', generates a step resonance signal fstep and outputs it: One, * 2, 2702 includes-transistor. A capacitor c is coupled to the transistor: L0, an inductor " is connected between the 和 -terminal of the transistor and the control ii of _1 ', and a control terminal of the voltage-varying capacitor vc and the transistor , N potential electric day solar body Q] body Q, control two :: time, and the delay line 7 ° 4 is connected to the power of the transistor control ~ _ transistor one ^ one, the step site vibrates; \, produces step production white fstep resonance signals and outputs of which 4 to FIG ΐ ΓΓ lin ^ iv ㈣㈣ FIG clearance rate, are not as music Ώ 'resonant frequency with each other having a predetermined frequency interval (fWn_fn,) substantially between 4MHz~8MHz. Mfs = fn-fn ·,), Figure 5 shows a schematic diagram of the delay line of the first embodiment of the present invention, as shown in Figure 5 1231097, the impedance of the delay line (resonant cavity) & is infinite, wave propagation Velocity, A: Wavelength, the formula of the cavity length L · is as follows: Cavity length ·· Z = „χ; ι / 2 Delay time: r = Z / v Parallel resonance frequency: y ^ v / A ^ xvQL resonance Frequency interval jfs: 乂 = 乂 + 1- 乂 = ν / 2Ι; =: 1 / 27Γ As the above expression, the resonance frequency interval can be used to determine the length of the resonance L 〇 center, please refer to Figure 2 again The mixer 80 is used to mix one of the first signal \ and the step resonance signal ^ output by the delay line oscillator 70 to generate a mixed signal Mi, and the second phase detector 90 will The phase of the mixed signal 俨 1 is compared with the second bleed S2, and a signal corresponding to the phase difference between the two is generated. As a first control signal, the second low-pass filter 100 is coupled to the first control signal Ci for Filter out noise and output the first control signal Ci to the first voltage-controlled oscillator 1 〇 Make the first voltage-controlled oscillator 1 〇 According to the first control signal The voltage level of No. c! = Adjust the first frequency fHB and suppress the phase noise of the first signal S1. Among them, the first voltage controlled oscillator 10, the second voltage controlled oscillator 60, the delay line oscillation 1§ 70, The mixer 80, the second phase detector 90, and a second low-pass filter 100 constitute a first phase-locked loop PLL1 (larger bandwidth), and a programmable divider 20 and direct digital synthesis The first phase detector 40, the first phase detector 40, and the first low-pass filter 50, together with the first phase-locked loop pLL1, form a second phase-locked loop PLL2 (with a smaller bandwidth), and The result of the first frequency in the lock loop pLL1 after feedback is equal to the sum of the step resonance signal and the second frequency f⑶ (fHB = fstep + fLB); The frequency of U is low phase noise and is much lower than the phase noise of the first frequency, so the phase noise of the second voltage controlled oscillator 10 can achieve the purpose of suppression and improvement (at the first phase lock 1231097 Tanlu PLL1 frequency See inside). The result of the second phase-locked loop pLL2 is related to the frequency of the reference money Sr (high-resolution accurate frequency source) == multiple (depending on the divisor), so the frequency of the first voltage-controlled oscillator ι〇 & Can achieve the goal of high resolution and accurate frequency. Fig. 6 shows a phase noise suppression diagram of the frequency synthesizing device according to the first embodiment of the present invention, and "as shown in Fig. M", it can be learned that the present invention uses a delay line oscillator% in the first-loop bandwidth BW1 and Between the second loop bandwidth BW2, the phase noise suppression capability is better than that of the conventional electronic control oscillator module 120. Second Embodiment: This embodiment is a method for applying frequency synthesizing device to synthesize frequency. The figure is shown in Fig. 2. The frequency synthesizing method includes the following steps. Control oscillator) to generate a first signal S1 corresponding to a first frequency fHB, the first frequency fHB is changed according to the voltage level of the first control k number C! The first signal Si is connected to the private division state 20, which is used to divide the first frequency of the first signal s 丨 by a specific multiple to obtain a divided signal Nι, provide an input signal & use a direct The digital synthesizer 30 generates a reference #SR corresponding to a reference frequency according to the input signal In, and compares the phase of the frequency-reduction signal No with the reference signal SR through a first phase detector 40 and generates a signal corresponding to two The first control k number C2 is one of the phase differences, and the second control signal c2 is coupled to a first low-pass filter 50 for filtering noise and the second low-pass filter 50 Control signal output. The second control signal C2 is coupled to a second voltage-controlled oscillator 60 (low-frequency voltage-controlled oscillator) to output a second signal S2 corresponding to a second frequency fLB. The second frequency fLB is based on the second control. The voltage level of the signal C2 changes. A delay line oscillator 70 is used to generate a step resonance signal and output one of them, 1231097, which correspond to the step resonance frequencies fi ~ fn ', respectively. The frequency interval ID combines the first signal S | and the step resonance signal outputted by the above delay [“中 之 — 进 ㈣ 4:; :: ΓΓΜι ′” to pass the mixed signal through a second phase detector 90%: : 2 compares the phases and generates a trustworthy tiger corresponding to the phase difference between them as the control signal of the brother (^. The decontamination control signal C1㈣ to-the second low-pass crossing wave 11⑽, used to cross the brother and the control signal Cl Output to the first voltage-controlled oscillator 10, so that the first: slimmer 1. Adjust the second rate fHB according to the voltage level of the first control signal C1 and suppress the phase noise of the first signal S1. Examples show that the present invention is more familiar The results of the vibration suppressor and delay line exhaustor are shown in the following table: No. — -------- Method 1-Also-Frequency Requirement j_ Characteristics Known Technology Multi-Stage Voltage Precision Architecture Complex Control Vibration and Multi-Stage The components of the electrical circuit for the back-pressure control oscillator need to be switched-one _ for the delay line vibration stability of the present invention ------- simple structure of the oscillator, using a single voltage control oscillator Q value (30 ~ 40) (200 ~~ 〇〇〇) 12 1231097, can be modified and retouched, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.
13 1231097 【圖式簡單說明】 第 斤…不口之頻率合成裝置之方塊圖 第2圖表示本發明之第一者 第3圖表示本發明之第—舍:歹’貝率合成裝置之方塊圖。 第4圖表示本發明之第例延遲線振盛器之電路圖。 點頻率圖。 A硫例延遲線振盪器輸出之共振 第5圖表示本發明之第_ 第6圖表示本發明之第— 抑制圖。 實施例延遲線之示 貫施例頻率合成裝 意圖。 置之相位雜訊 【符號說明】 10〜第一壓控振盪器， 20〜可程式除法器， 30〜直接數位合成器， 40〜第一相位檢測器， 50〜第一低通濾波器， 60〜第二壓控振盪器， 70〜延遲線振盪器， 702〜考畢子振盪器， 704〜延遲線， 80〜混波器，13 1231097 [Brief description of the diagram] The block diagram of the frequency synthesizer of the second pound ... The second diagram shows the first person of the present invention. The third diagram shows the first embodiment of the present invention. . Fig. 4 shows a circuit diagram of a delay line vibrator according to a first example of the present invention. Dot frequency graph. A Sulfur Example Resonance of Delay Line Oscillator Output Figure 5 shows the _th part of the present invention. Figure 6 shows the 2nd-the suppression graph of the present invention. The delay line of the embodiment is shown in the embodiment. Phase Noise [Symbol Description] 10 ~ First Voltage Controlled Oscillator, 20 ~ Programmable Divider, 30 ~ Direct Digital Synthesizer, 40 ~ First Phase Detector, 50 ~ First Low Pass Filter, 60 ~ Second Voltage Controlled Oscillator, 70 ~ Delay Line Oscillator, 702 ~ Kobe Sub Oscillator, 704 ~ Delay Line, 80 ~ Mixer,
90〜第二相位檢測器， 100〜第二低通濾波器， 110〜除法器， 12〜電壓控制振盡模組、 In〜輸入端， I!〜輸入信號， 14 1231097 ΪΗΒ〜第一頻率， fLB〜第二頻率，90 ~ second phase detector, 100 ~ second low-pass filter, 110 ~ divider, 12 ~ voltage control exhaustion module, In ~ input, I! ~ Input signal, 14 1231097 ΪΗΒ ~ first frequency, fLB ~ second frequency,
Si〜第一信號， s2〜第二信號， sR〜參考信號， 〜第一控制信號， c2〜第二控制信號， fstep〜步階共振信號’ fi-fn〜步階共振頻率信號’ fs〜頻率間隔，Si ~ first signal, s2 ~ second signal, sR ~ reference signal, ~ first control signal, c2 ~ second control signal, fstep ~ step resonance signal 'fi-fn ~ step resonance frequency signal' fs ~ frequency interval,
Mi〜混波信號，Mi ~ mixed signal,
Ni〜除頻信號， L〜電感’ C〜電容， VC〜可變電容，Ni ~ frequency-divided signal, L ~ inductance ’C ~ capacitor, VC ~ variable capacitor,
Qi〜電晶體’ R〜電阻， VIN〜輸入電壓， PLL1〜第一相鎖迴路， PLL2〜第二相鎖迴路， GND〜接地端， BW1〜第一迴路頻寬， BW2〜第二迴路頻寬。Qi ~ transistor 'R ~ resistor, VIN ~ input voltage, PLL1 ~ first phase locked loop, PLL2 ~ second phase locked loop, GND ~ ground, BW1 ~ first loop bandwidth, BW2 ~ second loop bandwidth .