TWI229913B - Test feature and test method thereof - Google Patents

Abstract

A test feature is disclosed, which is disposed in the scribe line region of the wafer to detect the overlay offset between the conductive plug and the conductive layer in the feature region. It comprises: an active area disposed in the said scribe line region; a first and a second T-shaped conductive layers disposed in the aforementioned scribe line region symmetrically, each has a first, second, and third ends; a first to third conductive bonding pad disposed at the first, second and third ends of the first T-shaped conductive layer, so as to test the first electrical characteristics; a fourth to sixth conductive bonding pad disposed at the first, second and third ends of the second T-shaped conductive layer, so as to test the second electrical characteristics. From the aforementioned first and second electrical characteristics, the overlay offset between the conductive plug and the conductive layer in the feature region is determined.

Description

1229913 Amendment P--Case No. 123695 Ning Wu, Invention (1) " '-[Technical Field of Invention] The invention relates to a semiconductor element, and in particular, to a conductive plug and a conductive layer in a cattle region. The heavy test and its test method. [Previous technology] In the semi-volume circuit, generally, there are many TG parts (f ea tur e), and these components and structures are gradually defined using photolithorgraphy. To match various process technologies, such as engraving, oxidation process, silicon oxide deposition, metal deposition, etc. Once the position of each component area is defined by lithography technology, good alignment and control of the critical dimensions of the circuit have a significant impact on the yield of the product. Therefore, in the process technology of the integrated semiconductor integrated circuit, it is an important issue to check with the process steps to check whether the components in it have an unexpected overlap phenomenon. For example, in the memory system, the metal layer ㈣ and the semiconductor element 14 are electrically connected through a bit line plug CB, as shown in FIG. 1. However, the alignment between the right metal layer M 0 and the bit line plug CB will cause an offset, which will cause the semiconductor device 14 to behave abnormally, or cause an open circuit between the semiconductor device 14 and the metal layer M0, making memory Cells cannot operate normally 0 [Summary of the Invention] In view of this, the primary purpose of the present invention is to provide a detection

1229913 Π7-—t. Q919 董 __Year Month Day Amendment V. Description of the Invention (2) One One ^ $ Test element for overlapping offset between the plug base and the conductive layer, and the way to proceed by it. The test element of the present invention can be arranged on a dicing track to monitor the degree of overlap and offset between the main conductive plug and the conductive layer simultaneously. ^ In order to achieve the above-mentioned object, the present invention provides a test element for measuring the offset of the conductive plug and the second gate of the second gate. The test element can be disposed on a cut area of a semiconductor wafer. The above-mentioned test element includes: an active area, It is arranged in the cutting area; a first and a second zigzag conductive layer are symmetrically arranged in the cutting area, each having a first, a second and a third end; a first to a second conductive bonding pad, The first, first, and second ends of the first T-shaped conductive layer are respectively disposed to measure a first electrical characteristic; and the fourth to sixth conductive bonding pads are respectively provided in the second T-shaped Above the first, first, and second terminals of the conductive layer are used to measure a second electrical characteristic; and based on the measured first and second electrical characteristics, it is judged that the component of the semiconductor wafer is used to detect conduction The overlap between the plug and the conductive layer is offset. Based on the above test, a wafer and a region are provided between the electrical plug and the conductive layer; the wafer is cut on the wafer, and the component region of the wafer is a line. Next, the second τ-shaped conductive layer and the second electrical characteristic are connected by the second and third conductive joints. Finally, the bit line inserting device in the element area overlaps with the above-mentioned track area to form a plurality of test element pads. The fourth test piece is measured. According to the plug and the invention, a method for detecting the device area shift is provided, including the following steps. The circle has at least one scribe line and a component to form the aforementioned test component, and at the same time, the semiconductor component, the bit line plug, and the first τ-shaped conductive layer, the first and the first electrical characteristics of the gold piece; and The fifth and sixth conductive bonding pads of the test element were used to measure the first and second electrical characteristics of the up-and-down, and the degree of overlap offset of the generatrix was estimated.

1229913

In order to make the above and other objects of the present invention obvious and easy to understand, a preferred implementation is exemplified below, and the desires and advantages can be described in more detail as follows: Sub-cooperation with the attached diagram, as [Embodiment] See Figure 2a, The metal layer and the conductive plug in the detection element region of the present invention are described in detail: one of the embodiments. And the active area 20 of the offset test element cloth is set on half of the semiconductor wafer. The semiconductor wafer also includes a plurality of components;: (® :: scribe line area ⑽ a metal line (M0) and bit line plug (CB ) System ',,, and _ identified in the figure), at least, the element area is the memory cell area, of which the two element area. For example, the first and second T-shaped conductive layers 31 and hard number memory cells. On the moving area 20, the first T-shaped conductive layer 31 has _ 2 symmetrically disposed on the main 3 ^ 2 and the third terminal ^ 13 a, and the second τ-shaped conductive layer 33 has 1 丨 1 and the first end and the first end. 3 3 2 and the third end 3 3 3 are used to measure-flute ', _ one, the second T-shaped conductive layer 31, 33 and the component area-electrical characteristics (the second line contact), using the same light Cover °° Lifan wire plug base (blt for example, the first and second τ-shaped conductive ^ process conditions are formed.: The wire plug base is composed of v electrical materials' for example, flip-chip stone, Ming, crane Wait for the first to second conductive bonding pads 41, 42 and the first end 311 of the n-T-shaped conductive layer 31 to be placed on the younger. Similarly, the fourth to first conductive bonding pads : Brother of end 312 and third end 313, conductive bonding pads 44, 45, 46, respectively

1229913

The first end 331, the second end 332, and the third end of the zigzag conductive layer 33 are used to measure a second electrical characteristic. The first to sixth guides (combination pads 4 and 46 are metal wires of the component area), and are formed using the same mask and process conditions. For example, the first to sixth pads 41 to 46 and the metal wires in the element region are made of the same conductive material, such as aluminum, crane, and so on. -In this example, 'by applying-a current from the first bonding clock through the first t-shaped conductive layer to the second conductive bonding pad 42, the voltage difference Vab between ㈡ and the second bonding pad 42 to find the pad The second conductive bonding pad 42, the _τ-shaped conductive layer, and the third conductive bonding pad 43 constitute one of the first equivalent resistance values Rab. By applying the predetermined current from the fourth bonding pad conductive layer to the fifth conductive bonding pad 45, and measuring the voltage difference Vcd between the sixth bonding pad and the fifth bonding pad 45, to obtain a second electrical characteristic That is, the fifth conductive bonding pad 45, the second T-shaped conductive layer 33, and the sixth conductive bonding pad 46 constitute a second equivalent resistance value Rcd. # 第 2b 图 is a sectional view in the aa direction in FIG. 2a. Under ideal conditions (that is, when no offset occurs), since the distance between points a and b will be equal to the distance between points ^, that is, L, the first equivalent resistance value Rab will be equal to the brother-specific resistance Value is Red. However, it can be seen from FIG. 3a that the first to sixth conductive bonding pads 41 to 46 are all shifted to the left by a distance of l. Fig. 3b is a cross-sectional view in the aa direction in Fig. 3a. 'Because the first to sixth conductive bonding pads 41 to 46 are all shifted to the left by a distance of l, the first equivalent resistance measured will be equal to Ra. b, while the second

1229913 Case No. 92123695 Amendment V. Description of the Invention (5) The effective resistance will be equal to Red ’. Since the first and second equivalent resistances will both conform to Equation 1 and Equation 2 ...

Ri2〇 —-7 ^ (1)

Red — x L-AL rw 7 (2) where Rpoly is the sheet resistance value of the first and second T-shaped conductive layers, and W is the line width of the first and second T-shaped conductive layers, because the process conditions are the same Therefore, according to Equations 1 and 2, Equation 3 ·· kT _ T Rab-Red 乂 Rob Seven Red can be obtained; (3) Therefore, by measuring the first and second equivalent resistance values, determine the First, the overlap offset between the second T-shaped conductive layers 31 and 33 and the first to sixth conductive bonding pad plugs 41 to 46. Since the first and second T-shaped conductive layers 31 and 33 are bit line plugs with the device region, they are formed using the same photomask and process conditions. Similarly, the first to sixth conductive bonding pads 41 to 46 are metal lines formed in the same region as the element area, and are formed using the same mask and process conditions. Therefore, when the mask is shifted, both the component area and the test component on the scribe line will produce a consistent shift. Therefore, the test component on the scribe line can reflect the conductive layer and bit line insertion in the component area. Whether there are overlapping shifts between the plugs. Next, a method for detecting whether an overlapping offset between the conductive layer and the bit line plug in the element region according to an embodiment of the present invention is described with reference to FIG. 4 is described below. The method includes the following steps. First step S402: providing a substrate having at least a dicing track and a component region thereon.

0548-93561WF1 (4.5); 91068; Dennis.ptc page 10 1229913 --- case number 92123695 V. Description of the invention (6)

Then step S404 is performed: forming a 5¾ yr piece on the scribe line of the substrate, and simultaneously forming a plurality of semiconductor components in the element area of the substrate, such as memory cells, transistors, etc., and at least one metal line, bit line plug The structure of the test element is shown in Figure 2a. Then proceed to step S 4 0 6. By applying a predetermined current from the eighth pad 41 through the first τ-shaped conductive layer 31 to the second conductive bonding pad 42, the third bonding pad 43 and the first The voltage difference V32 between the two bonding pads 42 has a long first electrical characteristic, that is, the second conductive bonding pad 42 and the first τ-shaped conductive layer constitute one of the second equivalent resistance values of the second conductive bonding pad 43 Rab.

Step S4 08: Apply the predetermined current from the fourth access person 44 to the second τ-shaped conductive layer to the fifth conductive bonding pad 45, and measure the voltage between the second bonding pad 46 and the fifth bonding pad 45. The difference is obtained in order to obtain a characteristic, namely, the fifth conductive bonding pad 45, the second τ-shaped conductive layer 33, and the first conductive bonding pad 46 constitute a second equivalent resistance value Rcd. ”Then proceed to step S410 ··············································· • ········ •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• of the overlap offset between the 41st and 46th-first plugs) The measured Rab specific resistance value Rab will be greater than the second equivalent

The sixth conductive bonding pad is offset two to seven to the right; 1 Rab will be less than the second equivalent resistance value Rcd. Resistance value The electrical offset between the electrical layers 31, 33 and the first to sixth guides, and the first T-shaped guide, is determined by the weight between the square plugs 41 ~ 46.

1229913 _ Case No. 92123695_ Year Month Date __ V. Description of the invention (7) kT _ T Eab-Red ^ Rab + Red; (3) Finally, step S412 is performed: the T-shaped conductive layer 31, 3 3 on the test element The amount of overlap with the conductive bonding pad plugs 41 to 46 estimates the degree of offset between the active area of the memory cell and the deep trench capacitance. Because when the mask is shifted, both the component area and the test component on the scribe line will produce a consistent shift. Therefore, the test line on the scribe line can reflect the metal line and bit line insertion in the component area. Whether there are overlapping shifts between the plugs. One of the advantages of the above-mentioned test element and test method is that the direction and degree of offset between the metal line and the bit line plug can be quickly confirmed by comparing the two equivalent resistance values Rab and Red. The second advantage of the above-mentioned test element and test method is that the test element is arranged on the scribe line, which can perform the same process as the element area simultaneously, monitor the offset between the metal line and the bit line plug, and avoid occupying the component area space. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

0548-93567WF1 (4.5); 91068; Dennis.ptc Page 12 1229913 Case No. 92123695 Amendment Brief Description of Drawings Figure 1 is a schematic diagram of a conventional metal wire and bit wire plug. Figure 2a is a schematic diagram of a test element of the present invention. Fig. 2b is a sectional view in the aa direction in Fig. 2a. Figure 3a is a schematic diagram of the test element of the present invention when an offset is generated. Figure 3b is a cross-sectional view in the direction aa of Figure 3a. FIG. 4 is a flowchart of a method for detecting a heavy offset of a metal line and a bit line plug in a device region according to the present invention. Explanation of symbols M 0: metal line; CB: bit line plug; 14: semiconductor device; 100: cut line area; 10: test device; 20: active area; 3 1: first T-shaped conductive layer; 32 : Second T-shaped conductive layer; 41 ~ 46: first to sixth conductive bonding pads; 311, 312, 313 ·· the first, second, and third ends of the first T-shaped conductive layer; 331, 332, 333 : The first, second, and third ends of the second T-shaped conductive layer

0548-9356TWFK4.5); 91068; Dennis.ptc page 13

Claims (1)

1229913 Case No. 92123695 Amendment VI. Patent Application Scope 1. A test element is provided in the scribe line area of a wafer to detect the overlap offset between the conductive plug and the conductive layer in the component area, including a An active area is provided in the above-mentioned cutting track area; a first and a second τ-shaped conductive layer are symmetrically provided in the above-mentioned cutting track area, each having a first, second, and third end; a first to a second Three conductive bonding pads are respectively disposed on the first, second, and third ends of the first T-shaped conductive layer to measure a first electrical characteristic; and a fourth to sixth conductive bonding pad, respectively It is disposed on the first, second, and third ends of the second T-shaped conductive layer to measure a second electrical characteristic. Based on the first and second electrical characteristics, it is determined to detect a component region. The overlap between the middle conductive plug and the conductive layer is offset. 2. The test device according to item 1 of the scope of patent application, wherein the above-mentioned device region has a plurality of semiconductor devices, bit line plugs and a metal layer. 3. The test device according to item 1 of the scope of patent application, wherein the first electrical characteristic is an equivalent resistance value of the first T-shaped conductive layer, the second and third conductive bonding pads. 4. The test element according to item 1 of the scope of patent application, wherein the second electrical characteristic is an equivalent resistance value of the second T-shaped conductive layer, the fifth and sixth conductive bonding pads. 5. The test element according to item 3 of the scope of patent application, wherein the first conductive bonding pad is used to receive a predetermined current, and the second and third bonding pads are used to measure a first voltage according to the above A predetermined current and the first voltage are used to obtain the first electrical characteristic. 0548-9356TWFK4.5); 91068; Dennis.ptc Page 14 1229913 Case No. 92123695 Amendment VI. Patent application scope 6. The test element according to item 5 of the patent application scope, wherein the fourth conductive bonding pad described above, The fifth and sixth bonding pads are used to receive the predetermined current, and the fifth and sixth bonding pads are used to measure a second voltage, and the second electrical characteristic is obtained according to the predetermined current and the second voltage. 7. The test device according to item 2 of the scope of patent application, wherein the first and second T-shaped conductive layers of the test device and the bit line plugs in the device region are formed by using the same mask. 8. The test element according to item 2 of the scope of patent application, wherein the first to sixth conductive bonding pads of the test element and the metal layer of the element region are formed using the same photomask. 9. The test element according to item 1 of the scope of the patent application, wherein the conductive plug is composed of polycrystalline stone. 10. The test element according to item 1 of the scope of patent application, wherein the conductive plug is made of tungsten. 11. The test device according to item 1 of the scope of patent application, wherein the conductive layer is composed of Shao. 1 2. — A test method for detecting the overlap offset between the bit line plug and the metal layer in the component area, including the following steps: Provide a wafer, the wafer has at least one scribe line and a component A test element is formed in the dicing track region of the wafer, and a plurality of semiconductor elements, bit line plugs, and metal lines are simultaneously formed in the element region of the wafer, wherein the test element includes: an active region, Set in the area of the cutting path; 0548-9356TWFK4.5); 91068; Dennis.ptc Page 15 1229913 Amendment VI. Patent application scope-the first and second τ-shaped conductive layers are symmetrically arranged in the above-mentioned cut-to-area, each having a first, The second and third ends; a first to a third conductive bonding pad respectively disposed on the first, second, and third ends of the first T-shaped conductive layer; and a fourth to sixth conductive pad. The bonding pads are respectively disposed on the first, second, and third ends of the second T-shaped conductive layer; the second and third conductive connections are measured by the first τ-shaped conductive layer and the first combination. A first electrical characteristic of one of the components; a second electrical characteristic of one of the test components measured by the second τ-shaped conductive layer, the fourth, fifth, and sixth conductive bonding pads; and according to the first and second electrical characteristics Characteristics, the degree of overlap offset between the bit line plug and the metal line in the element area is estimated. 1 3 · The test method described in item 12 of the scope of the patent application, wherein the first electrical characteristic is the equivalent resistance value of the first T-shaped conductive layer, the second and third conductive bonding pads. 1 4 · The test method as described in item 3 of the patent application scope, wherein the second electrical characteristic is an equivalent resistance value of the second T-shaped conductive layer, the fifth and sixth conductive bonding pads. 1 5 · The test method described in item 13 of the scope of patent application, wherein a predetermined current is applied to flow through the first and second conductive bonding pads, and the distance between the second and third bonding pads is measured. , The first voltage 'to obtain the first electrical characteristic. 1 6 · The test method as described in item 5 of the scope of patent application, wherein the fourth and fifth conductive bonding pads are passed through the application of the predetermined current, 0548-9356TWFK4.5); 91068; Dennis.ptc Page 16 1229913 Case No. 92123695 Amendment VI. Apply for a patent and measure the second voltage between one of the fifth and sixth bonding pads to obtain the second Electrical characteristics. 1 7. The test method as described in item 13 of the scope of the patent application, wherein the first and second T-shaped conductive layers of the above-mentioned test element are plugged with bit lines of the element area and formed using the same photomask . 1 8. The test method as described in item 13 of the scope of the patent application, wherein the first to sixth bonding pads of the test component and the metal layer of the component area are formed by using the same photomask. 0548-9356TWFK4.5); 91068; Dennis.ptc p. 17