TWI228791B - Stacked dielectric layer suppressing electrostatic charge buildup and method of fabricating the same - Google Patents

Abstract

A method of fabricating a stacked dielectric layer for suppressing electrostatic charge build up. First, a substrate having metal layers thereon is provided, with a plurality of gaps formed therebetween. Next, a dielectric layer is formed by simultaneous deposition and ion-bombardment, such that the dielectric layer covers the bottom dielectric liner and fills the gaps. Finally, a top dielectric liner is formed on the dielectric layer by deposition without ion-bombardment. Furthermore, the present invention provides another method to fabricate a stacked dielectric layer to suppress electrostatic charge buildup. As a result, the above-mentioned methods can efficiently avoid metal extrusion issues.

Description

1228791

V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a semiconductor process technology ', and more particularly to a dielectric layer which is less prone to static electricity and a method for manufacturing the same. With the advancement of semiconductor technology, the degree of semiconductor accumulation has continued to increase, and the number of components in a single chip has also increased. More multilayer interconnect wire layers must be used, and good electrical isolation must be filled between the interconnect wire layers. The material is the so-called inter-level metal die layer (IMD), and silicon oxide formed by an appropriate chemical vapor deposition method is a common metal interlayer dielectric material. In order to improve the characteristics of the dielectric layer and meet the special needs of different applications, there are many related studies on the dielectric layer process.

US Patent No. 5,60 5, 859 published by Lee et al., Discloses a method for forming a dielectric layer on the surface of polycrystalline silicon by plasma enhanced chemical vapor deposition (PECVD). method.

U.S. Patent No. 5,741,740 published by Jang et al. Discloses a method for forming a dielectric layer using plasma enhanced chemical vapor deposition (PECVD) as a shallow trench isolation This method allows the dielectric layer to be filled in trenches with a high aspect ratio. When the accumulation of the semiconductor ancient increasingly pumping, / ^ ^ t I ~ 咼 the pawl, respiratory droplets than the trench or gap X also ~ e to a density plasma chemical vapor deposition growing, therefore, the development of Che ancient

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1228791 V. Description of the invention (2) (High density plasma chemical vapor deposition; HDPCVD) ′ To improve the filling capacity of the deposited dielectric layer. The high-density plasma chemical vapor deposition system provides an ion bombardment at the same time of deposition to deposit a dielectric layer on the sidewall of the trench or the gap at a later time. In this way, the dielectric layer can be ensured along the trench or the gap Vertical growth ensures that the dielectric layer completely fills the trenches or gaps without leaving voids. ,

U.S. Patent No. 6,678, published by Shufflebotham, reveals that a silicon oxide film was formed using silicon densities, oxygen, and inert gases as precursors. Method, the width of the groove can be less than 0.5 centimeters, and the aspect ratio (up = groove ratio) can be higher than 1.5.

Knorr et al., U.S. Patent No. 6,531,377, also discloses a method for filling high aspect ratio trenches by a continuous high-density plasma chemical vapor deposition method. In the process of high-density plasma chemical vapor deposition (HDPCVD), the side walls of trenches or gaps to be filled are bombarded with r ions to make the deposits grow in a vertical direction. Therefore, the media deposited by HDPCVD The electrical layer may have good trench filling capabilities. However, the high-density plasma chemical vapor deposition method has a meta 1 extrusion issue when forming a dielectric layer. Referring to FIG. 1, a patterned metal is first formed on the semiconductor substrate 100. Layer 1 0 2. After that, a compliant linear dielectric layer 106 is formed on the surface of the metal layer 102. Thereafter, a dielectric layer 108 is deposited on the liner dielectric layer 102 by HDPCVD and filled.

0503-93661wF (η 1); t smc2002-0998; 0801; Fe1i c i a.ptd page 8 1228791 V. Description of the invention (3) A gap in the metal layer 102. Residues from ion bombardment or bombarded ions in the HDPCVD process may break the bonding of some dielectric layers, which may cause some charged particles in the dielectric layer 108 to be generated. Next, in order to remove impurities on the surface of the dielectric layer 108, a rinse process 4S100 (water scurbbin0g) is used.

To remove the impurities generated in the HDPCVD process, a jet scrubber is usually used for 3 ~ 6. The inclination angle provides a deil water to clean the surface of the dielectric layer 108. At this time, as the deion water rubs the surface of the dielectric layer 108, a large amount of electrostatic charges are induced on the surface of the dielectric layer 108. (Electrostatic charges) 2 0, and these electrostatic charges 20 0 will form a pull on the metal layer 10 6 below the dielectric layer 108. Force, which causes the problem of metal extrusion 106a. SUMMARY OF THE INVENTION One of the objectives of this month is to provide a dielectric layer which is less prone to generate static electricity and a method of manufacturing the same 'to avoid the problem of metal extrusion caused by a large amount of electrostatic charge induced near the surface of the dielectric layer due to the washing process.

The first main feature of this invention is that by forming a top chelated dielectric layer on the surface of a high-density plasma chemical vapor deposition dielectric layer with good trench filling capability, the top liner dielectric layer is deposited during the deposition process and It does not provide the Li Xiao to avoid the generation of charged particles, so it can effectively avoid the large static electricity induced by the friction between the water and the dielectric layer during the subsequent washing process, thereby suppressing the problem of metal extrusion. J, J: No.1—The main feature is the process of dysplasma treatment for "degree of electrical vapor deposition dielectric layer" with good trench filling force.

1228791 V. Description of the invention (4) Sequence 'The charge in the dielectric layer is eliminated by the ions and / or charges introduced by the low-power plasma processing program, so that water and dielectricity can be effectively avoided during subsequent washing procedures. A large amount of electrostatic charge is induced by the friction between the layers, thereby suppressing the problem of metal extrusion. ♦ In order to achieve the above object, the present invention proposes a method for manufacturing a dielectric layer that is not prone to generate static electricity. The steps of the method mainly include: First, providing a substrate, wherein the surface of the substrate has a metal layer, and the metal layer has a plurality of gap. Next, a dielectric layer is formed to cover the surface of the metal layer and fill the plurality of gaps. Finally, a low-power plasma processing program is used to introduce ions and / or charges into the dielectric layer to eliminate the charges in the dielectric layer. According to the present invention, the foregoing method can be applied to a semiconductor dielectric layer process with a notch line width less than 0.15 // m. According to the present invention ', the ions and / or charges are introduced into the dielectric layer by a plasma processing procedure. The gas used in the plasma treatment process may include nitrogen (n2), oxygen (〇2), nitrous oxide (N20), helium (He), neon (Ne), and argon (Ar). , 氪 (Kr), 氤 (xe), or 氡 (Rn). The detailed conditions for processing the private sequence by A electric table include: The pressure in the chamber is generally 2 to 10 torr, the flow rate of the gas used is about 30 0 to 500 sccm, and the power of the power (RF Power) is about 20 to 50. 0W, and its Bias Power is about 0 ~ 500W. The execution time is about 5 ~ 60 seconds. As described above, the material of the metal layer includes copper (Cu), indium (Ai), or copper aluminum alloy (Cu / Al al loy). As mentioned previously, before forming the dielectric layer, it may further include conformable

0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd Page 10 1228791 V. Description of the invention (5) The bottom pad dielectric layer is on the metal surface and in the notch. As described above, the material of the dielectric layer may be fluorinated silica glass (FSG). Silicon or fluorine-doped silicon glass,-squares are = a method for manufacturing a dielectric layer that is not prone to generate static electricity. The steps of this method mainly include: first, providing a substrate, wherein the surface of the substrate has a metal layer, and The metal layer has a plurality of notches. It is difficult to form a dielectric layer to cover the metal layer and fill the gap by a deposition method with ion strike. Finally, a top liner dielectric layer is formed on the surface of the dielectric layer by a deposition method without ion bombardment. According to this method, the method can be applied to the process of manufacturing a semiconductor dielectric layer with a notch line width greater than 0. 15 #m. As described above, before forming the dielectric layer, the method further includes: compliantly forming a bottom pad dielectric layer on the surface of the metal layer and in the gap. The bottom pad dielectric layer is formed by a deposition method without ion bombardment. The deposition method without ion bombardment includes: sub atmospheric pressure thermal chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), and low pressure chemical vapor deposition (low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition without ions bombardment; PECVD without ions bombardment, and high-density electropolymerized chemical vapor phases that do not provide ion bombardment

0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd page 11 1228791 V. Description of the invention (6) Deposition (high density plasma chemical vapor deposition without ions bombardment i HDPCVD without ions bombardment). The thickness of the bottom pad dielectric layer is about 200-400 A, and the material may include silicon oxide. As mentioned above, the material of the metal layer includes copper (Cu), aluminum (A1), or copper / aluminum alloy (Cu / Al alloy). As mentioned above, the dielectric layer is formed by high-density plasma chemical vapor deposition (HDPCVD), and the material can be silicon oxide or fluorine-doped silicon glass, and its thickness is generally 30 0 0 to 1 50 0 0 A.

As mentioned above, the deposition methods without ion bombardment to form the top liner dielectric layer include: sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LpcvD) 2. Plasma-enhanced chemical vapor deposition (PECVD with 0ut ioons bombardment) that does not provide ion bombardment and HDPCVD without ions bombardment that does not provide ion bombardment. Wherein, the material of the dielectric layer of the top liner includes silicon oxide, and its thickness is approximately 400 ~ 600 A. Through the above method of the present invention, the present invention also proposes a kind of static electricity that is not easy to produce: ′! The "electric capacitor" mainly includes: a substrate: a metal layer disposed on the bottom surface and having a plurality of notches; a dielectric layer covering the metal layer and J = = mouth; "and a top pad dielectric layer The top liner dielectric layer formed in the dielectric layer Table 2 is formed by a deposition method without ion bombardment. This month, a new type of dielectric layer that is not easy to generate static electricity is mainly proposed.

1228791 V. Description of the invention (7) "-Including a substrate · a metal layer provided on the surface of the substrate and having a plurality of missing two; and a dielectric layer covering the metal layer and filling the gap, wherein ^ 介The electrical layer is treated with a plasma to eliminate the charge in the original dielectric layer. In order to make the purpose, features, and advantages of the present invention more comprehensible, the preferred embodiments are exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: The implementer illustrates that the root pattern is plural or Copper and aluminum may be included in containers or used in the absence of examples, but the corresponding bottom of which is formed in the vapor-sinking type. Example 1 The cross-section view of the process with reference to Figures 2A to 2D is used according to the first of the invention Examples. First, referring to FIG. 2A, a substrate 200 is provided, and a metal layer 202 is formed on the surface of the substrate 200, and the metal layer 202 has a notch 204 therein. The material of the metal layer 202 is, for example, copper (Cu) or aluminum (Cu / Al alloy), and preferably copper. In addition, the substrate 200 includes required semiconductor elements (not shown), such as a transistor, and any conventional semiconductor element. The first embodiment of the present invention does not limit the present invention by using a semiconductor dielectric layer with a line width dl greater than 0.15 / m. For reference, please refer to FIG. 2B. The compliance ((3〇11 『〇rma 1) forms a compliant pad dielectric layer 206 on the surface of the metal layer 202 and the notch 204. The bottom pad dielectric layer 2 0 6 The deposition method without ion bombardment is used. The so-called deposition method without ion bombardment can be sub-atmospheric pressure thermal chemical

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T2287Q1 V. Description of Invention (8)

vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition without ion bombardment (Plasma enhanced chemical vapor deposition without ions bombardment; PECVD without ions bombardment) or high density plasma chemical vapor deposition without ion bombardment (HDPCVD without ions bombardment). Among them, high-density plasma chemical vapor deposition without ion bombardment is preferably achieved by adjusting the bias power to not provide ion bombardment. Generally speaking, the conventional high-density plasma chemical vapor deposition provides an ion bombardment at the same time as the deposition, which is used to etch the deposits formed on the gaps or trench sidewalls to be filled. It grows in the vertical direction of the notch or trench, but please note that this step uses a deposition method without ion bombardment. The preferred embodiment of the bottom pad dielectric layer 20 6 of the present invention is to place the substrate 200 with the metal layer 200 in a stomach of a plasma chemical vapor deposition reactor. The deposition was performed without providing the bias of the ion strike. The thickness of the bottom pad dielectric layer 206 is approximately 2000 to 400 A. The material may include oxide stone (eg, $ 丨 ο?). Next, referring to FIG. 2C, a dielectric layer 208 is formed to cover the surface of the metal layer 202 and fill the gap 2 by deposition and ion bombardment (that is, using a deposition method with ion bombardment). 0 4. The dielectric layer 204 is, for example, formed by using a pale-density electropolymerization chemical vapor deposition method (PCVD).

1228791 V. Description of the invention (9) Following the performance, the substrate 200 was placed inside the high-density plasma chemical vapor deposition reactor forming the bottom pad dielectric layer 206, under the condition of providing an ion bombardment bias. The dielectric layer 208 is deposited, so that the dielectric layer 208 will be deposited and grown along the vertical direction of the notch 204, so the dielectric layer 208 formed by the high-density plasma chemical vapor deposition can be Has good trench filling ability. However, due to the residual bombardment or bombardment ions in the traditional HDPCVD process, some of the bonding of the dielectric layer 208 will be interrupted, and there will be some electrical particles in the deposited dielectric layer 208. In the conventional technology, these charged particles (charges) cause a large amount of electrostatic charges to be induced on the surface of the dielectric layer 20 during a water scrubbing process, thereby causing the S problem of conventional metal extrusion. Wherein, the material of the dielectric layer 208 may be silicon oxide (for example, 〇2) or fluorine-doped silicon glass, and its thickness is generally 3000 ~ 15000A. Operating conditions for high-density plasma chemical vapor deposition include, for example: power supply (RF power) of about 20000 ~ 4500 watts, bias power (Bias Power) of about 2000 ~ 4500 watts, its precursors include Saisai and oxygen are under a pressure of about 0 ~ ltorr and a temperature of about 200 ~ 700 ° C.

Next, referring to FIG. 2D, a top liner dielectric layer 210 is formed on the surface of the dielectric layer 208 by a deposition method without ion bombardment. The deposition method without ion bombardment to form the top liner dielectric layer 2 10 can be sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), not provided Plasma enhanced chemical vapor deposition (PECVD without ions bombardment) for ion bombardment and high-density plasma chemical vapor deposition (HDPCVD with 〇ut iQns bombardment) that does not provide ion bombardment, of which the height without ion bombardment is preferred Density plasma

1228791 V. Description of the invention (10) ^-Chemical vapor deposition. In a preferred embodiment, the dielectric layer 2 and the substrate 200 are continuously placed in the stomach of a high-density plasma chemical vapor deposition reactor, and the deposition is performed without providing a bias voltage for ion bombardment. The material of the top layer 2 10 may be silicon oxide (for example, s 丨%), and its thickness is large; 400-600 A. for

Referring to FIG. 2D, the structure for avoiding the metal from the dielectric layer of the present invention mainly includes: a pad dielectric layer 210 from the substrate 200, the metal layer 202, and the dielectric layer 208. The metal layer 202 is disposed on the surface of the substrate 200 and has a plurality of notches 204 at the top. The dielectric layer 208 covers the metal layer 202 and is filled with a mold 204. The top liner dielectric layer 21 is formed on the surface of the dielectric layer 208 with a γ notch. The top liner dielectric layer 2 10 is formed by a deposition method without ion bombardment. In addition, a portion of the pad dielectric layer 206 may be further formed between the metal layer 202 and the dielectric layer 208. There is a bottom. Finally, a water scrubbing (water scrubbing) is performed on the entire surface of the stacked dielectric layer to remove the entire stacked dielectric layer ^ = impurities. A jet scrubber can be used to use the sophomore 3 side /

The inclination angle provides a deil water to clean the top liner dielectric layer 210. At this time, although the deionized water rubs the surface of the top liner dielectric layer 210, compared to the conventional HDPCVD deposition Dielectric layer: The top liner dielectric layer 210 formed by the deposition method without ion bombardment according to the present invention, because the top liner dielectric layer 21 does not have a large number of charged particles (charges), so When the flushing process is performed, the surface of the top pad dielectric layer 21 is not easily caused by a large amount of electrostatic charges, so that it can effectively avoid the conventional metal extrusion problem caused by the electrostatic charge.

1228791 V. Description of the invention (11) Advantages according to the first embodiment of the present invention: The method and structure have the following features: 1. The stacked dielectric according to the present invention ^ vapor-deposited dielectric layer 208. Chemistry 2. Stacking according to the present invention; ^ 7 \ good trench filling ability. 210, there is no mention during the deposition process-there will not be a lot of charge in the top lining dielectric layer 210 :: bombardment, so the induced static electricity in the top pad dielectric is reduced. problem. Therefore, the conventional metal extrusion is effectively avoided3. According to the present invention, the stacked dielectric 206, the dielectric layer 208, the TSAR layer including the bottom pad dielectric layer, and the dielectric layer 210 are lined with a sheet of silicon, The formation of each layer can be J: "The plasma chemical vapor deposition method does not provide ion bombardment, which is only possible when the dielectric layer 210 is lined on the top, and ion bombardment is provided when the electric layer 208 is provided. ^ Qn-sUu) Deposition stack Nie Jie said that it can be deposited in the same deposition device ^ a ^ 9 疋 21〇. The product is placed in the dielectric layers 20 6,208 and Example 2 After the development of the line width is less than 0.15_, the extra sub-transmission speed of the method of the first embodiment is increased, however, the resistance value of the overall dielectric layer is increased, and the electron-transmission speed of the lined dielectric layer 210 will be increased. .-Because of A, the bamboo shoots slowly increase and decrease; the manufacturing method of the dielectric layer .... U another is not easy to generate static electricity

1228791 V. Description of the invention (12) The following is a description of a second embodiment according to the present invention with reference to the cross-sectional views of the processes of FIGS. 3A to 3D. First, referring to FIG. 3A, a substrate 300 is provided, and a patterned metal layer 302 is formed on the surface of the substrate 300, and the metal layer 302 has a plurality of notches 304. The material of the metal layer 3 0 2 may include copper (Cu), aluminum (A 丨), or copper / aluminum alloy (Cu / Al alloy), preferably copper. In addition, the substrate 300 may include a required semiconductor element (not shown), such as a transistor, a capacitor, or any conventional semiconductor element. The second embodiment of the present invention takes the semiconductor dielectric layer process for the notch 304 with a line width d2 of less than 0.15 as an example, but it is not limited to the present invention. Then, the “4D photo according to FIG. 3B” compliance ((: 〇] 1] ^ 〇1 ^ 111 & 11 乂) forms a bottom pad dielectric layer 306 on the surface of the metal layer 302 and in the gap 304. Among them The bottom pad dielectric layer 306 is formed using a suitable chemical vapor deposition (CVD) method, including: sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (ApcvD), Low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and high density plasma chemical vapor deposition (HDpcVD). The thickness of the bottom pad dielectric layer 306 is approximately 200. ~ 400A, the material can be siliconized (for example, Si 02). Then, please refer to FIG. 3C to form a dielectric layer 308 covering the surface of the metal layer 302 and filling the gap 304. The dielectric layer 304 is formed, for example, by using high-frequency, f-plasma chemical vapor deposition (HDPCVD). The high-density plasma chemical vapor deposition method simultaneously provides an ion worm when depositing the dielectric layer 304. The dielectric layer 304 will be deposited and grown along the vertical direction of the gap 304, because

1228791 V. Description of the invention (13) The dielectric layer 308 formed by high-density plasma chemical vapor deposition can have good trench filling ability. However, in the traditional HDpcvD process, due to the residual ion or bombarded ions, some of the dielectric layers 308 will be broken, and some charged particles (charges) will be generated in the deposited dielectric layer 308. In the conventional technology, these charged particles will cause a large amount of electrostatic charge to be induced on the surface of the dielectric layer 308 during the subsequent washing process (~ redundant scrubbing), thereby causing the problem of metal extrusion. The material of the dielectric layer 308 may include silicon oxide (such as SiO 2) or fluorine-doped silicate glass (fluorated siUca giass; FSG), and its thickness is generally 3,000 to 150,000 a. Operating conditions for high-density plasma chemical vapor deposition include, for example, power supply power (RF power) of about 200 0 to 4500 watts, and bias power (Bias power) of about 2 0 0 0 to 4 5 0 0 wa t't s, the precursors of which include Shi Xiyao (sa 1 ne ne \ and oxygen, at a pressure of about 0 to ltorr, and a temperature of about 200 to 700 ° C.) For important steps, please refer to FIG. 3D. By performing a low-power plasma processing procedure S300 on the dielectric layer 308, introducing ions (including positively and negatively charged ions) and / or charges (including positively and negatively charged charges) into the dielectric Within the electrical layer 308, the charges in the dielectric layer 308 are neutralized or discharged, among which ions (positive and negative ions) are the main ones. Among them, the low-power plasma processing program S3. 〇The gas used can be nitrogen (N2), oxygen (〇2), nitrous oxide (n2〇), helium (He), neon (Ne), argon (Ar), krypton (κΓ), Krypton (Xe) or Krypton (R η). When the low-power plasma treatment program S 300 is performed, the pressure in the reactor is generally 2 to 10 Torr. Flow of about 3〇〇~5〇〇sccm, electrical power source (RF Power) about 20~5 00W, most preferably 5〇w which bias power

0503-9366twF (η 1); t smc2002-0998; 0801; Fe1i ci a.ptd page 19 1228791 V. Description of the invention (14) " " " * (Bias Power) is about 0 ~ 5. 〇w, the execution time is about 5 ~ 60 seconds. According to the present invention, after the low-power plasma processing program s300, the charged particles inside the dielectric layer 308 can be effectively eliminated. Then, a subsequent water scrubbing (not shown) can be performed on the surface of the dielectric layer 308 to remove impurities on the surface of the dielectric layer 308. For example, using a washing machine (with scrubber): two large, force 36 tilt angle, provide a deionized water to clean the top pad dielectric layer 210, at this time, although the deionized water will rub the dielectric layer 30 The surface, but after the low-power plasma treatment process of the present invention, it has a large number of bands ... 'Therefore, the dielectric layer 3.8 shows the "electric layer 08 induction, and a large amount of electrostatic charge is generated. By RF power 50w" The induced electrostatic tail voltage of the dielectric layer treated by the plasma treatment can be reduced from -7 3 V to 1 v, ro 1 1 丄 leilei; T μ η 丨 can be effectively avoided by people who are born and born The problem of metal extrusion due to electrostatic attraction. Although the present invention is disclosed as above with the preferred embodiments, the scope of the present invention is not limited. Anyone familiar with this item is not within the spirit and scope. It can be used as a variety of members. The scope of protection of the present invention shall be regarded as the attached patent. Range; catty;

1228791 Brief description of the diagram. Figure 1 shows the disadvantages and intentions of the conventional technology of extruding metal on the surface of the dielectric layer. Figures 2A to 2D show the fabrication of a dielectric layer that is not prone to static electricity according to the present invention A process cross-sectional view of a preferred embodiment of the method; and FIGS. 3A to 3D are cross-sectional views of a process of another preferred embodiment of a method for manufacturing a dielectric layer that does not easily generate static electricity according to the present invention. DESCRIPTION OF SYMBOLS 106a ~ Metal extrusion 100 ^ 200 ^ 300 substrate; 3 02 ~ metal layer; notch; 3 06 ~ bottom pad dielectric layer; 308 ~ dielectric layer; 102, 202 204, 304 106 > 206 108, 208, 210, 310 ~ top dielectric layer; 200 ~ electrostatic charge; S100 ~ flushing procedure; S300 ~ plasma processing procedure.

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Claims (1)

1228791, Shen Qing patent scope 1 Tart: a method of manufacturing a dielectric layer that is not prone to static electricity, including: a metal layer; and right, wherein the surface of the substrate has a metal layer, and the gold has a plurality of gaps; the gaps; 2 And; 1 an electrical layer to cover the surface of the metal layer and fill the plurality of introduced ions and / or charges in the dielectric layer. The method of making a layer of 2 layers, applying the dielectric or steel method which is not easy to generate static electricity as described in item 1 of the patent scope, wherein the material of the metal layer includes copper (Cu), aluminum (A1), J aluminum alloy (Cu / Al aUc) ) y). 1 5 # m。 3 J layer of Luo 2 application for the scope of the patent described in item 1 is not easy to generate static dielectric, manufacturing method 'wherein the line width of the gap is less than 0. 1 5 # m. The four-layer method of the patent application scope of the patent application No. 1 of the method for generating static electricity is not easy to generate a two-k method, wherein before forming the dielectric layer, further includes a conformable & pad dielectric layer on the metal The surface is within the gap. The method for manufacturing a dielectric layer is described in item 1 of the patent application range of 5 layers, which is not easy to generate static electricity. 'The dielectric layer is formed by high-density plasma chemical vapor deposition, silicon oxide or fluorine-doped. Fluorinated silica glass (FSG) layer. The method of manufacturing the dielectrics as described in item 1 of the scope of the patent application, which is not easy to generate static electricity, is the method of fabricating clothes, wherein the ions and / or charges are introduced into the dielectric layer by a plasma treatment. 7. The hard-to-produce party as described in item 6 of the scope of patent application, where the gas used in the plasma treatment process includes nitrogen pores (2), milk oxygen (02), _ dinitrogen oxide (仏 〇), helium He 0503-9366twF (nl); tsmc2002-0998; 0801; Fel iCja ptc ^ 1228791 6. Scope of patent application (Ne), argon (Ar), krypton (Kr), nitrogen (xe) or krypton (Rn). 8. The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in item 6 of the scope of the patent application, wherein the pressure in the reactor during the plasma process is 2 to 10 torr. The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in the above item, wherein the flow of the gas used in the plasma processing procedure is 300 ~ 500 sccm 〇 10. The dielectric material that is not prone to generate static electricity as described in item 6 of the scope of patent application The manufacturing method of the layer, wherein the RF power used in the plasma processing procedure is 20 ~ 500W. ... _11 · The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 6 of the scope of the patent application, wherein the bias work used in the plasma processing procedure (Bias Power) is 0 ~ 500W 〇1. 2. The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in item 6 of the scope of the patent application, wherein the plasma treatment process is performed for 5 to 60 seconds. "1 3 ·-A method for manufacturing a dielectric layer that is less prone to static electricity, includes: providing a substrate, wherein the surface of the substrate has a metal layer, and the metal layer has a plurality of gaps; forming a dielectric layer to cover the The surface of the metal layer is filled with the plurality of gaps; and a low-power plasma processing program is performed on the dielectric layer, and the power of the low-power plasma processing program (RF Power) is 20 ~ 50 0W. 1 4 · If applied The medium that is not easy to generate static electricity as described in the patent scope item 13 0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd page 23 1228791 6. A method of manufacturing a patented electrical layer, wherein the dielectric layer is made of high-density silicon oxide or fluorine-doped silicon formed by HDPCVD (fluorinated silica glass; FSg). )Floor. ,% -r π 囷 囷 1 factory / 丨 4 ~ 丨, manufacturing method of the blade house-generated electrostatic manpower layer, wherein the low-power plasma processing program is introduced; 1 and / or electricity% in the dielectric In the layer, it is used to make the sub / in the dielectric layer /,. 1 Λ J 电 何 敌 出 (discharge) ° 16 · The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in item 3 of the patent application scope, wherein the low-power plasma treatment process is used; 1 The second body includes nitrogen (N2), oxygen (0 2 ), Nitrous oxide (NgO), helium (He), neon (Ne), argon (Ar), i (Kr), krypton (Xe) or krypton (Rn). 17 · The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in item 3 of the patent application scope, wherein the pressure in the reactor during the low-power plasma processing procedure is 2 to 10 Torr. 18 · The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in item 3 of the scope of the patent application, wherein the flow rate of the gas used in the low-power plasma processing program is 3 0 ~ 5 0 0 s c c m. 19. The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in item 13 of the scope of the patent application, wherein the bias power (Bias Power) used in the low-power plasma processing program is 0 ~ 50 0W. 20 · The method for manufacturing a dielectric layer that is less prone to static electricity as described in item 13 of the scope of patent application, wherein the low-power plasma processing procedure is performed for 5 to 60 seconds. 21 · The medium that is not easy to generate static electricity as described in item 13 of the scope of patent application 1228791 6. Scope of patent application The manufacturing method of the electric layer, after the low-power plasma treatment process, further includes a water scrubbing process. 22 · A method of manufacturing a dielectric layer that is less prone to static electricity, including providing a substrate, wherein the surface of the substrate has a gold layer and a plurality of gaps in the metal layer; by a deposition method having ion bombardment, A dielectric layer is formed to cover the metal layer and fill the gap; and a member pad dielectric layer is formed on the surface of the dielectric layer by a non-ion deposition method. 2 3. The method for manufacturing a dielectric layer that is not prone to generate static electricity as described in item 22 of the scope of patent application, wherein before forming the dielectric layer, the method further includes: conformably forming a bottom pad dielectric layer on the surface of the metal layer. With the gap inside. 2 4. The method for manufacturing a dielectric layer that is less prone to static electricity as described in item 23 of the scope of the patent application, wherein the bottom pad dielectric layer is formed by a deposition method without ion bombardment. 25. The method for manufacturing a dielectric layer that is less prone to static electricity as described in item 24 of the scope of the patent application, wherein the deposition method without ion bombardment is sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD) ), Low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition without ion bombardment (PECVD without ions bombardment) or high density plasma chemical vapor deposition (HDPCVD without ions bombardment) that does not provide ion bombardment. 2 6 · The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 23 of the scope of patent application, wherein the thickness of the bottom pad dielectric layer is 0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd Page 25 1228791 VI. Patent application range 200 ~ 400 A ° 2 7 · Dielectric that is not easy to generate static electricity as described in item 23 of the patent application range The manufacturing method of the layer, wherein the material of the bottom pad dielectric layer includes oxidized stone. 2 8 · The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 22 of the scope of the patent application, wherein the material of the metal layer includes copper (CU), aluminum (A1) or Cu / Al alloy ). 2 9 · The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 22 of the scope of patent application, wherein the line width of the notch is greater than 0 · 1 5 // m. 30. The method for manufacturing a dielectric layer that is not prone to static electricity, as described in item 22 of the scope of the patent application, wherein the dielectric layer is a silicon oxide formed by high-density plasma chemical vapor deposition (HDPCVD) or Fluorinated silica glass (FSG) layer. 3 1. The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 22 of the scope of patent application, wherein the thickness of the dielectric layer is 3000 to 15000A. 3 2 · The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 22 of the scope of patent application, wherein the deposition method without ion bombardment is sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition without ion bombardment (PECVD without ions bombardment) or high density plasma chemical vapor deposition (HDPCVD without ions bombardment) ). 3 3 · The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 22 of the scope of patent application, wherein the material of the top pad dielectric layer includes oxidation 0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd page 26 1228791 Scope of Patent Application Shi Xi. 34. The method for manufacturing a dielectric layer that is not prone to static electricity as described in item 22 of the scope of patent application, wherein the thickness of the top pad dielectric layer is " 400 ~ 600 A 〇 35. As the scope of patent application item 22 The method for manufacturing a dielectric layer that is not prone to generate static electricity further includes performing a water scrubbing process after forming the top pad dielectric layer. 36 · A dielectric layer that is not prone to static electricity, including: a substrate: a metal layer provided on the surface of the substrate and having a plurality of gaps; and a dielectric layer covering the metal layer and filling the gap, wherein the The dielectric layer is processed by a plasma processing program. 37. A dielectric layer that is not prone to static electricity as described in item 36 of the scope of the patent application, wherein a dielectric layer is formed between the metal layer and the dielectric layer. -38-The dielectric layer that is not prone to static electricity as described in item 37 of the scope of patent application, wherein the thickness of the bottom pad dielectric layer is 200 ~ 400A. 39. The dielectric layer that is not prone to static electricity as described in item 37 of the scope of patent application, wherein the material of the bottom pad dielectric layer includes silicon oxide. 1 40 · As described in item 36 of the scope of the patent application, the eight electrical layers that are not prone to static electricity, wherein the material of the metal layer includes copper (Cu), aluminum (A1), or steel (Cu / Al alloy) ). 5 4 1 · The dielectric layer that is not prone to static electricity as described in item 36 of the scope of patent application, wherein the line width of the gap is greater than 0.1 5 # m. ;1 1228791 6. Scope of patent application 42. The eighth electrical layer that is not prone to generate static electricity as described in item 36 of the scope of patent application, wherein the material of the dielectric layer includes silicon oxide or fluorinated silica glass (FSG). 4 3 · As described in item 3 β of the scope of the patent application, the static electricity-generating public layer is difficult to generate, wherein the thickness of the dielectric layer is 3000 to 15,000 Α. 44. A dielectric layer that is not prone to static electricity as described in item 36 of the scope of the patent application, wherein the gas used in the plasma treatment process includes nitrogen (&) ^ oxygen (〇2), nitrous oxide (N20) , Helium (He), Neon (Ne), Gas $ (Ar), Krypton (Kr), Krypton (Xe), or Krypton (Rn). Feiqi 45 · As described in item 44 of the scope of the patent application, a dielectric layer that is not prone to static electricity ', wherein the power supply power (RFP 〇wer) of the plasma processing program is 2 0 ~ 5 0 0 W 〇46 · —It is not easy A dielectric layer that generates static electricity includes: a substrate; a metal layer disposed on the surface of the substrate and having a plurality of gaps; a dielectric layer covering the metal layer and filling the gap; and a top pad dielectric Layer formed on the surface of the dielectric layer, wherein the top pad dielectric layer is formed by a deposition method without ion bombardment. 4 7. The dielectric layer that is not prone to static electricity as described in item 46 of the scope of the patent application, wherein the dielectric layer and the metal layer further include: a bottom pad dielectric layer, and the compliance is formed on the metal The surface of the layer is within the gap. 48. The dielectric layer that is not prone to static electricity as described in item 47 of the scope of patent application, wherein the bottom pad dielectric layer is formed by a deposition method without ion bombardment. 0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd Page 28 1228791 VI. Application for patent scope 4 9 · As described in the scope of patent application No. 48, the dielectric layer is not easy to generate static electricity. The ion bombardment deposition method is sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition without ion bombardment (PECVD without ions bombardment) and high-density plasma chemical vapor deposition (HDPCVD without ions bombardment) 〇 5 0 · As described in the scope of the patent application No. 47, the dielectric layer is not easy to generate static electricity, wherein the bottom liner The thickness of the dielectric layer is 200 ~ 400A. 5 1 · The dielectric layer that is not prone to static electricity as described in item 47 of the scope of patent application, wherein the material of the bottom pad dielectric layer includes silicon oxide. 5 2 · The dielectric layer not likely to generate static electricity as described in item 46 of the scope of patent application, wherein the material of the metal layer includes copper (Cu), aluminum (A1) or copper / aluminum alloy (Cu / Al alloy). 5 3 · Dielectric layer that is less prone to generate static electricity as described in item 46 of the scope of patent application, where the width of the gap is greater than 5 4 · Dielectric layer that is not prone to generate static electricity as described in item 46 of the scope of patent application The dielectric layer is a silicon oxide or fluorine-doped silica glass (FSG) layer formed by a high-density plasma chemical vapor deposition method. 5 5. The dielectric layer that is less prone to static electricity as described in item 46 of the scope of the patent application, wherein the thickness of the dielectric layer is 3000 to 15000A. 56. The dielectric layer that is not prone to static electricity as described in item 46 of the scope of patent application, wherein the deposition method without ion bombardment is a subatmospheric chemical vapor phase 0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd Page 29 1228791 6. Application for patent scope deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical gas without ion bombardment Phase deposition or high density plasma chemical vapor deposition without ion bombardment. 5 7. The dielectric layer that is not prone to static electricity as described in item 46 of the scope of patent application, wherein the material of the top pad dielectric layer includes silicon oxide. 5 8. The dielectric layer that is not prone to static electricity as described in item 46 of the scope of patent application, wherein the top pad dielectric layer is 400 ~ 600A. 0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd page 30