TWI228791B - Stacked dielectric layer suppressing electrostatic charge buildup and method of fabricating the same - Google Patents
Stacked dielectric layer suppressing electrostatic charge buildup and method of fabricating the same Download PDFInfo
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12287911228791
五、發明說明(1) 發明所屬之技術領域 本發明係有關於一種半導體製程技術’且特別是有關 於一種不易產生靜電之介電層及其製造方法。 先前技術 隨著半導體技術的演進,半導體集積度不斷增加,單 一晶片内的元件數量也不斷增加,必須採用更多多層内連 導線層,而各層内連導線層之間便需要填充良好電性隔離 材料,即所謂的金屬層間介電層(inter-level metal d i e 1 e c t r i c ; I M D ),而以適當化學氣相沈積法形成的氧化 矽便是常見的金屬層間介電層材料。為了改善介電層特 性,並且符合不同應用之特殊需求,有許多關於介電層製 程的相關研究。V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a semiconductor process technology ', and more particularly to a dielectric layer which is less prone to static electricity and a method for manufacturing the same. With the advancement of semiconductor technology, the degree of semiconductor accumulation has continued to increase, and the number of components in a single chip has also increased. More multilayer interconnect wire layers must be used, and good electrical isolation must be filled between the interconnect wire layers. The material is the so-called inter-level metal die layer (IMD), and silicon oxide formed by an appropriate chemical vapor deposition method is a common metal interlayer dielectric material. In order to improve the characteristics of the dielectric layer and meet the special needs of different applications, there are many related studies on the dielectric layer process.
Lee等人所公開之美國專利第5, 60 5, 859號,便揭示— 種以電漿增進式化學氣相沈積法(p 1 a s m a e n h a n c e d chemical vapor deposition; PECVD)形成一介電層於多 晶矽表面的方法。US Patent No. 5,60 5, 859 published by Lee et al., Discloses a method for forming a dielectric layer on the surface of polycrystalline silicon by plasma enhanced chemical vapor deposition (PECVD). method.
Jang等人所公開之美國專利第5, 741,740號,則揭示 一種以電漿增進式化學氣相沈積法(plasma enhanced chemical vapor deposition; PECVD)形成一介電層以做 為淺溝槽隔離物的方法,可以使介電.層填充於高深寬比 (high aspect ratio)的溝槽内 。 、 當半導體的集積度越來抽古 ,/ ^ ^ t I 〜爪越咼,溝槽或缺口的沬X比也 〜辰出向密度電漿化學氣相沈積法 越來越大,因此,發展屮古U.S. Patent No. 5,741,740 published by Jang et al. Discloses a method for forming a dielectric layer using plasma enhanced chemical vapor deposition (PECVD) as a shallow trench isolation This method allows the dielectric layer to be filled in trenches with a high aspect ratio. When the accumulation of the semiconductor ancient increasingly pumping, / ^ ^ t I ~ 咼 the pawl, respiratory droplets than the trench or gap X also ~ e to a density plasma chemical vapor deposition growing, therefore, the development of Che ancient
0503-9366twF(nl);tsmc2002-0998;0801;Felicia.ptd0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd
1228791 五、發明說明(2) (high density plasma chemical vap〇r deposition; HDPCVD) ’以提南沈積介電層的填充能力。高密度電漿化 學氣相沈積係在沈積的同時提供一離子轟擊,以餘刻沈積 於溝槽或缺口側壁的介電層,如此一來,便可確保介電層 沿著溝槽或缺口的垂直方向成長,可確保介電層完全填充 溝槽或缺口 ,不會留下空洞。 、1228791 V. Description of the invention (2) (High density plasma chemical vapor deposition; HDPCVD) ′ To improve the filling capacity of the deposited dielectric layer. The high-density plasma chemical vapor deposition system provides an ion bombardment at the same time of deposition to deposit a dielectric layer on the sidewall of the trench or the gap at a later time. In this way, the dielectric layer can be ensured along the trench or the gap Vertical growth ensures that the dielectric layer completely fills the trenches or gaps without leaving voids. ,
Shufflebotham專人所公開之美國專利第6,678 號’便揭示一種以矽烧、氧以及惰性氣體為前驅物,利用 南密度電漿化學氣相》儿積法形成氧化石夕薄膜,以埴斧逢辦 的方法,溝槽的寬度可小於0.5心,且深寬比(上=槽 ratio)可高於 1·5。U.S. Patent No. 6,678, published by Shufflebotham, reveals that a silicon oxide film was formed using silicon densities, oxygen, and inert gases as precursors. Method, the width of the groove can be less than 0.5 centimeters, and the aspect ratio (up = groove ratio) can be higher than 1.5.
Knorr等人所公開之美國專利第6, 531,377號,亦揭示 一種以連續式高密度電漿化學氣相沉積法對高深寬比溝槽 進行填充的方法。 在高密度電漿化學氣相沉積(HDPCVD)的過程中,會以r 離子轟擊餘刻欲被填充之溝槽或缺口的側壁,以使沉積物 以垂直方向成長,因此,HDPCVD所沉積之介電層可具有良 好的溝槽填充能力。然而,高密度電漿化學氣相沉積法在 形成介電層時卻會有引發金屬擠出的問題(meta 1 extrusion issue) ° 請參閱第1圖,首先在半導體基底100上形成圖案化的 金屬層1 0 2。之後’形成順應的概塾介電層(linear dielectric layer)106於金屬層1〇2的表面上。之後,藉 由HDPCVD而沉積一介電層108於襯塾介電層1〇2上,並填滿Knorr et al., U.S. Patent No. 6,531,377, also discloses a method for filling high aspect ratio trenches by a continuous high-density plasma chemical vapor deposition method. In the process of high-density plasma chemical vapor deposition (HDPCVD), the side walls of trenches or gaps to be filled are bombarded with r ions to make the deposits grow in a vertical direction. Therefore, the media deposited by HDPCVD The electrical layer may have good trench filling capabilities. However, the high-density plasma chemical vapor deposition method has a meta 1 extrusion issue when forming a dielectric layer. Referring to FIG. 1, a patterned metal is first formed on the semiconductor substrate 100. Layer 1 0 2. After that, a compliant linear dielectric layer 106 is formed on the surface of the metal layer 102. Thereafter, a dielectric layer 108 is deposited on the liner dielectric layer 102 by HDPCVD and filled.
0503-93661wF(η 1);t smc2002-0998;0801;Fe1i c i a.ptd 第 8 頁 1228791 五 發明說明(3) 金屬層102中的缺口。由於HDPCVD製程中的離子轟擊的殘 留物或是轟擊離子會打斷部分介電層之鍵結,會導致介電 層1 08中有些許帶電粒子的產生。接著,為了清除介電層 108表面的雜質而採用一沖洗程4S100(water scurbbin0g)0503-93661wF (η 1); t smc2002-0998; 0801; Fe1i c i a.ptd page 8 1228791 V. Description of the invention (3) A gap in the metal layer 102. Residues from ion bombardment or bombarded ions in the HDPCVD process may break the bonding of some dielectric layers, which may cause some charged particles in the dielectric layer 108 to be generated. Next, in order to remove impurities on the surface of the dielectric layer 108, a rinse process 4S100 (water scurbbin0g) is used.
來清除該HDPCVD製程所產生的雜質,其通常係利用一沖洗 機台(jet scrubber),以3〜6。傾斜角度,提供一去離子 水(distil water)清洗介電層108的表面,此時,由於去 離子水摩擦介電層108表面,因而導致介電層1〇8表面會被 感應出大量靜電電荷(electrostatic charges) 2 0 0,而這 些靜電電荷20 0會對介電層1〇8下方的金屬層1〇6形成一拉。 力,而引發金屬擠出1 〇6a的問題。 發明内容 本I月之目的之一在於提供一種不易產生靜電之介電 層及其製造方法’以避免因為沖洗程序使介電層表面附近 被感應出大量靜電電荷而造成的金屬擠出問題。To remove the impurities generated in the HDPCVD process, a jet scrubber is usually used for 3 ~ 6. The inclination angle provides a deil water to clean the surface of the dielectric layer 108. At this time, as the deion water rubs the surface of the dielectric layer 108, a large amount of electrostatic charges are induced on the surface of the dielectric layer 108. (Electrostatic charges) 2 0, and these electrostatic charges 20 0 will form a pull on the metal layer 10 6 below the dielectric layer 108. Force, which causes the problem of metal extrusion 106a. SUMMARY OF THE INVENTION One of the objectives of this month is to provide a dielectric layer which is less prone to generate static electricity and a method of manufacturing the same 'to avoid the problem of metal extrusion caused by a large amount of electrostatic charge induced near the surface of the dielectric layer due to the washing process.
本f明之第一主要特徵在於藉由在具有良好溝槽填 能力的高密度電漿化學氣相沈積介電層表面形成一頂部 螯介電層’該頂部襯墊介電層的沈積過程中並不提供離 轟擊肖以避免大里帶電粒子的產生,如此便可有效避 後續沖洗程序時因水和介電層之間的摩擦所感應出的大 靜電電何,進而抑制金屬擠出的問題發生。 J,日:之第—主要特徵在於針對具有良好溝槽填充 力的“度電^學氣相沈積介電層進行〆電漿處理程The first main feature of this invention is that by forming a top chelated dielectric layer on the surface of a high-density plasma chemical vapor deposition dielectric layer with good trench filling capability, the top liner dielectric layer is deposited during the deposition process and It does not provide the Li Xiao to avoid the generation of charged particles, so it can effectively avoid the large static electricity induced by the friction between the water and the dielectric layer during the subsequent washing process, thereby suppressing the problem of metal extrusion. J, J: No.1—The main feature is the process of dysplasma treatment for "degree of electrical vapor deposition dielectric layer" with good trench filling force.
1228791 五、發明說明(4) 序’藉由透過低功率電漿處理程序所導入的離子及/或電 荷來消除介電層内的電荷,如此便可有效避免後續沖洗程 序時因水和介電層之間的摩擦所感應出的大量靜電電荷, 進而抑制金屬擠出的問題發生。 ♦ 為獲致上述目的,本發明提出一種不易產生靜電之介 電層的製造方法,該方法的步驟主要包括: 首先,提供一基底,其中該基底表面具有一金屬層, 且該金屬層中具有複數缺口。接著,形成一介電層,以覆 盍於該金屬層表面且填滿該複數缺口。最後,藉由低功率 電漿處理程序導入離子及/或電荷於該介電層内,用以消 除介電層内的電荷。 根據本發明,前述方法可適用於缺口之線寬小於〇 . 1 5 //m之半導體介電層製程。 根據本發明’該離子及/或電荷係藉由一電漿處理程 序而導入該介電層内。其中,該電漿處理程序所採用之氣 體可包括氮氣(n2)、氧氣(〇2)、一氧化二氮(N2〇)、氦氣 (He)、氖氣(Ne)、氬氣(Ar)、氪(Kr)、氤(xe)或氡(Rn)。 A電桌處理私序之細作條件包括·反應器(c h a m b e r)内壓 力大體為2〜10torr,所採用之氣體的流量約為 30 0〜500sccm,電源功率(RF Power)約為2〇〜5 0 0W,其偏壓 功率(Bias Power)約為〇〜5 0 0W。,施行時間約為5〜6〇秒。 如前所述’該金屬層之材質包括銅(Cu)、铭(Ai)或銅 鋁合金(Cu/Al al loy)。 如前所述’形成該介電層之前更可包括順應性形成一1228791 V. Description of the invention (4) Sequence 'The charge in the dielectric layer is eliminated by the ions and / or charges introduced by the low-power plasma processing program, so that water and dielectricity can be effectively avoided during subsequent washing procedures. A large amount of electrostatic charge is induced by the friction between the layers, thereby suppressing the problem of metal extrusion. ♦ In order to achieve the above object, the present invention proposes a method for manufacturing a dielectric layer that is not prone to generate static electricity. The steps of the method mainly include: First, providing a substrate, wherein the surface of the substrate has a metal layer, and the metal layer has a plurality of gap. Next, a dielectric layer is formed to cover the surface of the metal layer and fill the plurality of gaps. Finally, a low-power plasma processing program is used to introduce ions and / or charges into the dielectric layer to eliminate the charges in the dielectric layer. According to the present invention, the foregoing method can be applied to a semiconductor dielectric layer process with a notch line width less than 0.15 // m. According to the present invention ', the ions and / or charges are introduced into the dielectric layer by a plasma processing procedure. The gas used in the plasma treatment process may include nitrogen (n2), oxygen (〇2), nitrous oxide (N20), helium (He), neon (Ne), and argon (Ar). , 氪 (Kr), 氤 (xe), or 氡 (Rn). The detailed conditions for processing the private sequence by A electric table include: The pressure in the chamber is generally 2 to 10 torr, the flow rate of the gas used is about 30 0 to 500 sccm, and the power of the power (RF Power) is about 20 to 50. 0W, and its Bias Power is about 0 ~ 500W. The execution time is about 5 ~ 60 seconds. As described above, the material of the metal layer includes copper (Cu), indium (Ai), or copper aluminum alloy (Cu / Al al loy). As mentioned previously, before forming the dielectric layer, it may further include conformable
0503-9366twF(nl);tsmc2002-0998;0801;Felicia.ptd 第 1〇 頁 1228791 五、發明說明(5) 底部襯墊介電層於該金屬表面與該缺口内。 如前所述’該介電層之材質可肖枯 璃(fluorinated silica glass ;FSG)。矽或摻氟矽玻 、-方Ϊ者此=出一種不易產生靜電之介電層的製 造方法,此方法的步驟主要係包括: 首先,提供-基底,其中該基底表面具有一金屬層, 且該金屬層中具有複數缺口。才妾著,藉由具有離子爲擊的 沉積法形成一介電層覆蓋於該金屬層且填滿該缺口。最 後,以不具離子轟擊之沉積法形成一頂部襯墊介電層於該 介電層表面。 根據本^明’ 5亥方法可適用於缺口之線寬大於〇 · 1 5 # m之半導體介電層製程。 如前所述,形成該介電層之前更包括:順應性形成一、 底部襯墊介電層於该金屬層表面與該缺口内。其中,該底 部襯墊介電層係利用不具離子轟擊之沉積法所形成。該不 具離子轟擊之沉積法包括:次大氣壓化學氣相沉積 (sub atmospheric pressure thermal chemical vapor deposition ’SACVD)、常壓化學氣相沉積(atm0Spheric pressure chemical vapor deposition ;APCVD)、低壓化 學氣相沉積(low pressure chemical vapor deposition ;LPCVD)、不提供離子轟擊之電漿增進式化學 氣相沉積(plasma enhanced chemical vapor deposition without ions bombardment ; PECVD without ions bombardment)以及不提供離子義擊之高密度電聚化學氣相0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd Page 10 1228791 V. Description of the invention (5) The bottom pad dielectric layer is on the metal surface and in the notch. As described above, the material of the dielectric layer may be fluorinated silica glass (FSG). Silicon or fluorine-doped silicon glass,-squares are = a method for manufacturing a dielectric layer that is not prone to generate static electricity. The steps of this method mainly include: first, providing a substrate, wherein the surface of the substrate has a metal layer, and The metal layer has a plurality of notches. It is difficult to form a dielectric layer to cover the metal layer and fill the gap by a deposition method with ion strike. Finally, a top liner dielectric layer is formed on the surface of the dielectric layer by a deposition method without ion bombardment. According to this method, the method can be applied to the process of manufacturing a semiconductor dielectric layer with a notch line width greater than 0. 15 #m. As described above, before forming the dielectric layer, the method further includes: compliantly forming a bottom pad dielectric layer on the surface of the metal layer and in the gap. The bottom pad dielectric layer is formed by a deposition method without ion bombardment. The deposition method without ion bombardment includes: sub atmospheric pressure thermal chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), and low pressure chemical vapor deposition (low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition without ions bombardment; PECVD without ions bombardment, and high-density electropolymerized chemical vapor phases that do not provide ion bombardment
0503-9366twF(nl);tsmc2002-0998;0801;Felicia.ptd 第 11 頁 1228791 五、發明說明(6) 沉積(high density plasma chemical vapor deposition without ions bombardment i HDPCVD without ions bombardment)。該底部襯墊介電層厚度大約為20 0〜400 A,材質可包括氧化矽。 如前所述,該金屬層之材質包括銅(Cu )、鋁(A1)或銅 鋁合金(Cu/Al alloy)。 如前所述,該介電層係利用高密度電漿化學氣相沉積 法(HDPCVD)所形成,其材質可為氧化矽或摻氟矽玻璃,其 厚度大體為30 0 0〜1 50 0 0 A。0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd page 11 1228791 V. Description of the invention (6) Deposition (high density plasma chemical vapor deposition without ions bombardment i HDPCVD without ions bombardment). The thickness of the bottom pad dielectric layer is about 200-400 A, and the material may include silicon oxide. As mentioned above, the material of the metal layer includes copper (Cu), aluminum (A1), or copper / aluminum alloy (Cu / Al alloy). As mentioned above, the dielectric layer is formed by high-density plasma chemical vapor deposition (HDPCVD), and the material can be silicon oxide or fluorine-doped silicon glass, and its thickness is generally 30 0 0 to 1 50 0 0 A.
如前所述,形成該頂部襯墊介電層之不具離子轟擊之 沉積法包括:次大氣壓化學氣相沉積(SACVD)、常壓化學氣 相沉積(APCVD)、低壓化學氣相沉積(LpcvD)、不提供離子 義擊之電漿增進式化學氣相沉積(PECVD with〇ut i〇ns bombardment)以及不提供離子轟擊之高密度電漿化學氣相 沉積(HDPCVD without ions bombardment)。其中,該頂 部襯墊介電層之材質包括氧化矽,,其厚度大體為4〇〇〜6〇〇 A 〇 經由上述本發明方法,本發明亦提出一種不易產生靜 :之’!電㉟’主要係包括:一基底:一金屬層,設置於該 :底表面且具有複數缺口;—介電層,覆蓋於該金屬層且 J滿=口;“及一頂部襯墊介電層,形成於該介電層表 二中该頂部襯墊介電層係利用不具離子轟擊之沉積法 所形成。 本^月又提出-種不易產生靜電之介電層,主要係包As mentioned above, the deposition methods without ion bombardment to form the top liner dielectric layer include: sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LpcvD) 2. Plasma-enhanced chemical vapor deposition (PECVD with 0ut ioons bombardment) that does not provide ion bombardment and HDPCVD without ions bombardment that does not provide ion bombardment. Wherein, the material of the dielectric layer of the top liner includes silicon oxide, and its thickness is approximately 400 ~ 600 A. Through the above method of the present invention, the present invention also proposes a kind of static electricity that is not easy to produce: ′! The "electric capacitor" mainly includes: a substrate: a metal layer disposed on the bottom surface and having a plurality of notches; a dielectric layer covering the metal layer and J = = mouth; "and a top pad dielectric layer The top liner dielectric layer formed in the dielectric layer Table 2 is formed by a deposition method without ion bombardment. This month, a new type of dielectric layer that is not easy to generate static electricity is mainly proposed.
1228791 五、發明說明(7) " -- 括 基底·一金屬層,設置於該基底表面且具有複數缺 二;以及一介電層,覆蓋於該金屬層且填滿該缺口,其中 ^介電層係被電漿處理過,用以消除原來的介電層内的電 荷。 為使本發明之該目的、特徵和優點能更明顯易懂,下 文特舉較佳貫施例,並配合所附圖式,作詳細說明如下: 實施方 實 以 說明根 首 圖案化 有複數 或銅鋁 可能包 容器或 用於缺 例,但 接 應的底 其中, 所形成 氣相沉 式 施例1 下凊配合參考第2A圖至第2D圖之製程剖面圖,用以 據本發明之第一實施例。 先,請參照第2 A圖,提供一基底2 〇 〇,並且形成一 的金屬層202於基底200表面,且該金屬層202中具 缺口 204。金屬層202之材質例如是銅(Cu)、鋁(A1) 合金(Cu/Al alloy),較佳為銅。另外,基底2〇〇中 括所需之半導體元件(未圖示),例如:電晶體、電 任何習知之半導體元件。本發明之第一實施例係以 口之線寬dl大於〇·15 //m之半導體介電層製程為 並非限定本發明。 著,請參照第2B圖,順應性((3〇11『 〇 r m a 1)形成一順 部襯墊介電層206於金屬層202表面與缺口 204内。 底部襯墊介電層2 0 6係利用不具離子轟擊之沉積法 。所謂不具離子轟擊之沉積法可以是次大氣壓v化學 積(sub-atmospheric pressure thermal chemical1228791 V. Description of the invention (7) "-Including a substrate · a metal layer provided on the surface of the substrate and having a plurality of missing two; and a dielectric layer covering the metal layer and filling the gap, wherein ^ 介The electrical layer is treated with a plasma to eliminate the charge in the original dielectric layer. In order to make the purpose, features, and advantages of the present invention more comprehensible, the preferred embodiments are exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: The implementer illustrates that the root pattern is plural or Copper and aluminum may be included in containers or used in the absence of examples, but the corresponding bottom of which is formed in the vapor-sinking type. Example 1 The cross-section view of the process with reference to Figures 2A to 2D is used according to the first of the invention Examples. First, referring to FIG. 2A, a substrate 200 is provided, and a metal layer 202 is formed on the surface of the substrate 200, and the metal layer 202 has a notch 204 therein. The material of the metal layer 202 is, for example, copper (Cu) or aluminum (Cu / Al alloy), and preferably copper. In addition, the substrate 200 includes required semiconductor elements (not shown), such as a transistor, and any conventional semiconductor element. The first embodiment of the present invention does not limit the present invention by using a semiconductor dielectric layer with a line width dl greater than 0.15 / m. For reference, please refer to FIG. 2B. The compliance ((3〇11 『〇rma 1) forms a compliant pad dielectric layer 206 on the surface of the metal layer 202 and the notch 204. The bottom pad dielectric layer 2 0 6 The deposition method without ion bombardment is used. The so-called deposition method without ion bombardment can be sub-atmospheric pressure thermal chemical
0503-9366twF(nl);tsmc2002-0998;0801;Felicia.ptd 第 13 頁0503-9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd page 13
T2287Q1 五、發明說明(8)T2287Q1 V. Description of Invention (8)
vapor deposition ;SACVD)、常壓化學氣相沉積 (atmospheric pressure chemical vapor deposition ; APCVD)、低壓化學氣相沉積(low pressure chemical vapor deposition ;LPCVD)、不提供離子轟擊之電漿增進 式化學氣相沉積(plasma enhanced chemical vapor deposition without ions bombardment ; PECVD without ions bombardment)或不提供離子轟擊之高密度電漿化學 氣相沉積(high density plasma chemical vapor deposition without ions bombardment ; HDPCVD without ions bombardment)。其中較佳為不具離子轟擊 之高密度電漿化學氣相沉積,係可藉由調整成不提供離子 轟擊之偏壓功率來達成。一般來說,習知高密度電漿化學 氣相沉積在沉積的同時會提供一離子轟擊,用以I虫刻形成 於所欲填充之缺口或溝槽側壁的沉積物,如此沉積物便會 沿著缺口或溝槽的垂直方向成長,然而請注意本步驟是採 用不具離子轟擊之沉積方式。本發明之底部襯墊介電層 20 6的較佳實施例便是將該具有金屬層2〇2之基底2〇〇放胃置 於一局欲度電漿化學氣相沉積反應器内,在不提供離子義 擊之偏壓的狀態下進行沉積。底部襯墊介電層2 〇 6之厚度 大約為2 0 0〜4 0 0 A ’材質可包括氧化石夕(例如$丨ο?)。 接著,清參照第2 C圖,同時藉由沉積與離子轟擊(即 採用具有離子義擊的沉積法)’以形成一介電層2〇8覆蓋於 金屬層2 0 2表面且填滿缺口 2 0 4。介電層2 〇 4例如是利用古 密度電聚化學氣相沉積法⑽PCVD)所形成丄以二為vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition without ion bombardment (Plasma enhanced chemical vapor deposition without ions bombardment; PECVD without ions bombardment) or high density plasma chemical vapor deposition without ion bombardment (HDPCVD without ions bombardment). Among them, high-density plasma chemical vapor deposition without ion bombardment is preferably achieved by adjusting the bias power to not provide ion bombardment. Generally speaking, the conventional high-density plasma chemical vapor deposition provides an ion bombardment at the same time as the deposition, which is used to etch the deposits formed on the gaps or trench sidewalls to be filled. It grows in the vertical direction of the notch or trench, but please note that this step uses a deposition method without ion bombardment. The preferred embodiment of the bottom pad dielectric layer 20 6 of the present invention is to place the substrate 200 with the metal layer 200 in a stomach of a plasma chemical vapor deposition reactor. The deposition was performed without providing the bias of the ion strike. The thickness of the bottom pad dielectric layer 206 is approximately 2000 to 400 A. The material may include oxide stone (eg, $ 丨 ο?). Next, referring to FIG. 2C, a dielectric layer 208 is formed to cover the surface of the metal layer 202 and fill the gap 2 by deposition and ion bombardment (that is, using a deposition method with ion bombardment). 0 4. The dielectric layer 204 is, for example, formed by using a pale-density electropolymerization chemical vapor deposition method (PCVD).
1228791 五、發明說明(9) 繼績將基底200放置於前述形成底部襯墊介電層2〇6之高密 度電漿化學氣相沉積反應器内部,於提供一離子轟擊偏壓 之狀恶下,進行介電層2 0 8之沉積,如此介電層2 〇 8便會沿 著缺口 2 04之垂直方向沉積成長,所以高密度電漿化學氣 相沉積所形成之介電層2 〇 8可具有良好的溝槽填充能力。 然而,由於傳統HDPCVD製程中的離轟擊的殘留或是轟擊離 子會打斷部分介電層208之鍵結,沉積後之介電層2〇8中會 產生些ό午τ電粒子。在習知技術中,這些帶電粒子(電荷) 會在後績冲洗程序(water scrubbing)時,使介電層2〇8表 面感應出大量靜電電荷,因而引發習知金屬擠出的S問題。 其中,該介電層2 08之材質可為氧化矽(例如。〇2)或摻氟矽 玻璃’其厚度大體為3000〜15000A。高密度電漿化學氣相 沉積之操作條件例如包括有:電源功率(RF p〇wer)約為 2 0 0 0 〜450 0watts,偏壓功率(Bias Power)約為 2000〜4500watts,其前驅物包括石夕烧(saiine)和氧氣,於 壓力約為0〜ltorr,溫度約為200〜7〇〇°C下。1228791 V. Description of the invention (9) Following the performance, the substrate 200 was placed inside the high-density plasma chemical vapor deposition reactor forming the bottom pad dielectric layer 206, under the condition of providing an ion bombardment bias. The dielectric layer 208 is deposited, so that the dielectric layer 208 will be deposited and grown along the vertical direction of the notch 204, so the dielectric layer 208 formed by the high-density plasma chemical vapor deposition can be Has good trench filling ability. However, due to the residual bombardment or bombardment ions in the traditional HDPCVD process, some of the bonding of the dielectric layer 208 will be interrupted, and there will be some electrical particles in the deposited dielectric layer 208. In the conventional technology, these charged particles (charges) cause a large amount of electrostatic charges to be induced on the surface of the dielectric layer 20 during a water scrubbing process, thereby causing the S problem of conventional metal extrusion. Wherein, the material of the dielectric layer 208 may be silicon oxide (for example, 〇2) or fluorine-doped silicon glass, and its thickness is generally 3000 ~ 15000A. Operating conditions for high-density plasma chemical vapor deposition include, for example: power supply (RF power) of about 20000 ~ 4500 watts, bias power (Bias Power) of about 2000 ~ 4500 watts, its precursors include Saisai and oxygen are under a pressure of about 0 ~ ltorr and a temperature of about 200 ~ 700 ° C.
接著,請參照第2D圖,以不具離子轟擊之沉積法形成 一頂部襯墊介電層210於介電層208表面。形成頂部襯墊介 電層2 1 0之不具離子轟擊之沉積法可以是次大氣壓化學氣 相沉積(SACVD)、常壓化學氣相沉積(APCVD)、低壓化學氣 相沉積(LPCVD)、不提供離子轟擊之電漿增進式化學氣相 沉積(PECVD without ions bombardment)以及不提供離子 轟擊之高密度電漿化學氣相沉積(HDPCVD with〇ut iQns bombardment),其中較佳為不提供離子轟擊之高密度電漿Next, referring to FIG. 2D, a top liner dielectric layer 210 is formed on the surface of the dielectric layer 208 by a deposition method without ion bombardment. The deposition method without ion bombardment to form the top liner dielectric layer 2 10 can be sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), not provided Plasma enhanced chemical vapor deposition (PECVD without ions bombardment) for ion bombardment and high-density plasma chemical vapor deposition (HDPCVD with 〇ut iQns bombardment) that does not provide ion bombardment, of which the height without ion bombardment is preferred Density plasma
1228791 五、發明說明(10) ^-- 化學氣相沉積。較佳實施例為繼續將製備完介電層2 基底20 0放置於一高密度電漿化學氣相沉積反應器胃内,= 不提供離子轟擊之偏壓的狀態下進行沉積。頂部概’入 層2 1 0之材質可以是氧化矽(例如s丨% ),其厚度大 ;丨電 400〜600 A 。 為1228791 V. Description of the invention (10) ^-Chemical vapor deposition. In a preferred embodiment, the dielectric layer 2 and the substrate 200 are continuously placed in the stomach of a high-density plasma chemical vapor deposition reactor, and the deposition is performed without providing a bias voltage for ion bombardment. The material of the top layer 2 10 may be silicon oxide (for example, s 丨%), and its thickness is large; 400-600 A. for
請參閱第2D圖,本發明之避免金屬自介電層中 結構主要包括:基底2〇〇、金屬層2〇2、介電層2〇8 出的 部襯墊介電層210。金屬層202設置於基底2〇〇表面,及頂 有複數缺口 204。介電層208覆蓋於金屬層2〇2且填^具 204。頂部襯墊介電層21〇則形成於介電層2〇8表面γ缺口 頂部襯墊介電層2 1 0係利用不具離子轟擊之沉積法其中 成。另外’金屬層202與介電層208之間,可更形成% 部襯墊介電層206。 有一底 最後’施行一沖洗程序(water scrubbing,未 於整個堆疊介電層表面,用以除去整個堆疊介電層^ = 雜質。可利用一沖洗機台(jet scrubber),以大二3面/Referring to FIG. 2D, the structure for avoiding the metal from the dielectric layer of the present invention mainly includes: a pad dielectric layer 210 from the substrate 200, the metal layer 202, and the dielectric layer 208. The metal layer 202 is disposed on the surface of the substrate 200 and has a plurality of notches 204 at the top. The dielectric layer 208 covers the metal layer 202 and is filled with a mold 204. The top liner dielectric layer 21 is formed on the surface of the dielectric layer 208 with a γ notch. The top liner dielectric layer 2 10 is formed by a deposition method without ion bombardment. In addition, a portion of the pad dielectric layer 206 may be further formed between the metal layer 202 and the dielectric layer 208. There is a bottom. Finally, a water scrubbing (water scrubbing) is performed on the entire surface of the stacked dielectric layer to remove the entire stacked dielectric layer ^ = impurities. A jet scrubber can be used to use the sophomore 3 side /
傾斜角度,提供一去離子水(distil water)清洗頂部襯 介電層2 1 0,此時,雖然去離子水會摩擦頂部襯墊介電層 210表面,但是相較於習知之HDPCVD所沉積之介電層丨㈣曰, 根據本發明之由不具離子轟擊之沉積法所形成的頂部襯考 介電層210,因為頂部襯墊介電層21〇不具有大量帶電粒巧 (電荷),所以在進行沖洗程序時,頂部襯墊介電層21〇表 面也不容易被引發出大量靜電電荷’如此就能夠有效避角 由於靜電電荷的引力所造成之習知金屬擠出問題。The inclination angle provides a deil water to clean the top liner dielectric layer 210. At this time, although the deionized water rubs the surface of the top liner dielectric layer 210, compared to the conventional HDPCVD deposition Dielectric layer: The top liner dielectric layer 210 formed by the deposition method without ion bombardment according to the present invention, because the top liner dielectric layer 21 does not have a large number of charged particles (charges), so When the flushing process is performed, the surface of the top pad dielectric layer 21 is not easily caused by a large amount of electrostatic charges, so that it can effectively avoid the conventional metal extrusion problem caused by the electrostatic charge.
1228791 五、發明說明(11) 根據本發明第一實施例 優點: 迷方法與結構’其具有以下 1 ·根據本發明之堆疊介 ^ 氣相沉積之介電層208 曰匕括-南密度電裝化學 2.根據本發明之堆疊;^7\好的溝槽填充能力。 210,沉積過程中並無提 日中^括—頂部襯塾介電層 層210中不會有大量帶電;::轟擊,因此頂部襯墊介電 中減少感應靜電大電 7:產板二 出問題。 因而有效避免習知的金屬擠 3 ·根據本發明之堆疊介 2〇6、介電層208以为TSAR 層包括底部襯墊介電層 以麩由古一痒+ 頁邛襯電介電層210,各層的形成可 J : “、度電漿化學氣相沉積法成 不提供離子轟擊,僅於頂部襯電介電層210時 如此可.積,丨電層208時提供離子轟擊, 如此可以6^^Qn-sUu)沉積堆聂介 說,能夠在同一沉積裝置中^ a ^ 9疋 21〇之沉積。 積衣置中元成该等介電層20 6、208與 實施例2 隼積ΐΠΐϊ程ί術發展到線寬是〇.15_以下後,高 前述第-實施例方法所額外子傳輸速度,然而, 增加了整體介電層之阻值,部襯電介電層210會 電子傳輸速度。-因A,本笋遲緩的增加,降; 之介電層的製造方法。…U另一種不易產生靜電1228791 V. Description of the invention (11) Advantages according to the first embodiment of the present invention: The method and structure have the following features: 1. The stacked dielectric according to the present invention ^ vapor-deposited dielectric layer 208. Chemistry 2. Stacking according to the present invention; ^ 7 \ good trench filling ability. 210, there is no mention during the deposition process-there will not be a lot of charge in the top lining dielectric layer 210 :: bombardment, so the induced static electricity in the top pad dielectric is reduced. problem. Therefore, the conventional metal extrusion is effectively avoided3. According to the present invention, the stacked dielectric 206, the dielectric layer 208, the TSAR layer including the bottom pad dielectric layer, and the dielectric layer 210 are lined with a sheet of silicon, The formation of each layer can be J: "The plasma chemical vapor deposition method does not provide ion bombardment, which is only possible when the dielectric layer 210 is lined on the top, and ion bombardment is provided when the electric layer 208 is provided. ^ Qn-sUu) Deposition stack Nie Jie said that it can be deposited in the same deposition device ^ a ^ 9 疋 21〇. The product is placed in the dielectric layers 20 6,208 and Example 2 After the development of the line width is less than 0.15_, the extra sub-transmission speed of the method of the first embodiment is increased, however, the resistance value of the overall dielectric layer is increased, and the electron-transmission speed of the lined dielectric layer 210 will be increased. .-Because of A, the bamboo shoots slowly increase and decrease; the manufacturing method of the dielectric layer .... U another is not easy to generate static electricity
1228791 五、發明說明(12) 以下請配合參考第3 A圖至第3 D圖之製程剖面圖,說明 根據本發明之第二實施例。 首先,請參照第3 A圖,提供一基底3 〇 〇,並且形成一 圖案化的金屬層302於基底300表面,且金屬層302中具有 複數缺口 3 0 4。金屬層3 0 2之材質可包括銅(Cu)、鋁(A丨)或 銅鋁合金(Cu/Al alloy),較佳為銅。另外,基底3〇〇中可 能包括所需之半導體元件(未圖示),例如:電晶體、電容 器或任何習知之半導體元件。本發明之第二實施例係以用 於缺口 304之線寬d2小於〇. 1 5 之半導體介電層製程為 例,但並非限定本發明。 接著’ 4爹照第3B圖’順應性((:〇]1]^〇1^111&11乂)形成一 底部襯墊介電層30 6於金屬層302表面與缺口3〇4内。其 中,底部襯墊介電層3 0 6係利用適當的化學氣相沉積法 (chemical vapor deposition ; CVD)形成,包括:次大氣 壓化學氣相沉積(SACVD)、常壓化學氣相沉積(ApcvD)、 低壓化學氣相沉積(LPCVD)、電漿增進式化學氣相沉積 (PECVD)以及高密度電漿化學氣相沉積(HDpcVD)。其中該 底部襯墊介電層30 6之厚度大約為2 〇〇〜4〇〇 A,材質可/ 化矽(例如S i 02)。 、 . 接著,請參照第3C圖,以形成一介電層3〇8,覆蓋於 金屬層302表面且填滿缺口 304。介電層3〇4例如是利用高 始、f電漿化學氣相沉積法(HDPCVD)所形成,高密度電漿化 學氣相沉積法在沉積介電層3〇4時會同時提供一離子蟲 擊,使介電層304會沿著缺口 3〇4之垂直方向沉積成長,因1228791 V. Description of the invention (12) The following is a description of a second embodiment according to the present invention with reference to the cross-sectional views of the processes of FIGS. 3A to 3D. First, referring to FIG. 3A, a substrate 300 is provided, and a patterned metal layer 302 is formed on the surface of the substrate 300, and the metal layer 302 has a plurality of notches 304. The material of the metal layer 3 0 2 may include copper (Cu), aluminum (A 丨), or copper / aluminum alloy (Cu / Al alloy), preferably copper. In addition, the substrate 300 may include a required semiconductor element (not shown), such as a transistor, a capacitor, or any conventional semiconductor element. The second embodiment of the present invention takes the semiconductor dielectric layer process for the notch 304 with a line width d2 of less than 0.15 as an example, but it is not limited to the present invention. Then, the “4D photo according to FIG. 3B” compliance ((: 〇] 1] ^ 〇1 ^ 111 & 11 乂) forms a bottom pad dielectric layer 306 on the surface of the metal layer 302 and in the gap 304. Among them The bottom pad dielectric layer 306 is formed using a suitable chemical vapor deposition (CVD) method, including: sub-atmospheric pressure chemical vapor deposition (SACVD), atmospheric pressure chemical vapor deposition (ApcvD), Low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and high density plasma chemical vapor deposition (HDpcVD). The thickness of the bottom pad dielectric layer 306 is approximately 200. ~ 400A, the material can be siliconized (for example, Si 02). Then, please refer to FIG. 3C to form a dielectric layer 308 covering the surface of the metal layer 302 and filling the gap 304. The dielectric layer 304 is formed, for example, by using high-frequency, f-plasma chemical vapor deposition (HDPCVD). The high-density plasma chemical vapor deposition method simultaneously provides an ion worm when depositing the dielectric layer 304. The dielectric layer 304 will be deposited and grown along the vertical direction of the gap 304, because
1228791 五、發明說明(13) 此以高密度電漿化學氣相沉積所形成之介電層3〇8可具有 良好的溝槽填充能力。然而,傳統HDpcvD製程中由於離 擊的殘留或是轟擊離子會打斷部分介電層3〇8之鍵結、,沉 積後之介電層308中會產生些許帶電粒子(電荷)。在習知 技術中,這些帶電粒子會在後續沖洗程序(〜以冗 scrubbing)時,使介電層3〇8表面感應出大量靜電電荷, 因而引發金屬擠出的問題。介電層3〇8之材質可包括氧化 矽(例如Si〇2)或摻氟矽玻璃(flu〇rinated siUca giass ; FSG),其厚度大體為3000〜15〇〇〇a。高密度電漿化學氣相 沉積之操作條件例如包括有··電源功率(RF p〇wer)約為 20 0 0 〜4500watts,偏麼功率(Bias P〇wer)約為 2 0 0 0〜4 5 0 0 w a t’t s,其前驅物包括石夕烧(s a 1丨n e \和氧氣,於 壓力約為0〜ltorr,溫度約為200〜7〇〇°c下。 接著進行本實施例的重點步驟,請參照第3D圖,藉由 對介電層308進行一低功率電漿處理程序S3〇〇,導入離子 (包含正負電的離子)及/或電荷(包含正負電的電荷)於介 電層308内,而使介電層308中的電荷被中和 (neutralized)或放出(discharge),其中以離子(包含正 負電的離子)為主。其中,該低功率電漿處理程序S3〇〇所 採用之氣體可為氮氣(N2)、氧氣(〇2)、一氧化二氮(n2〇)、 氦氣(He)、氖氣(Ne)、氬氣(Ar)、氪(κΓ)、氤(Xe)或氡 (R η)。進行低功率電漿處理程序S 3 0 〇時反應器内壓力大體 為2〜lOtorr,所採用之氣體的流量約為3〇〇〜5〇〇sccm,電 源功率(RF Power)約為20〜5 00W,最佳為5〇w,其偏壓功率1228791 V. Description of the invention (13) The dielectric layer 308 formed by high-density plasma chemical vapor deposition can have good trench filling ability. However, in the traditional HDpcvD process, due to the residual ion or bombarded ions, some of the dielectric layers 308 will be broken, and some charged particles (charges) will be generated in the deposited dielectric layer 308. In the conventional technology, these charged particles will cause a large amount of electrostatic charge to be induced on the surface of the dielectric layer 308 during the subsequent washing process (~ redundant scrubbing), thereby causing the problem of metal extrusion. The material of the dielectric layer 308 may include silicon oxide (such as SiO 2) or fluorine-doped silicate glass (fluorated siUca giass; FSG), and its thickness is generally 3,000 to 150,000 a. Operating conditions for high-density plasma chemical vapor deposition include, for example, power supply power (RF power) of about 200 0 to 4500 watts, and bias power (Bias power) of about 2 0 0 0 to 4 5 0 0 wa t't s, the precursors of which include Shi Xiyao (sa 1 ne ne \ and oxygen, at a pressure of about 0 to ltorr, and a temperature of about 200 to 700 ° C.) For important steps, please refer to FIG. 3D. By performing a low-power plasma processing procedure S300 on the dielectric layer 308, introducing ions (including positively and negatively charged ions) and / or charges (including positively and negatively charged charges) into the dielectric Within the electrical layer 308, the charges in the dielectric layer 308 are neutralized or discharged, among which ions (positive and negative ions) are the main ones. Among them, the low-power plasma processing program S3. 〇The gas used can be nitrogen (N2), oxygen (〇2), nitrous oxide (n2〇), helium (He), neon (Ne), argon (Ar), krypton (κΓ), Krypton (Xe) or Krypton (R η). When the low-power plasma treatment program S 300 is performed, the pressure in the reactor is generally 2 to 10 Torr. Flow of about 3〇〇~5〇〇sccm, electrical power source (RF Power) about 20~5 00W, most preferably 5〇w which bias power
0503-9366twF(η 1);t smc2002-0998;0801;Fe1i ci a.ptd 第 19 頁 1228791 五、發明說明(14) " "" * (Bias P〇wer)約為〇〜5〇〇w,施行時間約為5〜6〇秒。根據本 發明’經過該低功率電漿處理程序s3〇〇後,可以有效消除 介電層308内部的帶電粒子。 接著,便可以施行後續的沖洗程序(water scrubbing,未圖示)於介電層3〇8表面,用以除去介電層 308表面之雜質。例如利用一沖洗機台(彳以scrubber): 二大、力3 6傾斜角度,提供一去離子水清洗頂部襯墊介 ,層210,此時,雖然去離子水會摩擦介電層3〇8表面,但 疋經過本發明之低功率電漿處理程 〇〇 :具有大量帶…’因此介電層3。8表”電層08 感,出大量靜電電荷。經由以RF功率5〇w的“ 降r月經過該電漿處理之介電層的感應靜 电尾壓可由-7 3 V降低至一 1 v,ro 1 1丄 雷雷;Τ μ η丨士私、生上 因而缸明可有效避免由於靜 電電何的引力所造成之金屬擠出問題。 本發明雖以較佳實施例揭露如上,然 本發明的範圍,任何熟習此項 =、非 精神和範圍内,當可做各種的員不:離本發明之 保護範圍當視後附之申請專利範圍;斤;定者::本發明之0503-9366twF (η 1); t smc2002-0998; 0801; Fe1i ci a.ptd page 19 1228791 V. Description of the invention (14) " " " * (Bias Power) is about 0 ~ 5. 〇w, the execution time is about 5 ~ 60 seconds. According to the present invention, after the low-power plasma processing program s300, the charged particles inside the dielectric layer 308 can be effectively eliminated. Then, a subsequent water scrubbing (not shown) can be performed on the surface of the dielectric layer 308 to remove impurities on the surface of the dielectric layer 308. For example, using a washing machine (with scrubber): two large, force 36 tilt angle, provide a deionized water to clean the top pad dielectric layer 210, at this time, although the deionized water will rub the dielectric layer 30 The surface, but after the low-power plasma treatment process of the present invention, it has a large number of bands ... 'Therefore, the dielectric layer 3.8 shows the "electric layer 08 induction, and a large amount of electrostatic charge is generated. By RF power 50w" The induced electrostatic tail voltage of the dielectric layer treated by the plasma treatment can be reduced from -7 3 V to 1 v, ro 1 1 丄 leilei; T μ η 丨 can be effectively avoided by people who are born and born The problem of metal extrusion due to electrostatic attraction. Although the present invention is disclosed as above with the preferred embodiments, the scope of the present invention is not limited. Anyone familiar with this item is not within the spirit and scope. It can be used as a variety of members. The scope of protection of the present invention shall be regarded as the attached patent. Range; catty;
1228791 圖式簡單說明 第1圖係顯示習知技術之金屬擠出於介電層表面之缺 點不·意圖, 第2A圖至第2D圖係顯示根據本發明之不易產生靜電之 介電層的製作方法之一較佳實施例之製程剖面圖;以及 第3A圖至第3D圖係顯示根據本發明之不易產生靜電之 介電層的製作方法之另一較佳實施例之製程剖面圖。 符號說明 106a〜金屬擠出 100 ^ 200 ^ 300 基底; 3 0 2〜金屬層; 缺口; 3 0 6〜底部襯墊介電層; 308〜介電層; 102 、 202 204 、 304 106 > 206 108 、 208 210、310〜頂部概墊介電層; 2 0 0〜靜電電荷; S1 0 0〜沖洗程序; S 3 0 0〜電漿處理程序。1228791 Brief description of the diagram. Figure 1 shows the disadvantages and intentions of the conventional technology of extruding metal on the surface of the dielectric layer. Figures 2A to 2D show the fabrication of a dielectric layer that is not prone to static electricity according to the present invention A process cross-sectional view of a preferred embodiment of the method; and FIGS. 3A to 3D are cross-sectional views of a process of another preferred embodiment of a method for manufacturing a dielectric layer that does not easily generate static electricity according to the present invention. DESCRIPTION OF SYMBOLS 106a ~ Metal extrusion 100 ^ 200 ^ 300 substrate; 3 02 ~ metal layer; notch; 3 06 ~ bottom pad dielectric layer; 308 ~ dielectric layer; 102, 202 204, 304 106 > 206 108, 208, 210, 310 ~ top dielectric layer; 200 ~ electrostatic charge; S100 ~ flushing procedure; S300 ~ plasma processing procedure.
0503,9366twF(nl);tsmc2002-0998;0801;Felicia.ptd 第 21 頁0503,9366twF (nl); tsmc2002-0998; 0801; Felicia.ptd page 21
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