TWI226658B - Method of filling intervals and method of fabricating a shallow trench isolation - Google Patents
Method of filling intervals and method of fabricating a shallow trench isolation Download PDFInfo
- Publication number
- TWI226658B TWI226658B TW92129093A TW92129093A TWI226658B TW I226658 B TWI226658 B TW I226658B TW 92129093 A TW92129093 A TW 92129093A TW 92129093 A TW92129093 A TW 92129093A TW I226658 B TWI226658 B TW I226658B
- Authority
- TW
- Taiwan
- Prior art keywords
- dielectric layer
- gap
- patent application
- scope
- item
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 111
- 238000002955 isolation Methods 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000000126 substance Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 238000005498 polishing Methods 0.000 claims description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- 229960002050 hydrofluoric acid Drugs 0.000 claims 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 238000007517 polishing process Methods 0.000 abstract 1
- 239000003989 dielectric material Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 5
- 239000012495 reaction gas Substances 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- WQLQSBNFVQMAKD-UHFFFAOYSA-N methane;silicon Chemical compound C.[Si] WQLQSBNFVQMAKD-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910000967 As alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 102100027340 Slit homolog 2 protein Human genes 0.000 description 1
- 101710133576 Slit homolog 2 protein Proteins 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- WZSUOQDIYKMPMT-UHFFFAOYSA-N argon krypton Chemical compound [Ar].[Kr] WZSUOQDIYKMPMT-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009331 sowing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
£26658 * $所屬之技術領 種壤充$明是有關於 f生、充間隙的方法與 【先前技術】 中，在半導體製程中 則稱Z f連結導線與 J二為播塞。其中， iit線直接接觸而發 ^導體元件之間及上 Uin’w所謂之内金屬介 ))加以隔離。 然而，隨著半導 ^來愈小，而使得導 日變大，如此將導致 另一方面，當導體與 =阻值以及導線間的 疋性關鐽之一。因此 有良好的操作速度， 求。介電材料不但要 有好的平坦性。此外 遞’並且具有低的介 一般而言，由於 所沈積的介電層在緻 均優於利用其他的化 域】 一種半導體製程，且特別是有關於一 淺溝渠隔離結構的製造方法。 ，各個元件之連結主要是靠導線。其 積體電路元件及上下兩層導線之部分 為了不讓導線與半導體元件及上下兩 生短路（有插塞之處除外），在導線與 下兩層導線之間必須以介電層（亦 電層（Inter-Metal Dielectrics， 體元 線間 在間 其他 寄生 ，為 對於 可以 ，介 電常 高密 密度 學氣 件集 的間 隙填 導體 電容 了使 導線 完全 電材 數， 度電 、阻 相沈 積度 隙其 入介 間的 大小 尺寸 間的 填入 料還 以減 漿化 隔水 積法 的增 高寬 電材 距離 係為 縮小 介電 導體 要能 少導 學氣 份與 所沈 加，元 比（A s p 料變得 變小時 影響元 的半導 材料就 的間隙 夠阻擋 線間的 相沈積 平坦化 積的介 件的尺寸會 ect Ratio) 比較困難。 ，導線本身 件速度的決 體元件上仍 有一些要 裡，且需具 水分的傳 寄生電容。 法（HDPCVD) 的特性方面 電層，因此£ 26658 * The technical field to which the seed belongs is the method and method of filling gaps and [prior art]. In the semiconductor manufacturing process, the Z f connection wire and J 2 are called sowing plugs. Among them, the IIT line is directly in contact with each other and the conductor elements are isolated from each other and on the Uin'w so-called inner metal dielectric)). However, as the semiconducting conductor becomes smaller and smaller, so that the heliostat becomes larger, this will lead to the other hand, when the resistance between the conductor and the resistance and the nature of the wire is one of the critical concerns. Therefore, there is a good operating speed. Dielectric materials must not only have good flatness. In addition, it has a low dielectric. Generally speaking, because the deposited dielectric layer is better than using other chemical domains] a semiconductor process, and in particular, it relates to a method for manufacturing a shallow trench isolation structure. The connection of various components is mainly by wires. In order to prevent the short circuit between the conductor and the semiconductor element and the upper and lower layers (except where there are plugs), a dielectric layer (also an electrical Layer (Inter-Metal Dielectrics, other parasitic between the voxel lines, in order to fill the conductor capacitance for the gap between the dielectric constant high-density density gas set, so that the number of electrical wires is completely The filling material between the size of the medium and the size of the medium is also increased by the method of dehydration and water separation. The distance between the electrical materials is to reduce the dielectric conductor. The gap of the semiconducting material that affects the element becomes small enough to block the phase deposition between the lines. The size of the media will be ect Ratio.) It is more difficult. There are still some important points on the block element of the wire itself. In addition, the parasitic capacitance of moisture is required.
1226658 —^~----- 、發明說明（2) ^經破廣泛的用於形成填充間隙的氧化物。不過，近年來 於7L件積集度不斷提高，因此導線間的間隙其高寬比愈 / $大。於是，即使利用高密度電漿化學氣相沈積法也不 # ^將間隙完全填滿。亦即在沈積後介電材料層中仍會有 縫隙存在，如此可能會影響後續的製程良率。1226658 — ^ ~ ----- 、 Explanation of the invention (2) ^ A wide range of oxides used to form gap-filling oxides. However, in recent years, the accumulation degree of 7L pieces has been continuously improved, so the gap between the wires has a higher aspect ratio / $. Therefore, even if a high-density plasma chemical vapor deposition method is used, the gap is not completely filled. That is, there will still be gaps in the dielectric material layer after deposition, which may affect the subsequent process yield.
除此之外，上述介電材料無法將間隙填滿的問題亦會 ^生在淺溝渠隔離結構的製程中。當元件積集度愈來愈高 時’係表示各個主動區的範圍愈來愈小，而位於主動區之 間的淺溝渠隔離結構亦會相對地縮小。換言之，溝渠的高 寬比會隨著元件積集度的提高而愈來愈大，因此在進行淺 溝渠隔離結構的製程時，利用高密度電漿化學氣相沈積法 亦不易將介電材料完全填滿溝渠。如此亦可能影響後續製 程的良率。於是，如何將介電材料完整地填滿於間隙内 (或溝渠中）是虽待解決的問題。 【發明内容】 有鑑於此，本發明的目的就是在提供一種填充間隙的 =，以解決習知利用高密度電漿化學氣相沈積法來填充 間隙，卻無法使得介電材料完全填滿間隙之問題。 *去本t = =以供一 _冓渠隔離結構的製造 方法，以解決I知在進行淺溝渠隔離結 料無法填滿溝渠，而使得介電 =^程時；丨電材 題。 π W冤材枓層中存在有縫隙的問 本發明提出一種填充間隙的方法， 基底’且此基底上已形成有複數個凸部 此方法係先提供一 ’而且各個凸部之In addition, the above problem that the dielectric material cannot fill the gap will also occur in the manufacturing process of the shallow trench isolation structure. When the component accumulation degree is getting higher and higher, it means that the range of each active area is getting smaller and smaller, and the shallow trench isolation structure located between the active areas will be relatively reduced. In other words, the aspect ratio of the trenches will become larger and larger with the increase of the component concentration. Therefore, it is not easy to completely use the high-density plasma chemical vapor deposition method to completely complete the dielectric material when manufacturing the shallow trench isolation structure Fill the ditch. This may also affect the yield of subsequent processes. Therefore, how to completely fill the gap (or in the trench) with the dielectric material is a problem to be solved. [Summary of the Invention] In view of this, the object of the present invention is to provide a gap filling = to solve the conventional use of high-density plasma chemical vapor deposition method to fill the gap, but can not make the dielectric material completely fill the gap. problem. * Go to t = = for a manufacturing method of trench isolation structure to solve the problem that I ca n’t fill the trench with shallow trench isolation material, so that the dielectric = ^ process; the problem of electrical materials. The problem of gaps in the π W layer is provided. The present invention proposes a method for filling a gap. The substrate 'has a plurality of convex portions formed on the substrate. This method first provides a' and each of the convex portions
1226658 五、發明說明（3) 間係具有間隙。之後，於基底上形成第一介電層，以填入 這些凸部之間的間隙，並覆蓋這些凸部，其中所形成之第 一介電層中具有數個縫隙，且這些縫隙的位置係高於凸部 的頂部。接著，進行化學機械研磨法，移除部分第一介電 層，以使縫隙打開，而形成數個開口。然後，進行非等向 性蝕刻製程，以擴大這些開口的寬度。繼之，於第一介電 層上形成第二介電層，以填滿開口。 本發明提出另一種填充間隙的方法，此方法係先提供 一基底，且此基底上已形成有至少一第一開口。之後，於 此基底上形成第一介電層，以填入第一開口中，並覆蓋基 底，此第一介電層中具有至少一縫隙，且此縫隙係位於開 口上方且高於基底的表面。接著，移除部分第一介電層， 以使此縫隙打開，而形成一第二開口。然後，移除此第二 開口側壁之第一介電層，以擴大第二開口的寬度。繼之， 於第一介電層上形成第二介電層，以填滿第二開口。 由於本發明在形成第一介電層後，先利用化學機械研 磨法將存在於第一介電層中的縫隙打開，並且之後還利用 非等向性蝕刻擴大開口（或第二開口）的寬度。因此，在後 續形成第二介電層時，可以將開口（或第二開口）完全填 滿，而形成使得各個凸部的間隙（或第一開口）完全填滿介 電材料。 本發明提出一種淺溝渠隔離結構的製造方法，此方法 係先提供一基底，且此基底已形成有圖案化之墊氧化層與 罩幕層以及數個溝渠。之後，於罩幕層上形成第一介電1226658 V. Description of the invention (3) There is a gap between them. Thereafter, a first dielectric layer is formed on the substrate to fill the gaps between the convex portions and cover the convex portions. The formed first dielectric layer has several gaps, and the positions of the gaps are Higher than the top of the protrusion. Next, a chemical mechanical polishing method is performed to remove a portion of the first dielectric layer so that the gap is opened to form several openings. Then, an anisotropic etching process is performed to enlarge the width of these openings. Next, a second dielectric layer is formed on the first dielectric layer to fill the opening. The present invention provides another method for filling a gap. This method first provides a substrate, and at least one first opening has been formed on the substrate. Thereafter, a first dielectric layer is formed on the substrate to fill the first opening and cover the substrate. The first dielectric layer has at least one gap, and the gap is located above the opening and above the surface of the substrate. . Then, a part of the first dielectric layer is removed, so that the gap is opened to form a second opening. Then, the first dielectric layer on the sidewall of the second opening is removed to enlarge the width of the second opening. Then, a second dielectric layer is formed on the first dielectric layer to fill the second opening. After the first dielectric layer is formed in the present invention, a gap existing in the first dielectric layer is first opened by a chemical mechanical polishing method, and then the width of the opening (or the second opening) is enlarged by using anisotropic etching. . Therefore, in the subsequent formation of the second dielectric layer, the opening (or the second opening) can be completely filled, so that the gap (or the first opening) of each convex portion can be completely filled with the dielectric material. The invention provides a method for manufacturing a shallow trench isolation structure. This method first provides a substrate, and the substrate has been formed with a patterned pad oxide layer and a mask layer and a plurality of trenches. After that, a first dielectric is formed on the mask layer.
11978twf.ptd 第9頁 1226658 五、發明說明⑷ 以填入這些溝退 數個縫隙，且這^ 。其中，所形成之第一介電層中具 J;移除部分第一；3的頂部係高於罩幕層的表面。接 ^開口。然後，移除ϊ層，以使這些縫隙打開，而形成數 2 =的寬度。繼之τ=些開口側壁之第一介電層，以擴大 楚滿這些開口。之後；第一介電層上形成第二介電層，以 一介電層。 ’移除這些溝渠以外之第一介電層與 雷思由於本發明在步士〜 女"中的縫隙打開^，第一介電層後，先將存在於第一介 、、器。因此，在後續米ΐ為開口，之後並將開口的寬度擴 ‘，而形成無縫隙^ f*第二介電層時，可以將開口完全填 為讓本發明之 》溝渠隔離結構。 顯易懂，下文特舉士，和其他目的、特徵、和優點能更明 細說明如下： 較佳實施例，並配合所附圖式，作詳 【實施方式】 -種Π圖所繪示為依照本發明-較佳實施例的 真充間隙的方法之流程剖面示意圖。 合金或鋁銅 1 0 2例如、… 的其他半導體元件結構 明參照第1人圖，提供一基底，且基底100上已形成 有數個凸部1 0 2，而且各個凸部1 〇 2之間係具有間隙丨〇 J。 在一較佳實施例中，這些凸部1 〇 2例如是導線結構，且這 些導線結構可以是各種不同的材料，例如：鋁°、銅、鋁矽 合金或銘銅合金或銅。此外，另一較佳實施例中，這些凸 部1 0 2例如是閘極結構、電晶體、二極艚$羽一祕热運田11978twf.ptd Page 9 1226658 V. Description of the invention ⑷ To fill these gaps and retreat several gaps, and this ^. Among them, the first dielectric layer formed has J; the removed portion is first; and the top of 3 is higher than the surface of the mask layer. Then ^ open. Then, the sacral layer is removed so that these gaps are opened to form a width of number 2 =. Followed by τ = the first dielectric layer on the side walls of the openings to enlarge the openings. After that, a second dielectric layer is formed on the first dielectric layer to form a dielectric layer. ‘Remove the first dielectric layer and Rath outside these trenches. Because of the gap in the priest ~ female’ of the present invention, the first dielectric layer will first exist in the first dielectric layer. Therefore, in the subsequent step, when the opening is enlarged, and the width of the opening is expanded to form a seamless gap ^ f * the second dielectric layer, the opening can be completely filled into the trench isolation structure of the present invention. It is easy to understand. The following special envoys, and other purposes, features, and advantages can be described in more detail as follows: The preferred embodiment, in conjunction with the accompanying drawings, details [Embodiment]-The type shown in the figure is shown in accordance with Schematic cross-sectional view of the method of the present invention-the preferred embodiment of the method of true gap filling. The structure of other semiconductor elements such as alloy or aluminum-copper 1 0 2 such as, is clearly referred to the first figure, a substrate is provided, and a plurality of convex portions 102 have been formed on the substrate 100, and the relationship between each convex portion 102 With a gap 丨 〇J. In a preferred embodiment, the protrusions 102 are, for example, wire structures, and the wire structures can be various materials, such as aluminum, copper, aluminum-silicon alloy, or copper alloy or copper. In addition, in another preferred embodiment, the convex portions 102 are, for example, a gate structure, a transistor, and a two-pole electrode.
11978twf.ptd 第10頁 1226658 五、發明說明（5) 接著’於這些凸部102與基底100的表面上形成襯層 1 0 4 '其中，襯層丨〇 4的材質例如是氧化矽，而其形成方法 例如是化學氣相沈積法。此外，形成襯層丨〇 4的作用係可 使凸部1 0 2之間的間隙1 〇 1其高寬比降低。 之後，於基底100上形成介電層106，以填入這些凸部 1 0 2之間的間隙丨〇 !，並覆蓋這些凸部丨〇 2。其中，所形成 之介電層1 0 6中具有數個縫隙1 〇 8，且這些縫隙1 0 8的位置 會高於凸部1 〇 2的頂部。此外，介電層1 〇 6的材質例如是氧 化石夕’而其形成方法例如是高密度電漿化學氣相沈積法。 值得注意的是，此高密度電漿化學氣相沈積法所使用之反 應氣體、惰性氣體或是所施予之偏壓，並無特定之限制’ 其只需使得所生成之縫隙1 〇 8其位置高於凸部1 〇 2的頂部即 可。在一較佳實施例中，此反應氣體例如是矽甲烷與氧 氣，而惰性氣體例如是氬氣。 接著，請參照第1 B圖，進行化學機械研磨法 (Chemical Mechanical Polishing，簡稱CMP)，移除部分 介電層1 0 6，以使縫隙1 〇 8打開，而形成數個開口 1 1 0。由 於上述所形成之縫隙1 〇 8的位置高於凸部1 0 2的頂部’因此 在進行化學機械研磨時，可以在不損傷凸部1 0 2的情況 下，將縫隙1 0 8打開。 然後，請參照第1 C圖，進行非等向性蝕刻 (Anisotropic Etch)製程，以擴大這些開口 11〇的寬度。 其中，此非等向性蝕刻製程例如是濕式蝕刻製程，且此濕 式蝕刻製程所使用之蝕刻液例如是氫氟酸溶液（HF) °此11978twf.ptd Page 10 1226658 V. Description of the invention (5) Next, a liner layer 1 0 4 is formed on the surfaces of the convex portions 102 and the substrate 100. The material of the liner layer 04 is, for example, silicon oxide, and the The formation method is, for example, a chemical vapor deposition method. In addition, the action system for forming the liner layer 04 can reduce the gap 101 between the convex portions 102 and its aspect ratio. Thereafter, a dielectric layer 106 is formed on the substrate 100 to fill the gaps between the convex portions 102 and cover the convex portions 102. Wherein, the formed dielectric layer 106 has a plurality of slits 108, and the positions of the slits 108 are higher than the top of the convex portion 102. The material of the dielectric layer 106 is, for example, oxidized oxidized silicon, and the formation method thereof is, for example, a high-density plasma chemical vapor deposition method. It is worth noting that there are no specific restrictions on the reactive gas, inert gas or bias voltage applied in this high-density plasma chemical vapor deposition method. It only needs to make the generated gap 1 0 8 The position may be higher than the top of the convex portion 102. In a preferred embodiment, the reaction gas is, for example, silicon methane and oxygen, and the inert gas is, for example, argon. Next, referring to FIG. 1B, a chemical mechanical polishing method (CMP) is performed to remove a portion of the dielectric layer 106 so that the gap 108 is opened to form a plurality of openings 110. Since the position of the slit 108 formed above is higher than the top of the convex portion 102, when the chemical mechanical polishing is performed, the slit 108 can be opened without damaging the convex portion 102. Then, referring to FIG. 1C, an anisotropic etching (Anisotropic Etch) process is performed to enlarge the width of these openings 110. The anisotropic etching process is, for example, a wet etching process, and the etching solution used in the wet etching process is, for example, a hydrofluoric acid solution (HF).
11978twf.ptd 第11頁 1226658 五、發明說明（6) 外’將開口 1 1 0擴大成開口 1 1 〇 a，主要是可以使得開口 1 1 〇 的高寬比降低。 繼之，於介電層1 0 6上形成另一層介電層丨丨2 ,以填滿 開口 110a。其中’介電層112的材質例如是氧化梦，而形 成方法例如是化學氣相沈積法，且其反應氣體例如是四乙 基石夕酸酷（Tetra - Ethyl - Ortho - Silicate，簡稱TEOS)。值 付注思的疋’由於開口 1 1 0 a的面寬比較小，因此介電材料 (介電層1 0 6 )可以將開口 1 1 〇 a完全填滿。 由於本發明在形成介電層1 〇 6後，先利用化學機械研 磨法將存在於介電層1 〇 6中的縫隙1 〇 8打開，並且之後還利 用非等向性餘刻擴大開口 1 1 〇的寬度。因此，在後續形成 另一層介電層1 1 2時，可以將開口 1 1 〇 a完全填滿，而形成 使得各個凸部1 0 2的間隙1 0 1完全填滿介電材料。 此外，上述之填充間隙的方法，係適用於填充各種凸 部之間的間隙，而這些凸部例如是導線結構、閘極結構、 電晶體、二極體或習知所能運用的其他半導體元件結構。 第2 A圖至第2 D圖所繪示為依照本發明一較佳實施例的 一種淺溝渠隔離結構之製造流程剖面示意圖。 請參照第2A圖，提供基底200，且基底200上已形成有 圖案化之墊氧化層（pad oxide)202、罩幕層204以及數個 溝渠2 0 6。其中，墊氧化層2 0 2的材質例如是氧化矽，而罩 幕層2 04的材質氮化矽。此外，溝渠2 0 6的形成方法例如是 以圖案化之罩幕層204為蝕刻罩幕而形成之。 接著，於溝渠206的表面形成襯層208。其中，襯層11978twf.ptd Page 11 1226658 V. Description of the invention (6) Outside ′ The opening 1 1 0 is enlarged to the opening 1 1 〇 a, which mainly reduces the aspect ratio of the opening 1 1 〇. Next, another dielectric layer 2 is formed on the dielectric layer 106 to fill the opening 110a. The material of the 'dielectric layer 112 is, for example, an oxide dream, and the formation method is, for example, a chemical vapor deposition method, and the reaction gas is, for example, Tetra-Ethyl-Ortho-Silicate (TEOS). Since the area width of the opening 1 1 0 a is relatively small, the dielectric material (dielectric layer 10 6) can completely fill the opening 1 1 0 a. After the dielectric layer 106 is formed in the present invention, the gap 1 108 existing in the dielectric layer 106 is opened by a chemical mechanical polishing method, and the opening 1 1 is also enlarged by using an anisotropic aftermath. 〇Width. Therefore, when another dielectric layer 1 12 is subsequently formed, the opening 1 10 a may be completely filled, so that the gap 10 1 of each convex portion 102 is completely filled with the dielectric material. In addition, the above-mentioned method for filling a gap is suitable for filling a gap between various convex portions, and the convex portions are, for example, a wire structure, a gate structure, a transistor, a diode, or other semiconductor devices that can be used conventionally. structure. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. Referring to FIG. 2A, a substrate 200 is provided, and a patterned pad oxide layer 202, a mask layer 204, and a plurality of trenches 206 have been formed on the substrate 200. The material of the pad oxide layer 202 is, for example, silicon oxide, and the material of the cover layer 204 is silicon nitride. In addition, the trench 206 is formed by, for example, using the patterned mask layer 204 as an etching mask. Next, a liner layer 208 is formed on the surface of the trench 206. Among them, the liner
11978twf.ptd 第12頁 1226658 五、發明說明（7) 2 0 8的材質例如是氧化矽，而其形成方法例如是熱氧化 法。 之後，於基底200上形成介電層210，以填入溝渠2〇6 中。其中，所形成之介電層210中具有數個縫隙212，且這 些縫隙212的頂部會南於罩幕層204的表面。此外，介電層 2 1 0的材質例如是氧化矽，而其形成方法例如是高密度電 漿化學氣相沈積法。值得注意的是，此高密度電漿化學氣 相沈積法所使用之反應氣體、惰性氣體或是所施予之偏 壓，並無特定之限制，其只需使得所生成之縫隙2 1 2其頂 部高於罩幕層2 0 4的表面即可。在一較佳實施例中，此反 應氣體例如是矽甲烷與氧氣，而惰性氣體例如是氬氣。 接著，請參照第2 B圖，移除部分的介電層2 1 0，以使 縫隙2 1 2打開，而形成數個開口 2 1 4。其中，移除部分的介 電層2 1 0的方法例如是化學機械研磨法。由於上述所形成 之縫隙212其頂部會局於罩幕層204的表面，因此在移除部 分的介電層2 1 0時，可以在不損傷罩幕層2 0 4的情況下，將 縫隙2 1 2打開。 ^ 然後，請參照第2 C圖，移除開口 2 1 4側壁之介電層 2 1 0，以擴大開口 2 1 4的寬度。其中，移除的方法例如是非 等向性蝕刻製程，而此非等向性蝕刻製程例如是濕式蝕刻 製程’且此濕式餘刻製程所使用之蚀刻液例如是氩說酸溶 液。此外，將開口 2 1 4擴大成開口 2 1 4 a，主要是可使得開 口 2 1 4的高寬比降低。 繼之，於介電層21〇上形成另一層介電層216，以填滿11978twf.ptd Page 12 1226658 V. Description of the invention (7) The material of 208 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation. Thereafter, a dielectric layer 210 is formed on the substrate 200 to fill the trenches 206. The dielectric layer 210 is formed with a plurality of slits 212, and the tops of the slits 212 are south of the surface of the mask layer 204. In addition, the material of the dielectric layer 210 is, for example, silicon oxide, and the formation method thereof is, for example, a high-density plasma chemical vapor deposition method. It is worth noting that there are no specific restrictions on the reactive gas, inert gas or bias voltage applied in this high-density plasma chemical vapor deposition method. It only needs to make the gap 2 1 2 The top is only higher than the surface of the cover layer 204. In a preferred embodiment, the reaction gas is, for example, silicon methane and oxygen, and the inert gas is, for example, argon. Next, referring to FIG. 2B, a part of the dielectric layer 2 1 0 is removed, so that the slit 2 1 2 is opened to form a plurality of openings 2 1 4. Among them, a method of removing a part of the dielectric layer 2 10 is, for example, a chemical mechanical polishing method. Since the top of the gap 212 formed above is located on the surface of the mask layer 204, when the dielectric layer 2 10 is partially removed, the gap 2 can be formed without damaging the mask layer 204. 1 2 Open. ^ Then, referring to FIG. 2C, the dielectric layer 2 1 0 on the sidewall of the opening 2 1 4 is removed to enlarge the width of the opening 2 1 4. Among them, the removal method is, for example, an anisotropic etching process, and the anisotropic etching process is, for example, a wet etching process', and the etching solution used in the wet post-etching process is, for example, an argon acid solution. In addition, expanding the opening 2 1 4 to the opening 2 1 4 a mainly reduces the aspect ratio of the opening 2 1 4. Next, another dielectric layer 216 is formed on the dielectric layer 21 to fill it.
1226658 五、發明說明（8) · 開口 2 1 4 a。其中，介電層2 1 6的材質例如是氧化矽，而形 成方法例如是化學氣相沈積法，且其反應氣體例如是四乙 基矽酸酯。值得一提的是，由於開口 2丨4 a的高寬比較小， 因此介電材料（介電層2 1 6 )可以將開口 2丨4 a完全填滿。 之後’請參照第2 D圖，移除溝渠2 〇 6以外之介電層 (210與216)，而僅留下填滿溝渠2〇6的絕緣層21“。其 中’移除的方法例如是化學機械研磨法。 繼之’將基底200上的墊氧化層2〇2以及罩幕層2〇4移 除，以完成淺溝渠隔離結構之製程。 由於本發明在形成介電層21〇後，先將存在於介電層 2 1 0中的縫隙2 1 2打開而成為開口 2 1 4，之後並將開口 2 1 4的 寬度擴大。因此，在後續形成另一層介電層216時，可以 將開口 2 1 4a完全填滿，而形成無縫隙之淺溝渠隔離結構。 以下為了證明本發明的方法，特舉出一較佳實施方式 加以說明。 首先利用高密度電漿化學氣相沈積法於凸部（例如： 第1A圖所示之凸部1〇2)上沈積一層氧化矽介電層。其中， 此沈積製程之反應氣體例如是矽甲烷與氧氣，而矽甲院的 流速例如是介於80至1 OOsccm之間，且氧氣的流速例如是 介於140至160sccm之間。另外，沈積製程之惰性氣體例如 疋氬氣’而氬氣的流速例如是介於20至40sccm之間。此 外’於此南密度電聚化學氣相沈積製程中，用來控制電裂 方向之偏壓值例如是介於4200至4500瓦特之間。值得一提 的是，利用上述製程參數所形成之縫隙（例如：第丨A圖所1226658 V. Description of the invention (8) · Opening 2 1 4 a. The material of the dielectric layer 2 1 6 is, for example, silicon oxide, and the formation method is, for example, a chemical vapor deposition method, and the reaction gas is, for example, tetraethyl silicate. It is worth mentioning that, since the height 2 of the opening 2 丨 4a is relatively small, the dielectric material (dielectric layer 2 1 6) can completely fill the opening 2 丨 4a. After 'please refer to FIG. 2D, remove the dielectric layers (210 and 216) other than the trench 2 06, and leave only the insulating layer 21 filling the trench 2 06.' The method of removal is, for example, Chemical mechanical polishing method. Then, the pad oxide layer 200 and the mask layer 204 on the substrate 200 are removed to complete the process of the shallow trench isolation structure. Since the dielectric layer 21 is formed by the present invention, First, the gap 2 1 2 existing in the dielectric layer 2 10 is opened to become the opening 2 1 4, and then the width of the opening 2 1 4 is enlarged. Therefore, when another dielectric layer 216 is subsequently formed, the The opening 2 1 4a is completely filled to form a seamless shallow trench isolation structure. In order to prove the method of the present invention, a preferred embodiment is specifically described below. First, a high-density plasma chemical vapor deposition method is used to project the convex structure. A silicon oxide dielectric layer is deposited on the substrate (for example, the convex portion 102 shown in FIG. 1A). The reaction gases in the deposition process are, for example, silicon methane and oxygen. 80 to 1 OOsccm, and the flow rate of oxygen is, for example, 140 to 160s ccm. In addition, the inert gas in the deposition process, such as krypton argon, and the flow rate of argon gas is, for example, between 20 and 40 sccm. In addition, in this southern density electropolymer chemical vapor deposition process, it is used to control the The bias value of the crack direction is, for example, between 4200 and 4500 watts. It is worth mentioning that the gap formed by the above process parameters (for example, as shown in Figure 丨 A)
1226658 五、發明說明（9) 示之縫隙1 0 8 )，其位置會高於凸部的頂部。 然後，進行化學機械研磨法，以使縫隙打開。由於上 述所形成之縫隙高於凸部的頂部，因此在進行化學機械研 磨時，可以在不損傷凸部的情況下，將縫隙打開。 接著，利用氫氟酸溶液進行非等向性蝕刻製程，以使 這些縫隙的開口寬度變大，進而降低縫隙開口的高寬比。 繼之，進行化學氣相沈積法，以於介電層上形成另一 層氧化矽介電層，並且填滿這些縫隙的開口。其中，電漿 化學氣相沈積法的反應氣體例如是四乙基石夕酸酯。由於縫 隙開口的高寬比較小，因此所形成之氧化矽介電層可以填 滿開口 ，而使得凸部之間的間隙完全填滿介電材料，且無 縫隙之存在。 綜上所述，利用本發明之方法可以避免習知在凸部之 間的間隙填入介電材料時，會於介電材料層中產生縫隙的 問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。1226658 V. Description of the invention (9) The gap 1 0 8) is positioned higher than the top of the convex portion. Then, a chemical mechanical polishing method is performed to open the gap. Since the gap formed above is higher than the top of the convex portion, the crevice can be opened without damaging the convex portion when performing chemical mechanical grinding. Next, an anisotropic etching process is performed using a hydrofluoric acid solution to increase the opening widths of these slits, thereby reducing the aspect ratio of the slit openings. Then, a chemical vapor deposition method is performed to form another silicon oxide dielectric layer on the dielectric layer, and fill the openings of these gaps. Among them, the reaction gas of the plasma chemical vapor deposition method is, for example, tetraethyl oxalate. Because the height and width of the gap openings are relatively small, the formed silicon oxide dielectric layer can fill the openings, so that the gaps between the convex portions are completely filled with the dielectric material, and there are no gaps. In summary, the method of the present invention can avoid the problem that gaps are caused in the dielectric material layer when the dielectric material is filled in the gap between the convex portions. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
11978twf.ptd 第15頁 1226658 圖式簡單說明 第1 A圖至第1 C圖所繪示是依照本發明之一較佳實施例 的一種填充間隙的方法之流程剖面示意圖。 第2 A圖至第2 D圖所繪示是依照本發明之一較佳實施例 的一種淺溝渠隔離結構之製造流程剖面示意圖。 【圖式標記說明】 1 0 0、2 0 0 :基底 1 0 1 :間隙 1 0 2 :凸部 1 04、2 0 8 :襯層 106、112、210、210a、216 :介電層 1 0 8、2 1 2 :縫隙 110、 110a、 214、214a:開口 202 墊氧化層 204 罩幕層 206 溝渠11978twf.ptd Page 15 1226658 Brief Description of Drawings Figures 1A to 1C are schematic cross-sectional views of a method for filling a gap according to a preferred embodiment of the present invention. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a shallow trench isolation structure according to a preferred embodiment of the present invention. [Illustration of figure mark] 1 0 0, 2 0 0: base 1 0 1: gap 1 0 2: convex portion 1 04, 2 0 8: liner 106, 112, 210, 210a, 216: dielectric layer 1 0 8, 2 1 2: gaps 110, 110a, 214, 214a: openings 202 pad oxide layer 204 cover layer 206 trench
11978twf.ptd 第16頁11978twf.ptd Page 16
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92129093A TWI226658B (en) | 2003-10-21 | 2003-10-21 | Method of filling intervals and method of fabricating a shallow trench isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW92129093A TWI226658B (en) | 2003-10-21 | 2003-10-21 | Method of filling intervals and method of fabricating a shallow trench isolation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI226658B true TWI226658B (en) | 2005-01-11 |
| TW200515487A TW200515487A (en) | 2005-05-01 |
Family
ID=35634276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW92129093A TWI226658B (en) | 2003-10-21 | 2003-10-21 | Method of filling intervals and method of fabricating a shallow trench isolation |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI226658B (en) |
-
2003
- 2003-10-21 TW TW92129093A patent/TWI226658B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200515487A (en) | 2005-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI249774B (en) | Forming method of self-aligned contact for semiconductor device | |
| TW554472B (en) | A method for forming shallow trench isolation | |
| JP2004186557A (en) | Method for manufacturing semiconductor device | |
| TW201010026A (en) | Through substrate via including variable sidewall profile | |
| JP2001358214A (en) | Semiconductor device and its manufacturing method | |
| JP2001015594A (en) | Formation of multilayered metallic wiring of semiconductor device | |
| JP2002043413A (en) | Semiconductor device and its manufacturing method | |
| JP3463038B2 (en) | Method for manufacturing semiconductor device | |
| JP4791723B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI320215B (en) | Method of forming shallow trench isolation(sti) with chamfered corner | |
| TWI360184B (en) | Method for fabricating semiconductor device with b | |
| TWI226658B (en) | Method of filling intervals and method of fabricating a shallow trench isolation | |
| JPH10116904A (en) | Manufacture of semiconductor device | |
| TW202234594A (en) | Dyanmic random access memory and method of manufacturing the same | |
| JP2004040117A (en) | Semiconductor memory device using damascene gate and epitaxial process, and its manufacturing method | |
| JP2008010884A (en) | Method of manufacturing semiconductor device | |
| JP3987239B2 (en) | Manufacturing method of semiconductor device | |
| JP2009054683A (en) | Semiconductor device and manufacturing method therefor | |
| JP2000031489A (en) | Manufacturing semiconductor device | |
| JP2001093861A (en) | Semiconductor device and manufacturing method thereof | |
| JP2002083866A (en) | Semiconductor device and production method therefor | |
| JP2000294629A (en) | Semiconductor device and manufacture of the same | |
| JPH08330251A (en) | Manufacture of semiconductor device | |
| JP2003100868A (en) | Semiconductor device and its manufacturing method | |
| TWI306643B (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |