TWI225346B - Crossbar switch controller and method of optimizing the same - Google Patents

Abstract

The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configures to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position.

Description

1225346

说明 Description of the invention (The description of the invention should state: the technical field, prior art, content, implementation, and drawings of the invention) The priority of US Patent No. 60 / 333,945, filed on November 20, 2002, is incorporated herein by reference. Field of invention

This invention relates to the field of telecommunications, and in particular to advanced telecommunications routers and crossbar switch controllers. 1〇 [iltr] Background of the Invention The innovation of network communication and exchange is developing at extremely fast speed. The emergence of optical network connections requires network switching technology that can be performed at relatively high speeds. 15 Traditional technology requires a considerable number of devices to achieve high speeds and cannot

Provide support for future high data rate exchange needs. One of the obstacles of the conventional technology is the use of crossbar switches and the related rule system for setting the switches. The crossbar switch technology is quite simple in principle, but it is very complicated to optimize it, because for each data, they may think that many switches need to be set and those switches may be different. _ Data conflicted in transmission. Some people have tried to develop technologies that can support high data rates. For example, US Patent No. 5,734,649 describes a crossbar switch rule system to optimize the decision tree, and US Patent No. 5,500,858. Patent No. describes another technique. However, 6 1225346

发明, invention description These technologies will not provide the bandwidth required for future needs. What we need is an advanced telecommunications router and crossbar switch controller that can perform to some extent consistent with optical network systems. 5 [Summary of the Invention] Summary of the Invention

The present invention overcomes known limitations and provides an advanced telecommunications router and crossbar switch controller. A conventional crossbar switch includes a plurality of input ports' which are switched to a plurality of outputs. These switches are set to 10 = at the intersection of most lines. Because the crossbar switch has a large number of destinations, the data can flow through these paths to its destination, and switches such as * Hai must be set before transmitting data. The mechanism used to set this switch is called an Arbiter. The present invention provides a high-efficiency arbitration benefit, which includes multiple new technologies to improve speed and exchange options.

15. ^ By providing materials with efficient time, the present invention supports a very high processing capacity by this route. In the case of 20 ears, the present invention relates to a crossbar switch controller, which includes a structure to receive a service request signal from one of a group of virtual input queues, the input terminal, and each virtual input queue. It includes a set of seals, = inventions, and -sets of matrix circuits, which are pushed to the input and are constructed to represent the set of service request signals in the form of a -matrix, where the "service" month seeks a number of positions M And a line position N to indicate. The invention further includes an input terminal, which is structured to receive a portion of the packet received during an operation (epoch); _ arbiter circuit, deaf 7 1225346 玖, invention Explanation L ... a4: '23 '': i structure to interactively scan the matrix during the -operation period and generate the group of authorization signals to the virtual output queue during the operation period to receive a portion of the group of packets; and- The arbiter controller is structured to enable the arbiter circuit with an array of non-expense, vehicle, and vehicle components. In this way, the arbiter circuit scans the matrix during the fifth operation, generates the set of authorized money, and allows the set of authorized service requests to complete completely, and scans the matrix during subsequent operation periods if necessary. In another implementation, the invention relates to a crossbar switch controller, including an arbitration pre-processor, which is lightly connected to the input terminal and the matrix circuit, and is structured to map the matrix with a mapping. Type to represent the group of services "Monthly seeking number", and is also structured to convert the first mapping position to the second mapping position of the service request signal based in part on a mapping rule system. This month also includes a The arbiter post processor is connected to the output terminal and the matrix circuit, and is further configured to convert the second bit 15 of the service request signal back to the first position. In another embodiment, the present invention It is about a method for optimizing a vertical and horizontal parent switch controller. This method further includes an architecture_input terminal to receive a group of service request signals from a group of virtual output queues, and each group of virtual outputs 仵The column includes a set of packets. The method also includes lightly connecting a momentary 20-array circuit to the input terminal, coupling the matrix circuit to represent the group of service request signals in a matrix form, and coupling an output terminal to the matrix circuit. . The method further includes constructing the output to receive a portion of the group of packets during an operation period, coupling an arbiter circuit to the matrix circuit, and constructing the arbiter circuit to interactively scan the matrix during the operation period. And produces this 8 1225346

The description of the invention, the group authorizes the signal to the virtual input fanning column to decide that a service request is authorized. The method further includes a pure-arbiter controller to the arbiter circuit, and the arbiter controller is configured to start the arbitration H circuit with the array non-conflict matrix element, operate the matrix at __, and generate the Group authorized signal. The method further includes allowing the set of authorized service requests to be fully completed; and, if necessary, scanning the matrix during subsequent operational periods.

Advantages of the present invention include the ability to use a crossbar exchange to manage high data rates, and to improve the fairness of arbitration without substantially damaging the performance of the crossbar switch. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is explained by way of example and accompanying drawings, but it is not limited thereby. The same reference numerals refer to similar elements and among them: FIG. 1 illustrates an implementation according to one of the present inventions. Example 15 is a crossbar switch used in telecommunication switches. This will be used in an Internet router.

A group of virtual output queues, a group of switches, a group of output queues, and an arbiter are shown. Figures 2A-F illustrate a preliminary virtual output queue of a matrix, a switch matrix, according to an embodiment of the present invention. A set of output queues and an arbiter 20; Figure 3A is a flowchart according to an embodiment of the present invention, which shows the execution steps during the data conversion cycle of the arbitration; Figure 3B is a timing line , Which shows the continuous execution steps of FIG. 3A; FIG. 4A shows an arbiter circuit according to one embodiment of the present invention; 9 1225346 more than 4 dollars, I 玖, invention description HiLljLljij Invention of the invention—an actual arbitration unit circuit; FIG. 4C illustrates an internal circuit of an arbitration unit according to an embodiment of the present invention; Sections 5A-D1) will show that according to an embodiment of the present invention— An arbitration unit of a simplified matrix in a crossbar switch 5 machine; FIG. 6 illustrates a crossbar switch with an additional arbitration pre-processing m arbitration post-processor according to an embodiment of the present invention;

Figures 7A-D show 10 columns of virtual output pieces of the simplification matrix of a rotation mapping rule system using an arbitration pre-processor according to an embodiment of the present invention; Figure 7E shows according to an embodiment of the present invention An arbitration pre-processor uses one of the rotating mapping rules system to simplify the functional logic diagram; FIG. 8 shows a simplified functional logic diagram using an arbitration pre-processor to use one of the mapping mapping rule systems according to an embodiment of the present invention 15 Figures 9A-D show a pre-arbitration process according to an embodiment of the present invention;

The processor uses one of the first-level mapping rule systems to simplify the matrix virtual output queue; and FIG. 10 illustrates a simplified pre-processor using an exchange network mapping rule system in accordance with an embodiment of the present invention. Functional logic diagram. 20 [Embodiment] Detailed description of the preferred embodiment The present invention is described with reference to a specific basic architecture and communication protocol. Those skilled in the relevant art will understand that the description is provided for illustration and to provide the best mode for carrying out the invention. This description is not intended as a limitation on this issue.

rL 3 l 2s j; 'M 玖, description of the invention L-1-1. For example, the reference is the Internet protocol, but any packet protocol can be applied. Furthermore, the reference refers to a chip containing integrated circuits, but the owner of other hybrid or super-circuit combination chips can be expected. This exemplary embodiment provides a 5x5 switch, but may be 5 other numbers consistent with switch technology. A. Crossbar Switch Architecture and Method Figure 1 shows one crossbar switch 100 used in telecommunication switching, which can be used in an Internet router. The core of the switch 100 is β the crossbar circuit 110 (sometimes referred to as a switch matrix), which includes 10 consecutive rows and columns, and has a switch at the intersection of the rows and columns. A set of virtual input queues 12 ^ (^ 1 to Vq_MN) is coupled to an external data source and buffered such data is transmitted through the horizontal and vertical circuit lines no. The switch matrix is usually rectangular (M = N), but this need not be the case. A set of output queues 130 are also coupled to the crossbar circuit and are designed to transmit the output data to external circuits. A controller 140 is coupled to the virtual input queue and the switch matrix. Each data transfer is called an operational epoch, and the switch is typically set during the operational period immediately before the data transmission. Figures 2A-F illustrate a dummy 20 output queue of a matrix according to one embodiment of the present invention. Figure 2A shows the virtual output queue service request for this matrix. The squares labeled 1 are the ones that generated a service requester, and the squares labeled 0 are the ones that did not generate the service requester. It is an object of the present invention to set the switch matrix to allow the largest data to pass through the switch and avoid data collision. In order to do this, the present invention uses a method of determining 11 1225346 • Feiyi »Λ · LL .¾ 发明, description of the invention 5 non-conflicting data transmission requests and then authorizing these requests. One of the requests that would conflict with the first ten authorizations is rejected until a subsequent period of operation. Fig. 3A is a flowchart showing the steps performed during the arbitration and data transfer cycle according to an embodiment of the present invention. Figure 3 is explained in conjunction with Figures 2B-2F. In step 32, the data is buffered in the virtual output string and transmitted via the switch. In step 322, the controller selects the first group of squares to be tested (referred to as a wavefront). This selection can be done arbitrarily, or based on available information, such as the wavefront with the most requests, or by other techniques. In step 10 324, the first wavefront W0 is tested. Please refer to Figure 2B, the first wavefront W0 is a group of squares (Al, B2, C3, D4, E5). It should be noted here that these blocks do not share a row or a row with each other, which means that any request authorized in this group will not cause a data conflict. Each block of a wavefront is checked independently and in parallel. In this example, blocks (: 3 and 1) 4 are identified by 15 as having one of them, so the requests will be authorized to their respective virtual input queues. In step 326, the next wavefront (W1) is tested according to Fig. 2C. Note here that the group in Figure 2C does not have any columns or rows in common. In this example, blocks eight 2 and E1 are identified as having a one among them, so the requests will be authorized for their respective virtual input queues. In steps 326 to 328, other wavefronts up to WN-1 are tested. It should be noted here that in block 2d, 'block C5 is not authorized because block C3 is authorized in wavefront w0 and authorizing block C5 will cause a data destruction. Figure 2E tests the next wavefront and the identification block B5 has a 1 and will not interact with any previously authorized party 12 20

发明, invention description "... Block X conflicts. Therefore, the request will authorize Block B5. 2FS1 does not have an i in Block B1, but generates an authorization that will conflict with the previously authorized Block E1. Step 330 and then edit Decode the signals from the arbiter registration and provide-authorize signals to the virtual input symbol at an appropriate time to allow the data to enter the switch matrix 100. The authorization signals include a plurality of authorization signals i, j , Which represents the row and row of the input port and the required output port. Step 332 represents that the data is transmitted through the switch 100. Figure 3B shows the time of these operation periods and the time from step 33 to step 322. Loop effect. For each operating period, a represents the decision period and B represents the data transmission period. Because it will be an unfair choice for the same starting wavefront W0, one feature of the present invention is to provide the following The starting wavefront of an operation period can be different. For example, please refer to Figure 2a_F again, the next operating period can use the 2C block group as the starting wavefront, and then Figure 2D square wavefront and so on. This becomes a cyclic technique. Another technique is the randomly selected such wavefronts shown in Figures 2C-F. There is another technique to determine an operation period p The non-collision matrix of the array, which is based at least in part on a previous operation period ρ · χ, where X is a natural number. For example, in testing the first request array of Figure 2A, the controller can learn There are many requests in a particular group, which show a certain characteristic of preference and the controller, and then the wavefront can be selected as the starting wavefront. B. Controller and Arbitration Circuit Figure 4A shows a diagram according to the present invention. An embodiment of an arbiter circuit. 5346 F.y'r 3c '" 9al 23 玖, description of the invention LJ * month-said that the arbiter is part of the controller 140 shown in Figure 1. In the exemplary embodiment, the arbiter has the same dimensions as the switch matrix and the request matrix (M × N). As shown in the figure, the arbiter includes a plurality of elements called arbitlets 450-11 Up to 450-ij, which are arranged to match the M × N matrix And line (iJ), and the execution of those authorization decisions and the generation of signals in the arbiter to form the controller's authorization signal. Each arbitration cell includes a row of inputs and a row of outputs, a row of inputs and a row of outputs, and A data input and authorized output. The controller authorization signal includes a set of authorized outputs of the arbitration unit. 10 Note that Figure 4A shows a set of arbitration units, whose column and row inputs are compared with other arbitration units (450 -u, 45 (M, 2,45 (M, 3, ..., 450.hj) are not connected together. This means that the logic circuit is based on an initial wavefront w0 as shown in Figure 2B. And does not require the physical structure of the arbiter 400. In addition, it should be noted that a group of arbitration units 450 ·! ", 15 450 · 1, 2, 450 · 1, 3, ..., 450-i , J appears to send their signals to the terminals along the top side of Figure 4A, and a group of arbitration cells 4% "^, 45 (M, 2, 45 (M, 3, ..., 450- I, j appear to send their signals to the terminals along the right side of Figure 4A. Also note that a group of arbitration units 450 · 2,1, ..., 450-U appear to receive signals from the left side of Figure 4A, and a group of arbitration units 450-il, ..., 450ij appear to receive signals from Input signal on the bottom side of Figure 4A. In one feature of the invention, the arbitration units are matched to the inputs along the left side of FIG. 4A by interconnecting the outputs on the right side in FIG. 4A, and The outputs on the top side are connected to each other and match these inputs along the bottom side of Figure 4A. 14 20 1225346 发明 Description of the Invention-L1: Match 0 Figure 4B shows one of the embodiments according to the present invention. The arbitration unit is 45 ° (the first one is Arbitrary Arbitration). As shown in the figure, the arbitration unit i, j has a row input called Row-i-Busy and a row input c01-Busy. The 5 arbitration unit also has a data input D_i_J, which represents the data from the request matrix block corresponding to the arbitration unit 450 at positions i, j. The arbitration unit generates a signal according to these inputs according to the following table (X means irrelevant): M—iJ 〇 D—U MJ 0 0 1 1 X 0 X 0

Row-i-Busy Column "-Busy 10 0 0 0 0 1 x X 1 15 The output signals Row-i-Busy and ColJ-Busy are the same as their input values after the OR operation with the MJJ. That is, when Row_i_Busy, Col_J_Busy or 1, the output signals Row_i_Busy and Col '' _ Busy become 1. The signals are transmitted through the arbiter circuit 400 to all arbitration orders 20 hours. When the arbiter decides to authorize a virtual output queue to access the switch matrix (M_ij is 1), the remaining ones in the same column and row are:]. This avoids data conflicts in the switch matrix 110. Once the request matrix has been evaluated by the arbiter, the controller sets up a switch in the switch matrix and generates the authorization signal to the virtual input queue. The data is then sent securely through the switch matrix, and the request matrix is evaluated during the next operation. 15 1225346 发明 Description of the invention As shown in FIG. 4A and described above, the arbiter circuit 400 has an output from the right side and the right side is connected to an input on the left side, and an output from the top side, and the top side Is connected to the input on the bottom side. However, this is a possible architecture. There are still other architectures. An actual architecture 5 is called a donut, and as its name implies, it provides a loop of output signals from one set of arbitration units to the input of another set of arbitration units. Figure 4C shows two slightly different arbitration cells 45a & 45b. The Row Busy and Column Busy signals are transmitted from one arbitration cell to the next arbitration cell. In order to perform the arbitration at a high speed, the transmission delay of the (Cloumn) Busy will be minimized. A typical logic database check (for example, using the IBM cu_u program) identifies two types of gates. AOI and OAI gates are the fastest of all standard gates and have the correct logic function. However, because of the logic inverters on the output of the aoi and OAI gates, they are on the other hand installed 15 rows to eliminate the effect of the inverter. As a result, two types of arbitration monomers were designed: type 0 (45〇a) and type 1 (450b). They were used in a proofreading board, where the type 0 arbitration monomer was used in a white square, and the type 1 is used in black squares. According to another embodiment of the present invention, an arbitration pre-processor is used to optimize fairness. Generally speaking, fairness represents a method for comparing average resource utilization with resource demand. In the present invention, fairness refers to the possibility that any given arbitration unit will authorize access to a specific output. For example, in a fair implementation, all arbitration units have substantially the same authorized storage. Probability. 16 1225346

， Replacement page I D, description of the invention ^ Please refer to Figures 5A-D, a simplified matrix arbitration unit in a crossbar switch, each with four columns of 502 are connected to the virtual output The magic column and four rows 504 are coupled to corresponding output ports. In a general implementation, the arbiter will arbitrate a wavefront in each operation period and in the same direction 505, usually along a diagonal 505. This is generally used to optimize the arbitration performance, because changing the direction of the wavefront arbitration can also be substantially increased. The functional complexity in the arbiter requires more logical request steps. In FIG. 5A, the arbiter starts the wavefront arbitration along the diagonal line 506 from element 00 to element 33. In Figure 5B, the arbiter moves the wavefront to the diagonal line 508 from elements ⑴ to 10 70 pieces 30. In Figure 5C, the arbiter again moves the wavefront from the components 02 to 31 to the diagonal line 51. And finally, in Figure 5D, the arbiter moves from element 03 to element 32, and the wave reaches the diagonal 512. In this implementation, elements in the starting diagonal 506 will tend to be evaluated first, and will therefore be given priority over 15 other elements in the matrix. For example, component 00 will always be evaluated before component 01, and therefore will be unfairly given a higher probability to access an output port. Referring now to FIG. 6, the crossbar switch 500 in FIGS. 5A-D is shown, which has an additional arbitration pre-processor 604 and a 20 arbitration post-processor 608. In a non-obvious way, the arbitration pre-processor 604 substantially improves the fairness of the crossbar switch 5 by continuously remapping the virtual output row 602 to a new non-conflicting position in a mapping matrix. It is based in part on a pre-defined mapping rule system that is used as one of the continuous coupling nodes or logic switches. When not changing in any way, crossbar 17 1225346 346, invention description The two switches arbitrate these re-mapping pairs in a general way, and then transmit the result to the post-arbitration processor 608, which is then mapped to the authorized The simulated output is listed to the appropriate output (61). Furthermore, during the operation of the crossbar switch 500 used via the mapping pair input, the predefined 5 mapping rule system can be further constructed. Advantages of the present invention include improving the fairness of arbitration without substantially compromising the effectiveness of the arbiter. Referring now to Figures 7A-D, a virtual output queue for the arbitration preprocessing of Figure 6 is displayed, and one of the rotation mapping logic is used. Based on the mapping input logic input, the rotation mapping rule system remaps the virtual 10 output queue 702, so the wavefront arbitration begins along a different diagonal from one of the original unmapped pair matrices. Please refer to Figure 7-8. An unmapped pair matrix is shown in the figure. The arbiter will perform wavefront arbitration along the diagonal line 706 from το piece 00 to component 33 as shown in the fifth figure. Please refer to FIG. 7B, the rotation mapping pair logic has a re-mapping queue for the virtual output, so that the wave 15 front arbitration starts from element 01 to element 30 along the diagonal 708, which is a row of compensation positions To the right of diagonal 706. Please refer to FIG. 7C. The rotation mapping pair logic has been mapped to the virtual output queue, so the wavefront arbitration starts from element 10 to element 3 along the diagonal 710, which is on the diagonal A row of supplementary positions below 706. And now please refer to FIG. 7D, the rotation mapping pair logic 20 has been re-mapped to the virtual output "quoting" so the wavefront arbitration starts from element 11 to element 00 along the diagonal 712, which is at Both a column of compensation positions below the diagonal 706 and a row of compensation positions to the right of the diagonal 706. Using this rotation mapping logic, for example, up to n statistical permutations can be achieved, where n is the number of virtual output ports. The advantages of the present invention 18 1225346 First, the description of the invention ^ points include improving the fairness of arbitration by periodically allowing each virtual round queue to be placed along the diagonal line of the initial arbitration wavefront. Now referring to FIG. 7E, a simplified functional logic diagram of one of the arbitration pre-processors 604 in FIG. 6 is shown, and a rotation mapping logic is used by 5. Twenty-four logical multiplexing elements 730 are coupled together and have level 0 including elements 730a-h, level 1 including elements 730i-p, and level 2 including elements 730q-x. The mapping logic input is c0, c 1, and c2 as shown in the figure, and the column or row position of the virtual output line is shown as the input 0 or 1 to switch 81 Oa-h. In the beginning, in the level 0, each 10 virtual output rows are connected to the input 0 of a multiplexer element, and the input of a multiplexer 1 is at four position distances. Furthermore, the virtual output queue 0 is coupled to the input 0 of the multiplexer 730a and the input 1 of the multiplexer 730e at four position distances. In level 1, the output of each multiplexer element of level 0 is connected to the input 0 of a multiplexer element and the input 1 of 15 multiplexer elements at two position distances. For example, the output from the multiplexer element 703e is connected to the input 0 of the multiplexer element 730m and the input 1 of the multiplexer element 730k at two position distances. And in level 2, the output of each multiplexer element of level 1 is further coupled to the input 0 of a multiplexer element and the input 1 of a multiplexer element at a position distance. For example, the output from multiplexer element 20 730k is coupled to input 0 of multiplexer element 730s and input 1 of multiplexer element 730r at a position distance. In another feature of the invention, the arbitration pre-processor implements a first order mapping rule system. In one embodiment, a binary tree topology is used. The class mapping rule system is based on the mapping rule system input followed by 19 1225346

发明 Description of invention

The positions or rows of the virtual output queues of the mapping pairs in these layers become a continuous small group. For example, the class mapping rule system initially splits the virtual output into two halves. If the mapping rule system input is true at this level, the column or row position of each element in the first group is exchanged with the column or row position of the corresponding element in the 5 first group (also That is, the first element in the first group is exchanged with the first element in the second group, and so on). Each group was then divided into two smaller groups, and the process was repeated again and again. In addition, the hierarchical mapping rule system can also allow arbitration to pre-process | § 6 04 to deal with one of them first, and then the other 10 to exchange column and row positions. Referring now to Fig. 8, a simplified functional logic diagram of one of the arbitration pre-processors 604 in Fig. 6 is shown, in which a class of mapping rule system is used. Four logical switches 810 are coupled together and have a level 0 including switches 810a-b, and a level 1 including switches 15 810c-d. The input of the mapping rule system is c0, cl, as shown in the figure.

And c2, and the column or row position of the virtual output queue is shown as the input 0.3 switch 810a-b. At the beginning, in level 0, input 0_3 is divided between switches 810a-b into inputs 0 and 2 are coupled to switch 810 & and inputs 1 and 3 are coupled to switch 81 Ob. If the mapping rule system input c0 20 is a logical truth value, then no mapping occurs, because inputs 0 and 1 are transmitted to switch 810c and inputs 2 and 3 are transmitted to switch 810d. That is, the two halves 0_1 and 2-3 remain in the original queue 0-3. If the mapping pair rule system input c0 is a logical false value, inputs 2 and 3 are transferred to switch 810 (:, and inputs 0 and 1 are transferred to switch 810d, which maps to each half of the column or 20

Rose, invention description L order position to the other-half of the column or row position. In Hierarchy, the process is repeated. However, in this class-Bai Yanjia has an independent mapping rule system. The input is just the opposite, as in the former-class. Subsequent levels can have two mapping rule system inputs, where 0 is the number of levels. Referring now to Figures 9A-D, the virtual output symbol sequence of a simplified matrix of one of the arbitration preprocessors 604 in Figure 6 is shown, which uses a first-order mapping rule system. Based on the input of the mapping rule system, the rotating mapping rule system remaps the virtual output character array 902 in exchange to change the relative positions of the virtual output arrays, just like the original non-map matrix. Please refer to Figure 9α. A diastereomorphic matrix is shown, where the arbiter will start wavefront arbitration along a diagonal line 906 including several 00, 11, 22 to element 33. "Monthly reference 9B As shown in the figure, the class mapping rule system will remap the virtual output queue by the 歹 i, so the wavefront arbitration is along a new one including files 10, 01, 32, and 23. Diagonal line 908 starts. Now please refer to Figure 9C, the class mapping rule system has re-mapped the virtual output queue by these rows, so the wavefront arbitration includes components along the way. 1 A new diagonal line 91, 10, 23, and 32 begins. Now please refer to Figure 9D, the class mapping rule system has remapped the virtual output by the rows and columns. Queues, so the wavefront arbitration starts along a new diagonal line 912 which includes one of the components 001 ′ 33 and 22. Using a binary tree-like twist, for example, statistical combinations of up to 2rM can be used Achieved, where η 疋 is the number of virtual output ports. Advantages of the present invention include non-conflicting Combined to change the relative position of the virtual output queue. In another aspect of the present invention, the processor implements a previous arbitration Nine a cross-1,225,346, the invention described DOr day]

Change network mapping rules system. In one embodiment, the switch network maps to a logical use-butterfly topology. Furthermore, the switch network mapping rule system re-maps the paired column and row positions within the virtual queue based on the mapping rule system input step by step. For example, the switch's network mapping algorithm 5 method-just beginning to pair each file with another component. If the mapping rule system is logically true at this level, the column or row position of each element is replaced by the parent. This process is repeated over and over until it reaches the need. The switch network mapping rule system may also allow the arbitration pre-processor 604 to exchange column and row 10 positions by processing them one after another and then another. As shown in Figure 8, unlike the class mapping rule system, the switch network mapping rule system can have n number of mapping rule system inputs in each layer, where η is a coupled virtual Outputs half the number of queues. For example, eight virtual outputs4 listed in each hierarchy may require four mapping rule system inputs. 15 Please refer to Figure 10, the arbitration preprocessor 604 in Figure 6

One simplified functional logic diagram is shown, which uses a switch network mapping rule system. Twelve logic switches 1010 are coupled together using a butterfly topology, and each stage includes four switches. Furthermore, each switch uses a different mapping rule system input. For example, the first output port of the switch 20 l0a is coupled to the first input of the switch i010c. The second output port of the switch 1010b is coupled to the second input port of the switch 1010d. The input of the mapping rule system is shown in the figure: switches 1 〇 丨 〇 & c0, switch 1010b, c2, switch 1010c, C4, switch 1010 (1, c6. At first, if the switch i〇1〇a's mapping pair 22 1225346 j ·-; 9a 4. ^ 23 Rose, description of the invention ... i: L. λ When the regular system input c is a logical truth value Then, the input 0 is transmitted to the switch «machine 1010c, and the input 1 is transmitted to the switch 1010d. If the mapping pair system input is a logical false value, and then the opposite occurs, the input 1 is transmitted to the switch 1010c, and the input 〇 It is transmitted to switch i010d. As in 5, if the mapping pair system input c2 is a logical truth value, then input 4 is transmitted to switch 1010d, and input 5 is transmitted to switch 1010 ( ^ If the input of the mapping rule system is a logical false value, and then the opposite happens, input 5 is transmitted to the switch 1010d, and input 4 is transmitted to the switch 1010c. This program is in the arbitration preprocessor 604 Every 10 switches in each layer are repeated. Use butterfly type For example, as many as 2n / 21Mn statistical combinations can be achieved, where n is the number of virtual output ports. Its advantages include the fact that the possible non-conflicting permutations and combinations can be used to change the number of virtual output queues. 15 C. Conclusion The advantages of the present invention include the ability to use a crossbar switch to manage high data rates, and to improve it without substantially damaging the performance of the crossbar switch. Fairness of arbitration. Although the present invention has been described with many preferred embodiments, there are still other changes, arrangements, and equivalent implementations within the scope of the rights of the present invention. For example, although the The reference materials are binary tree and butterfly topologies. It should be understood that there are still other topologies that can be used. It should also be noted here that there are many ways to implement the device of the present invention. The scope of the attached patent application can be interpreted to include falling on 23 1225346

Ii. Description of the invention All changes, permutations, and equivalent implementations within the true spirit and scope of the present invention. The disclosed examples and the best mode, modifications and changes can also be completed as disclosed embodiments of the subject matter and spirit of the invention as defined by the scope of the attached patent application. [The diagram is simple and clear.] Figure 1 shows a telecommunication switch according to an embodiment of the present invention.

A crossbar switch, which will be used in an Internet router, which displays a set of virtual output queues, a set of switches, a set of output queues, and a 10-bit router; Figures 2A-F are illustrations According to one embodiment of the present invention, a preliminary virtual output queue of a matrix, a switch matrix, a set of output queues, and an arbitration as shown in FIG. 3A is a flowchart according to an embodiment of the present invention. Show 15 steps taken during the arbitration's data conversion cycle;

Figure 3B is a timing line showing the continuous execution steps of Figure 3A; Figure 4A shows an arbiter circuit according to an embodiment of the present invention; Figure 4B shows one of the embodiments according to the present invention Arbitration unit circuit. Fig. 4C shows the internal 20 circuits of the arbitration unit according to one embodiment of the present invention. Figs. 5A-D show one of a crossbar switch according to an embodiment of the present invention. Simplified matrix arbitration unit; Figure 6 shows a crossbar switch with an additional arbitration pre-processor and an arbitration post-processor according to an embodiment of the present invention; 24 1225346

发明 、 Explanation of the invention; called Qi 卩 3 J i '; · ν ί ~.' 一. _ 一, 乂 .. ', ...,.… .. 3 Figures 7A-D show an embodiment according to the present invention A virtual output queue of a simplification matrix using a rotation mapping rule system in an arbitration pre-processor; FIG. 7E shows a system using a rotation mapping rule system in an arbitration pre-processor 5 according to an embodiment of the present invention. A simplified functional logic diagram; FIG. 8 illustrates a simplified functional logic diagram of an arbitration pre-processor using one of the first-level mapping rule systems according to an embodiment of the present invention;

Figures 9A-D illustrate a simplified matrix virtual output queue 10 using an arbitration pre-processor rule system in an arbitration pre-processor according to an embodiment of the present invention; and, Figure 10 illustrates a method according to an embodiment of the present invention in An arbitration pre-processor uses a switch network mapping rule system to simplify the functional logic diagram. [Representative symbol table of the main elements of the diagram] 100 ··· Switch 110 ··· Vertical circuit 120 ··· Virtual output > (Ning 130; Output 140; Controller 400; Arbiter Circuits 450-11 ~ 450-ij ··· Arbitration unit 450a, 450b ··· Arbitration unit 500 ··· Vertical switch 602 ... Virtual output column 604 ·· Arbitration preprocessor 608 ··· After arbitration Processor 610 ... Output port 702 ... Virtual output> (Ninglie 730 ... Logical multiplexing element 810 ... Switch 902 ... Virtual output queue 1010 ... Logic switch W0 ~ WN-1 ... Wavefront

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Claims (1)

1225346 妁 1 妁, 范围, patent application scope LiLJLjJ 1. A crossbar switch controller includes: an input end, receiving a set of service requests from a set of output virtual output queues, each output virtual queue includes There is a set of packets; a matrix circuit is coupled to the above inputs and is configured to represent the above set of service request signals in a form of 5 matrixes, where each service is printed 彳 § 5 tiger is a column position M and a row Position N to indicate; An output terminal is coupled to the matrix circuit and is configured to receive a part of the group of packets during an operation period; an arbiter circuit is coupled to the matrix circuit and is configured to perform the above operation. During the period, the matrix circuit is interactively scanned and the set of authorization signals is generated to the virtual output queue to determine which request is authorized; an arbiter controller is coupled to the arbiter circuit and is configured to start the above-mentioned An array of non-conflicting matrix elements as described above; In this way, the aforementioned arbiter circuit scans the matrix during the first operation period to generate the aforementioned set of authorization signals, allows the aforementioned set of authorized service requests to substantially complete, and scans the matrix during the next operation if necessary. The vertical and horizontal switch controller described in the scope of application of the patent, wherein: '' The arbiter controller is configured to start the arbiter circuit with a non-conflicting matrix element of a different array during each operation. ; And 26 1225346, the patent application scope pif. ', When operating in steady state, the above arbiter controller is constructed to: partly based on non-conflicting matrix X pieces of different arrays during each operation period The non-conflicting chirped elements of the above array of decision-operation periods p. According to the crossbar switch controller described in item 1 of the patent application scope, in A: 〃 The above arbiter controller is constructed to use __ in each operation period. Non-conflicting matrix elements of different arrays to start the arbiter operator; and when operating in steady state, the arbiter controller is constructed to be determined based at least in part on random selection-the non-conflicting matrix of the array in operation period P element. • The crossbar switch controller described in item 1 of Shen Qing's patent scope, basin f: 8 The arbiter controller described above is constructed to The same array of non-conflicting matrix elements to enable the arbiter controller, and when operating in steady state, the arbiter controller is constructed based at least in part on the previous operation period? To determine the non-conflicting matrix element of one of the arrays of operation period P, let X be a natural number. The crossbar switch controller described in the first patent application scope, wherein: the arbiter controller is configured to start the arbiter controller with a non-conflicting matrix element of a different array at each operating period 27 1225346 The patent arbitrage of patents is limited; and when the operation is stable, the arbiter controller is constructed to determine one of the operation periods based on the information collected during the previous operation period P · χ. Non-conflicting matrix element of the array, where X is a natural number. 6. The crossbar switch controller as described in item 4 of patent application 11 in item 4, in i: 〆, The arbiter circuit includes a plurality of arbitration cells matching the matrix and column arrangement of the matrix; and each arbitration cell includes a column of inputs and a column of outputs, a row of inputs and a row of outputs, and a data input and authorized output. 7. The crossbar switch controller as described in item 6 of the patent application scope, wherein: Most of the above arbitration units include a first arbitration unit, wherein the first arbitration unit may make an authorization decision based on a matrix element corresponding to the first arbitration unit. 8. The crossbar switch controller described in item 7 of the scope of patent application, wherein: the plurality of arbitration units further include a second arbitration unit and a third arbitration unit coupled to the first arbitration unit. The arbitration unit; the first arbitration unit may be determined based on the previous authorization and the second arbitration unit and the third arbitration unit. 9. The crossbar switch controller described in item 8 of the scope of patent application, wherein: 28 1225346 票 Ticket, patent application scope Replacement page: The above arbitration single circuit authorization signal includes a group of arbitration single authorization signal output. 10 · If the scope of patent application is the first! The crossbar switch controller described in the item, t includes: 5 an arbitration pre-processor, which is coupled to the above input terminals and the above-mentioned matrix circuit, and is structured to represent the group of services in the form of a mapping pair matrix Request signals, and is further based on a mapping rule system to convert the above-mentioned service request signal of the first mapping pair position to a second mapping pair position; and, 10 an arbiter pre-processor, light access To the above output terminal and the above-mentioned matrix circuit 'and more, it is configured to convert the above-mentioned service request signal of the second spider pair back to the first mapping pair service. 11. The crossbar switch controller according to item 10 of the scope of patent application, wherein the mapping rule system further includes a set of mapping rule system inputs. 12. The crossbar switch controller described in item 1 of the patent application scope, wherein the mapping rule system includes a rotation rule system. 13. The crossbar switch controller according to item 2 of the patent application scope, wherein the input of the set of mapping pair rule system includes a column of compensation. 20 14. According to the horizontal and vertical switch controller described in item 12 of the scope of patent application, the input of the set of mapping pair rule system includes one line of compensation. 15. The crossbar switch controller described in item 12 of the scope of patent application, the input of the above-mentioned mapping pair rule system includes a column of compensation and a row of compensation 29 1225346 16. Patent application scope 16. The crossbar switch controller described in item u of the patent application scope, wherein the mapping rule system further includes a set of mapping pairs. 17. The crossbar switch controller described in item 16 of the scope of patent application, wherein each mapping pair hierarchy of the above mapping pair hierarchy further includes a flip node. 18. The crossbar switch controller described in item 17 of the scope of patent application, Each node of the above group of nodes further includes a group of node inputs and a group of node outputs. 19. The crossbar switch controller according to item 18 of the scope of patent application, wherein each node of each of the above-mentioned groups of nodes further includes a state. 20. The crossbar switch controller according to item 9 of the patent application, wherein the input method of the set of mapping pair rule system includes the above state. 21. The crossbar switch controller described in item 20 of the scope of patent application, further comprising a first mapping pair hierarchy including a first node having a first node. Mapping layer, and a second layer having a second node and a third node, wherein: a first service request signal is coupled to a first node input of one of the first nodes; a second service request signal is coupled Connected to a second node input of one of the first nodes; a first node output of one of the first nodes is coupled to a first node input of the second node; and a second node output of one of the first nodes A first node input coupled to the second point; 30 1225346 (1 year of patent application scope): 丨-… .-Mman ^ 'V ··. * .. person ... 22 · The crossbar switch controller described in item 21 of the patent application scope, where: If the state is a logical truth value, the first service request signal is transmitted to the first node input of the second lang point; and, 5 the second service request signal is transmitted to the first node input of the third node. . 23. The crossbar switch controller according to item 21 of the scope of patent application, wherein: if the state is a logical false value, the first service request signal 10 is transmitted to the first node input of the third node; and The second service request signal is transmitted from the second node to the first node input. 24. The crossbar switch controller according to item 21 of the scope of patent application, wherein the mapping rule system includes a hierarchical mapping rule system. 15 25. The crossbar switch controller described in item 24 of the scope of patent application, wherein the above-mentioned class mapping rule system further includes a binary tree topology. 26. The crossbar switch controller according to item 21 of the scope of patent application, wherein the mapping rule system includes a switch network mapping rule system. • The crossbar switch controller as described in item 26 of the patent application scope, wherein the switch network mapping rule system further includes a butterfly topology. A method for optimizing a vertical and horizontal switch controller includes: 31 1225346 Patent application scope 丨 An architecture input terminal to receive a group of virtual output character string t--group service request signal, each-virtual output The Ning column includes a set of # packets; a matrix circuit is coupled to the above input terminals; 5 consumes the above matrix circuit to represent the above group of service requests in a matrix type, and its service request is-column position I M and a row of position N are described; an output terminal is connected to the above-mentioned matrix circuit; the above-mentioned output terminal is configured to receive _ 10 to receive a part of the above-mentioned group of packets during the operation period of howling; coupled to an arbiter circuit To the above matrix circuit; ㈣ the arbitration n circuit interactively scans the above matrix during the ㈣ period, and generates the set of authorization signals to the virtual output queue to determine which service request is authorized; 5 is coupled to an arbiter control To the arbiter circuit; constructing the arbiter controller to start the arbiter circuit with an array of non-conflicting matrix elements Scanning the matrix during a first operation period; generating the group of authorization signals; 3 allowing the group of authorization service requests to be fully completed; and, if necessary, scanning the matrix during the next operation period. 29. The method for optimizing a crossbar switch controller as described in item 28 of the scope of patent application, wherein: 32 rt < r pick up and apply for a patent when the above H material is cut, JL describes the array one or two Conflict matrix elements are non-conflict matrix elements based on, at least in part, a successful selection of a different array at each working period. The patent described the optimization method described in item 28, the method of making vertical and horizontal switches, in which the non-conflicting matrix elements of the array are based at least in part on the steps of the above-mentioned arbiter controller. A random selection of non-conflicting matrix elements in different arrays in each operation. 10 The method for optimizing the crossbar controller described in item 28, wherein: In the step of constructing the arbiter controller, the non-conflicting matrix element of the array is based at least in part on a previous operation. The period is selected in each of the operation periods-a non-conflicting matrix element of a different array. 32 · Optimization as described in the Outline of the Patent Scope_Method of Crossbar Switch Controller, where ·· In the step of constructing the arbiter controller described above, the non-conflicting matrix elements of the array are based at least in part on the pre-operation period, and the non-conflicting matrix elements of a different array are selected in each of the operation periods. 20 33. The method for optimizing the crossbar switch controller as described in item 28 of the scope of patent application, wherein: in the step of coupling to an arbiter circuit, the arbiter circuit includes a column and a row matching the matrix. The majority of arbitration units configured; and, 33 1225346, patent application scope: 'The parent-arbitration unit includes a row of inputs and a row of outputs, a row of inputs and a row of outputs, and a data input and authorized output. 34. The optimization method of the crossbar switch controller described in the first aspect of the patent application scope, wherein: the above-mentioned plurality of arbitration units include a first arbitration unit, wherein the first arbitration unit may be based on A matrix element coupled to one of the first arbitration unit, the second arbitration unit, and a third arbitration unit is used to make an authorization decision. 35. The method for optimizing a crossbar switch controller as described in item 34 of the scope of patent application, wherein: the plurality of arbitration units include a second arbitration unit coupled to one of the first arbitration unit And a third arbitration unit; wherein the first arbitration unit further includes an authorization decision based on the second arbitration unit and the third arbitration unit. 15 36. The method for optimizing a crossbar switch controller as described in item 35 of the scope of patent application, wherein the above-mentioned arbiter circuit authorization signal includes a set of arbitration unit authorization outputs. 20 37. The method for optimizing a crossbar switch controller as described in item 28 of the scope of patent application, further comprising: coupling an arbitration pre-processor to the above-mentioned input terminal and the above-mentioned matrix circuit; constructing the above-mentioned arbitration pre-processing The device represents the above group of service request signals in the form of a mapping matrix; 34 The above-mentioned arbitration pre-processor is based in part on a mapping rule system to convert the first mapping position of the service request signal to a second mapping position; and coupling a post-arbitration processor to the above output. The terminals and the above-mentioned matrix circuit; and the above-mentioned arbitration processor converts the second mapping position of the service request signal back to the first mapping position. 38. The method for optimizing a crossbar switch controller as described in item 37 of the scope of patent application, wherein the mapping rule system further includes a set of mapping rule system inputs. 39. The method of optimizing a crossbar switch controller as described in item 38 of the scope of patent application, wherein the above mapping rule system includes a rotation method 0 40. The best method as described in item 39 of the scope of patent application Method for transforming a controller of a crossbar switch 15 in which the system of the above mapping pair includes There is a column of compensation. 41. The method for optimizing a crossbar switch controller as described in item 39 of the scope of the patent application, wherein the above-mentioned set of mapping pair rule system rotation includes one line of compensation. 20 42. The method for optimizing a crossbar switch controller as described in item 39 of the scope of patent application, wherein the input of the mapping rule system includes a column of compensation and a row of compensation. 43. The method for optimizing a crossbar switch controller as described in item 38 of the scope of patent application, wherein the above mapping rule system further includes a group of 35 1225346 Pick up and apply for patents. 44. The method for optimizing a crossbar switch controller as described in item 43 of the scope of the patent application, wherein each of the above mapping layer layers further includes a set of nodes. 45. For example, the method described in Article 44 of the Chinese Patent #Scope of Optimization of a crossbar switch controller, wherein each node of the above group of nodes further includes a set of node inputs and a set of node outputs. 仉 The method for optimizing a crossbar switch controller as described in item 45 of the scope of patent application, wherein each node of the above group of nodes further includes a state. 47. The method for optimizing a crossbar switch controller as described in item 46 of the scope of patent application, wherein the above-mentioned set of mapping pair rule system inputs include the above-mentioned states. 48. The method for optimizing a crossbar switch controller as described in item 47 of the scope of patent application, further comprising: Coupling a first service request to a second node input of a first node in a first mapping pair hierarchy; coupling a first node output of one of the first nodes to a second node in a second mapping pair hierarchy A second node is one of the first nodes in turn; a second node that is coupled to one of the first nodes is output to a first node that is one of the third nodes in the second mapping pair hierarchy; where 'if the above state is If the logic value is true, the first node input of the first service request signal is transmitted to the second node of the second node, and the second service request signal is transmitted to the third section above. ^ "36 1225346 Manma song j '" The scope of the patent application is wide: "] m point input; and if the state is a logical false value, the first service input is transmitted to the first node input of the second node, and the second service is transmitted. A request signal is input to the first node input 5 of the second node. · '49. The method for optimizing a crossbar switch controller as described in item 48 of the scope of patent application, wherein the mapping rule system includes a one-level mapping rule system. φ 50. The method for optimizing a crossbar switch 10 controller as described in item 49 of the scope of patent application, wherein the above-mentioned class mapping rule system further includes a binary tree topology. 51. The method for optimizing a crossbar switch controller according to item 48 of the scope of patent application, wherein the mapping rule system includes a switch network mapping rule system. 15 52. The method for optimizing a crossbar switch controller as described in item 49 of the scope of patent application, wherein the switch network mapping rule system further includes a butterfly topology. 37