TWI223925B - A speeded up multistage comparator with power reduction and reliable output - Google Patents

Abstract

A configuration of sub-comparators for use within an analog to digital conversion circuit is disclosed. A number of the sub-comparators are adapted to receive equalization and power down control signals. In one embodiment, several of the sub-comparators are cascaded together in the analog to digital conversion circuit. An equalization signal and a power down control signal are applied to at least some of the sub-comparators enabling the sub-comparators to attenuate or eliminate offset voltage and environmental noise associated with the signal to be sampled. Furthermore, in accordance with another aspect, the analog to digital conversion circuit includes a latch type differential sub-comparator, which can attenuate or eliminate output levels of the sub-comparators from residing in an unstable input region of the digital converter.

Description

1223925 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to the field of semiconductor manufacturing, more specifically, to a comparator having the characteristics of simultaneously providing reliable output, eliminating offset voltage, and low power consumption. . [Prior art] Traditional signal processing is usually done with digital circuits. However, many applications need to generate and process analog signals. When processing mixed signals, it is common practice to convert analog signals into corresponding digital signals, and then the microprocessor completes the processing and so on. In practical applications, for many microprocessor chips, it is commercially feasible to install an analog-to-digital (A / D) converter on the chip. When processing signals, specific analog signals may require different types of conversion circuits and techniques. For example: A variety of different circuits can generate analog signals on a single conductor relative to the ground. Such signals are called `` signa 1-ended '' signals, which means that the size of the signal is relative to It is obtained by measuring the reference voltage (such as ground). Other circuits can generate differential signal on a pair of conductors. At this time, the analog signal on one conductor is measured relative to the other conductor, not the ground circuit. Transformers, differential output amplifiers, and many other circuits can generate this type of signal. In this case, in addition to using a single-ended grounded analog-to-digital device, a differential device is also desired. In general, the operation of analog / digital devices is usually based on the use of a comparator. A comparator is a circuit that compares two input signals and generates an output signal. The output signal indicates the

9818twf.ptd Page 6 1223925 V. Description of the invention (2) The comparison result ’is the maximum value. Comparators are often used for analog / digital conversion, that is, they convert analog inputs to digital inputs. Because the comparator included in the prior art is an element of an analog / digital converter, when the typical function of the comparator is described in the description of the present invention, the comparator will be described as a basic element of the analog digital converter. Under high-precision application conditions, the fully differential structure is often used at the comparator stage to cancel out such issues as digital clock crosstalk (cr oststa 1 k) interference, clock feed-through, power, and / or ground ] ^ (ground bounce) and 1 / f noise environment common mode noise. The figure "shows a conventional comparator circuit 100, which includes four fully differential regenerative sub-comparators 1 05, 106, 107, and 108, so that the advantages of this type of full differential circuit can be fully utilized. In addition to these sub-comparators, there are two sets of single-ended grounded inverting sub-comparators 162, 164, 166, and 168, which can further enhance the signal gain of the comparator circuit 100. In After all these sub-comparator stages, there are two sets of general-purpose digital inverters 174, 175, 176, and 173, and latch 180, which are used to provide a single digital output. This type of complex comparator also has full differential And single-ended ground (FS) structural characteristics. The sub-comparators 105, 106, 107, and 108 are used in series in the separation level. The sub-comparator 105 receives the input voltages VinX- and VinX + from the circuits 11 and hi, respectively, and provides Output signals 121 and 122. The output signal of each stage of the sub-comparators 105, 106, 107, and 108 connected in series is the input signal of the sub-comparator input to the next sub-comparator of the series circuit.

1223925 V. Description of the invention (3) Comparator 1 0 6 receives the output signals 1 2 1 and 1 2 2 of sub-comparator 1 and outputs two signals 1 2 3 and 1 2 4; sub-comparator 1 〇7 receives The output signals 123 and 124 of the sub-comparator 1 〇6 and output two signals 125 and 126, and the sub-comparator 108 receives the output signals 125 and 126 of the sub-comparator 107 and outputs two output signals 〇υτ + and OUT- 〇 Output signals 0 UT + and 0 UT-from the last sub-comparator 1 in the series circuit are provided to the single-ended grounded inverter sub-comparators 1 6 2 and 1 6 respectively. The inverted signal is provided to the Single-ended grounded inverter comparators 16 4 and 16 8 which further increase the signal gain. The signals from the inverting sub-comparators 16 4 and 16 8 are supplied to general-purpose digital inverters 174, 176, 175, and 173. The signal from the digital inverter 175 will set or reset the state of the latch 180. At this time, it can be determined that the differential negative voltage input usually from the external source of the chip is 4 Lu (analog input signal) V i Comparison result between η-and a differential positive voltage input signal (analog reference signal) V i η + which is usually input from the outside of the chip. This comparison process of signals is usually divided into two separate steps: a) sampling phase, b) bit cycling phase 〇 Please continue to refer to Figure 1 A, circuit 1 丨 〇 and 丨丨 i is used to provide the comparator circuit 100 with input signals vi η ×-and V 1 η × + as the sampling signal and the reference signal, respectively. Electricity> Road / 1 〇 is used to sample ν soil η and the differential negative electricity usually generated in the chip, refer to the detection (analog voltage reference) vda —, and sample the signals V in- and / da— at different time intervals. . The operation mode of the circuit 丨 丨 1 is the same as that of the circuit 1 1 〇 Only the circuit 丨 丨 samples v 丨 n + and the differential positive voltage reference signal (analog voltage reference) Vda + that is usually generated in the chip. Sampled signal

1223925 V. Explanation of the invention (4) (such as: Vi η-) and the transmission sequence of the reference signal (such as: Vda-) meet the conditions shown in the waveforms PVin + and Pda + in Figure 1B. When the input control signal Pvin + is in a high state and Pda + is in a low state, the analog signal Vin_ (Vin +) is supplied to the comparator circuit 100. When switch R6 is closed for a period of time △ T1 'Pvin + becomes low state and when pvin + setting (sef) is low after a period of time △ T 3, P da + becomes high state, then the analog voltage reference V da-(V da +) is applied to the comparator circuit 100. During the sampling phase of the analog-to-digital conversion process described below, the circuit 110 provides Vi_n_ as a Vi nX- signal. The circuit no accepts an input signal Vin- from a signal source (not shown). When pvin + is in the "high position, and it is cancerous", it is applied to the circuit 1 1 〇 through the inverting control signal pv 丨 5 of the circuit 丨 5 will set the PMOS transistor on the circuit 1 1 5 to the "on" state (On) ,, The signal pvin + applied to the pass circuit 115 sets the NMOS transistor on the pass circuit 115 to the "on state". Therefore, when Pvin + is in the "high" state and fda + is in the "low" state ; State, both transistors pM0s and OFF03 are in the "on state", and both transistors satisfy the equation v 丨 η χ — = V i η-. It is worth noting that when the signal Pda + is in the "low" state. When pda + and Pda- are applied to pass through circuit 116, both transistors PMOS and NMOS pass through circuit 116 are in the "off state" (off), so no signal Vda- is sent. To the output of the circuit 110. In particular, during this period, the circuit 110 sets the pmos transistor to the 'off state' via the control signal Pda- used by the circuit 116 through the N M 0 S transistor of the circuit 1 1 6 The signal pda + used will set this transistor through circuit 1 1 6 to Off state ". Therefore, in the sampling phase ', to achieve the sampling purpose, V i η-is applied to the comparator circuit 1 〇 0

9818twf.ptd Page 9 1223925 5. The output signal of the circuit 1 1 0 of the invention description (5). Also, in this sampling phase, the circuit 11 outputs Vin + to the comparator circuit 100. It should be noted that pvin + * pda + is essentially a non-overlapping signal, and at any time, Vin— * Vda_ can be transmitted as the output result of circuit 1 1 0. Its further advantage is that Vin- can be provided as the output result of circuit 110 through the PMOS transistor or NMOS transistor of circuit 115. The reason for the repeated use of this function is pM0s transistor or OFF08 transistor. It is to ensure the signal quality of the output result of the circuit. For example, in circuit 1 10, using a PMMOS transistor or an NMOS transistor through circuit 5 alone may be sufficient to transfer the input signal VinX- to the comparator circuit 100. However, the reason for reusing and providing both PMMOS transistors and NMOS transistors is to eliminate the possibility of weak signals, because one transistor may be in a weak state when transmitting a high state, and another transistor may be transmitting. Weak state in low state. This basic principle also applies to the passing circuits 116, 117, 118. Please continue to refer to the timing chart in Figure 1B. After the sampling phase is completed, the control signal pvin + is immediately followed. After the last input signal is sampled and before pda + becomes the high state, there will be a delay △ T2. In the implementation form, a time delay ΔT 3 is used as an embodiment to avoid the output signal interference (i n t e r f e r e n c e) of the comparator circuit. When the control signal p v i n + is in the "low," state, the circuit 丨 1 passes through the inverted pvin-signal used by the circuit 117? ^ 3 transistor is set to the π-off state ", and the transistor 03 is set to the π-off state by Pvin + used in the circuit. During this time, when p v i n + is in a low state and Pda + is in a high state, the PMos transistor and

9818twf.ptd Page 10 1223925 V. Description of the invention (6) NMOS transistors are in π-on state "and any one of them provides a number Vda + which contains an analog voltage reference and is used as the output result of circuit 111. Therefore, In the bit period comparison phase, Vda + is used as an output signal for the comparator circuit 1 0 0 as a comparison circuit 1 1 1. Similarly, when the circuit 1 1 0 is in the bit period phase, it will Output signal Vda- ° to the comparator circuit As mentioned earlier, the analog / digital converter conversion process occurs in the following two different phases: the sampling phase and the bit period phase. During the sampling phase, the analog signal V i η ~ And V i η + are applied to the circuits 1 1 0 and 1 1 1 to provide analog voltage reference signals Vda- and Vda + during the bit period. Once the sampling signal appears at the input terminal of the comparator circuit 100, and Before the initial phase of sampling, all the auto-zero control signals (ie, R i, R2, R3, R4, R5, and R6) will be set to the high state in order to close their switches with the help of the well-known V cm So that the corresponding Than the car parent device is maintained in an auto-zeroing state (auto-zeroing sta te ^. At the beginning of the sampling phase, the switches will open sequentially, and the remaining charge will be stored in the input nodes of all the sub-comparators. When the sampling phase is completed, R 6 changes It is in the low state, and the corresponding switch is turned on. After a period of delay Δ T i, \ p V 丨 n + will change to the low state. At the end of the sampling phase, the electricity stored in ^^ — and V in T + Lang point is stored. What is proportional to the signals vi η-and Vi i η + and at the same time proportional to the input offset voltage (0ffset voltage) of the complex comparator. Ronaldo has different potentials (potent ial) in different converters of the complex comparator. Leading to this offset voltage, the stored charge at the positive voltage node can be expressed as two (Vcm-Vin +) * C, and the stored charge at the negative voltage node can be expressed as

1223925

Q- = (Vcm-Vin-) 氺 C ° ^: ΐ ί After the input signal is sampled, it enters the bit period stage (ie, ^ analog voltage reference), and generates multiple bit comparison outputs,:, =: ΐ Ϊι: The comparison between the sample signal and the analog voltage reference signal. State, PWn is in the low state. $ 样 通 ^ is in the south position. Ί The Jiif low position is relative to the time sample used. Binary Examinations in Digital Language

A corresponding determined voltage level exists at both the terminals VinT + and VinT-. This voltage level can be roughly estimated by the formula VinT + = Ί 进 1, < Zhong❹ has been mentioned above. Then, based on these temporary determination values on VinT + and VinT-, after a ΐ ί ί, the corresponding comparison result will be generated at the terminal cmp0ut. Here the time delay is a function of parameters such as the number of sub-comparators in series. And ί Ϊ t ，, the number S above the discrete step value of the terminal corresponds to the number of output / bits on the terminal cmpOut.

Fig. 2 shows the comparator circuit when the prior art is used. The human molecular comparator 200. The micromolecular comparator 200 shown in FIG. 2 is a master device, and can simultaneously receive signals I N ~ and N +. When the input signal 丨 N + is low ^

1223925 V. Description of the invention (8) In the state, the P M 0 S transistor 2 0 1 is set to " on state " and the p M 0s transistor 2 0 3 is set to " off state. &Quot; The current flowing through the PMOS transistor 2 0 2 in the saturation state mode will appear at node b, and at the same time provide a certain voltage Vb. If the push-pull transistor (pUSh-pUii transistor) is considered 2 0 5-2 0 6 , It can be clearly identified that the PMOS transistor 205 is indeed operating in a saturated state. 'At this time, if V b is in a high state, then υ τ + ground. Push-pull transistors 207 and 208 are similar to this, when IN + is in a high state, ρ μ 〇S transistor 2 0 3 is set to Η on state π, ν a, 〇 τ-ground is formed at node a. In the actual circuit, the voltage on node A and node B It may be different. In this case, the offset voltage between them needs to be eliminated before the next sampling phase. The signals on node A and node B will also have some environmental noise related to these nodes. Sub-comparator 2 00 can reduce or completely cancel the noise and cancel it The terminal provides voltage gain. The amplified differential voltage output and noise reduction can be expressed as follows: If it is assumed that the single-ended ground node A is used for a gain stage including 205 and 206 (or 207 and 208), then the differential output of the sub-comparator = [ A (Vin + + noise) -A (Vin- + noise)]. At this time, the noise can be canceled and an amplified differential voltage output value A (2Vin) can be obtained. Another advantage of the present invention is the sampling and holding process (h ο 1 dpr 〇cess), at each stage of the series of sub-comparators, the output signal related to the sub-comparator of the stage can obtain a gain relative to the input signal of the stage, and can have a reduced noise level ( level). Repeat this voltage gain and noise reduction at each stage of the series of sub-comparators, and

9818twf.ptd Page 13 1223925

And noise reduction analysis. Fig. 3 shows a conventional inverter comparator controlled by an input signal 30i. When the input signal 30 1 is in the low state,?% 05 transistor 3 2 0 is in the “on state”, .03 transistor 31 () is in, and the off state ”, the output result is VDD. However, when this When the input signal is in a high state, the NMOS & transistor 31o is in the "on state", and when the pMOS transistor 32o is in the "off > state", the output result is vss. Even if an input signal high enough or low appears at the input node of the inverter (Figure 3), problems related to power consumption are unlikely to occur. In addition, any other gray area (gjay z ^ ne :) signal can be used for the transistor at the same time? 1 {〇3 gw and nmOS 310, not placed in the on state ", which will cause electricity to appear between VDD and

:: two 2: Γ: ’This type of gray zone signal is usually unavoidable during comparison. Tian Bai ί: The problem in step 3 is that because there are time delays between different αα phases with analog / digital functions, and the same amount of power is consumed in the time delay samples, it is necessary to reduce the delay. Power consumption during time delay. Another :: For example, if you change the circuit, you also need to transmit a reliable output junction. # 换 所 # & The device is unlikely to use a normal digital inverter due to the [inventive content 1 unstable input transition area mechanism. In order to meet the above requirements, the differential structure of the phaser and the latch is compared with the complex comparison of digital conversion.

The present invention uses a fully differential, single-ended ground (F S L). The structure includes a complete comparator. The complex comparator includes a plurality of inverter sub-comparators connected in series, and a latch.

Page 14 1223925 V. Description of the invention (ίο) micromolecular comparator, when multiple inverting lines are analog-to-digital conversion, the complex specific power consumption will be reduced, and the reliability will obtain the combined equalization control signal (equal monthly reduction k According to another feature of the present invention, the device is used to compare two processes of sampling and saving the turn-in signal to illuminate the signal. The equalization control signal is used to reduce the control signal and 'Sampling down or shutting down the comparator between sampling stages includes providing a falling edge latch to maintain a round-out voltage. The input area mitigates or eliminates the comparator within any feature described in this specification unless that feature The combination is summarized from the perspective of the knowledge of those skilled in the art, and the present point is mentioned here. Of course, it should be understood that not all of them are reflected in any detailed description of the present invention and the scope and features of the patent application. In order for the present invention The above and its device and a latch. In this way, the speed of the comparator will be increased and the power consumption will be improved. Compared with the complex comparator of the present invention, izing control signal) and electrical gnal) can achieve the effect of further increasing the speed of the signal. The present invention is a method for using a comparison, which comprises comparing an input signal with the sampled input signal and a voltage reference to equalize the offset voltage in the comparator, the power supply of at least one element between the energy segment and the comparison segment. The method also allows the latch to output voltage levels from the device's unstable sub-comparator below the falling edge latch. Or the feature combinations are included in the present invention, the production angle, the description angle and the proverb are contradictory. Certain features, advantages, and innovations that are apparent to the present invention are all in the form of%. The following advantages of the present invention can be understood by referring to the following of the present invention. His objectives, features, and advantages can be more clearly understood.

1223925 V. Description of the invention (11) It is easy to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings: [Embodiment] Referring to the drawings, this patent specification provides several advantages of the present invention. The implementation form is described, and detailed reference numbers are marked in the drawings. The principle of using reference numbers is that wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or similar parts. It is worth noting that the drawings are drawn in simplified form and therefore are not accurately scaled. In this patent specification, for convenience of description and clarity, directions such as top, bottom, left, right, up, down, top, top, bottom, bottom, back, and front are used with reference to the drawings. Sex term. These directional terms should not be understood as terms used to limit the scope of the invention. Although the description of the present invention includes certain embodiments, it should be understood that these embodiments are merely exemplary illustrations of the present invention and should not be construed as limiting the present invention. Although the following detailed description is only discussed for the exemplary embodiments, as long as it falls within the spirit and scope of the invention defined by the scope of the attached patent application, it should be understood to include all modifications, replacements, etc. of these embodiments Effective use. The present invention can be used with various integrated circuits commonly used in the technical field, only for the purpose of understanding the present invention, here are provided several steps that are often used. In general, the present invention has utility in the field of circuits. However, for the purpose of illustrating the present invention, the following description relates only to an improved apparatus and method for comparing signals in a fully differential, single-ended grounded inverter and latch differential structure. Please refer to FIG. 4A in detail, which provides an implementation form of the present invention

9818twf.ptd Page 16 1223925 5. The schematic diagram of the invention description (12) is different from the fully differential and single-ended grounded structure (FS) in Figure 1A. The diagram includes a fully differential, single-ended grounded inverter and latch. Differential (FSL) structure. In more detail, the fully differential, single-ended grounded inverter and latch differential structure in FIG. 4A includes a complex comparator 4 0 0. In order to improve performance, the complex comparator 4 0 0 includes a full differential comparison Converter, single-ended grounded inverter, and latched differential structure. Performance improvements include at least speed performance improvements (eg, for equalization devices such as 405-408), power consumption improvements (eg, · for use such as 405-408, 4 6 2, 4 6 4, 4 6 6 , 4 6 8 and 4 7 2 power reduction structure) and reliability performance improvement (such as: designed for additional (extra) differential gain, especially for reducing the 472 input transition region of the normal digital inverter unstable). As described in this embodiment, the complex comparator 400 includes a plurality of serially connected all-micromolecule comparators 405, 406, 407, and 408, a plurality of inverter sub-comparators 462, 464, 466, and 468, one A latch-type micromolecular comparator (ltchBuff) 472, a plurality of inverters 474 and 476, and a latch 480. In the described embodiment, the micromolecular comparators 405, 406, 407, and 408 for the complex comparator 400 are similar to the micromolecular comparators 105, 106, 107, and 108 of FIG. 1A. However, each of the regenerated micromolecular comparators used in the above embodiment may further include a balanced structure such as 510 shown in FIG. 5 and a power reduction structure such as 600 shown in FIG. 6. According to other features of the invention, the power reduction structure can also be used in conjunction with inverter sub-comparators 462, 464, 466, and 468. In a modified embodiment, according to other features of the present invention, the micromolecule comparator may further include a non-regenerative all-micromolecule comparator.

9818twf.ptd Page 17 1223925 V. Description of the invention (13) ---- ^ ^ σ ^ ^ in the cascaded sub-comparator of the double-stage comparator is used as the input signal VinT of the sampling signal: and ::: = ; Connect: incoming signal VinT +. Similar to the aforementioned combination = Κ =: Lose VinT +-(Q +) / C + Vda + = Vcm-(Vin4- 丄, bucket, middle · Q + = (Vcm-Vin +) * C, and VinT_ = Vcm _ (

Vin--Vda-). In this way, the deviation between the two input signals is = VinTi-VinT- = _ [(Vin +-Vin-) _ (Vda +-Vda-)]-(2Vin-2Vda). When the input deviation is input to the FS1 comparator structure of the present invention, a logic high state or low state signal will be obtained at the output (the polarity of the signal depends on the application). The advantage of this case is that the pass circuits 410 and 411 which provide the signals Vin +, Vin_, Vda + * Vda_ in this embodiment are similar to the pass circuits 110 and 111 used in the prior art described in FIG. The micromolecule comparator 405 also receives the equalization control signal EQlJ and the power reduction control signal PD. The equalization control signal EQU controls the equalization structure 51 shown in the typical micromolecule comparator 500 shown in FIG. 5. The power reduction control signal PD controls. The electric energy reduction device 6 1 0 shown in FIG. 6. Micromolecule comparison 405 outputs two output signals 4 21 and 422. The σ micromolecular comparator 406 receives the output signals 4 2 1 and 4 2 2 from the micromolecular comparator 405 'equalized control signals £ q υ from a signal source, and the power reduction control signal p D from another signal source. The micromolecular comparator 4 〇6 outputs two output numbers 423 and 424, the micromolecular comparator 407 receives the output signals 42 1 and 42 2 from the micromolecular comparator 406, and the equalization control signals EQlJ and ^ electricity reduction control k number ? 1) As its own input signal 'and output two output numbers 42 5 and 4 2 6. The micromolecular comparator 4 0 8 receives from the micromolecular comparator 4 0 " 7

9818twf.ptd Page 18 1223925 V. Description of the invention (14) The output signals 4 2 5 and 42 6 are equalization and power reduction control signals equ and PD, and output OUT + and OUT-. The equalization control signal E Q U for the multi-level comparator 400 micromolecular comparators 405, 406, 407, and 408 is provided by an equalization control signal source (not shown in the figure). The equalization control signals EQU + and EQU- controlled equalization structures 5 1 0 (figure 5) are added to the micromolecular comparators 405, 406, 407, and 408 in order to shorten the time from the micromolecular comparators 4 0 5, 4 0 6, 4 0 7 and 4 0 8 The recovery time from the relative state of the output nodes (residual state of the previous comparison result) to their equilibrium / balanced state. The power reduction control signal Pd applied to the micromolecular comparators 405, 406, 407, and 408 and the inverter sub-comparators 462, 464, 4 6 6 and 4 6 8 is a power reduction control signal source (not shown in the figure) Out) provided. The power reduction device controlled by the power reduction control signal PD is designed to reduce power consumption. The power reduction control signal PD can help reduce power consumption before and after each sequence comparison operation by ensuring that the micromolecular comparators 40, 5, 6, 4, 7 and 4 0 8 are in a reduced power state during the comparison process. Inverter sub-comparators 462, 464, 466, and 468 are single-ended grounded inverter sub-comparators, which are connected in series after the micromolecular comparators 4 0 5, 4 0 6, 4 0 7 and 4 0 8 Provides additional (e X tra) signal gain in the case of silicon crystal space. In the described embodiment, the inverter sub-comparators 4 6 2, 4 6 4, 4, 6 6 and 4 6 8 are similar to the inverter sub-comparators 1 6 2, 1 6 4, 1 6 6 in the prior art. , 1 6 8. However, according to the present invention, each of the inverter sub-comparators 162, 164, 166, and 168 is improved by adding a power reduction device such as the power reduction structure 600 shown in FIG. Power reduction control letter

9818twf.ptd Page 19 1223925 V. Description of the invention (15) PD controlled inverter sub-comparators 46 2, 464, 4 6 6 and 468 additional power reduction device. The inverter sub-comparators 462 and 464 are connected in series. The inverter sub-comparator 4 6 2 receives the power reduction control signal PD and the output signal OUT + of the micromolecule comparator 408 as its input signal and provides an output signal. 4 6 3. The inverter sub-comparator 464 receives the output signal 463 of the inverter sub-comparator 462 and the power reduction control signal PD, and provides an output signal 469 used by Itch Buff 4 72. Similarly, the inverter sub-comparators 466 and 468 are connected in series, and the inverter sub-comparators 4 6 6 receive the power reduction control signal PD and the output signal OUT- of the micromolecular comparator 408 as its input signals and provide Output signal 4 67. The inverter sub-comparator 468 receives the output signal 467 of the inverter sub-comparator 466 and the power reduction control signal PD, and provides an output signal 471 used by the ItchBuff 472. The first group of inverter sub-comparators 462, 464 and the second group of inverter sub-comparators 466, 468 are connected in parallel with each other, and are also connected in parallel with the micromolecular comparator 408. Fig. 4B shows a schematic diagram of the control signal of the complex comparator 400 shown in Fig. 4A according to the embodiment of the present invention. Initially, all the auto-zero control signals (ie, Rl, R2, R3, R4, R5, and R6) are set to " high state, and all switches are closed and all have a common voltage V c m. The design principle of the power reduction control signal PD is to allow the micromolecular comparators 405, 406, 407, 408 to be in a reduced power state before and after the comparison operation. The method of completing the sampling phase of the input signal V i η is similar to the method described in the prior art above, except that the equalization structure 5 1 0 shown in FIG. 5 is used. The equalization structure 5 1 0 shown in FIG. 5 is controlled by the equalization control signal EQU, as described above.

9818twf.ptd Page 20 1223925 V. Explanation of the invention (16) In combination with the situation shown in Figure 5, the relative state of the output nodes from the micromolecular comparators 4 0 05, 4 06, 4 07, and 40 8 (previously) A residual state of the comparison results) to their equilibrium / equilibrium recovery time. As a specific implementation form of the present invention, the control signal Pv i n and the control signal Pda are non-overlapping signals. Prior to the sampling phase, the control signal pvn is initialized and not set to " high state ", and the control signal Pda is set to ' low state during sampling. Setting the control signal pv i η to the "high" state causes the analog input signals to be sampled by the circuits 41 and 411 in the sampling phase of the comparison process as shown in Fig. 4B to be sent to the complex comparator 400. After the end of the sampling phase, 'is followed by a delay ΔΤ1, and then the control signal Pvi η is set to " low state, " and another time delay △ Τ3, the control signal Pda is not set to "high state." Those skilled in the art should recognize that each of the above time delays is necessary for, for example, setting and resetting the complex comparator 400 from one stage to another. Bits in the comparison process During the period, the control signal Pda is always in the high state, so that the micromolecular comparator 4 05 can be provided with a signal including an analog voltage reference through the circuits 4 10 and 4 1 1 "&. In the bit period phase, V d a appears as a stepped discrete waveform (s t a 丨 r η k e discrete waveform) as shown in FIG. 4B. When the PD control signal decreases, an analog-to-digital conversion (including two phases) occurs. At this time, all micromolecule comparators and inverter sub-comparators are in the active (a c t i v e) state, so they consume DC power (D C). When the bit period is compared with the first sampling voltage, the enable (e n a b 1 e) E N control signal becomes a high state to enable the ltchBuff472 amplification operation. The latch 480 is touched by the latch signal LTCH.

9818twf.ptd Page 21 1223925 V. Description of the invention (17) Before sending to the falling edge, EN should be in an active-high state during the time period of △ τ 2 in order to ensure that the appropriate input signal is delivered to Latch 4 8 0. When E N becomes a low state, the Eq signal will perform an equalization operation on the voltages V a and V b at nodes A and B in FIG. 5. The EN control signal shown in Figure 4B is used to enable ItchBuff 472 (Figure 4A and 700 in Figure 7), so when EN is in the high state, itchBuff 472 is in the active state and acts as an input signal (IN- And IN +) will generate an amplified output signal pair (OUT + and OUT-). According to this implementation form, itchBuff 472 includes an internal power reduction structure, and the inversion of EN (Figures 4B and 7) operates as a power reduction signal. When in the low state, EN disables (disconnects) the two transistors NMOS on the bottom (see Figure 7), which cuts off the current path between VDD and VSS. At the same time, when in the low state, EN will turn on the top two transistors PM0S (see Figure 7), so that the two output nodes of VDD can be set (see OUT + and OUT- in Figure 7) so that the two Inverters 474 and 476 (Figure 4A) are logic high, which does not cause leakage circuit channels. To reduce power consumption, E N can be set to a low state when there are no appropriate input signal pairs at the inputs (I N + and I N-). The internal valley about reducing power consumption has been described in Figure 4B. When pvin +: = i〇w (low state) and Pda + = high (high state), the time of each rising edge of ENS is set to Later than the occurrence of the rising edge of the analog voltage reference signal Vda +. When designing the EN pulse width, consider the total response of itchBuff 472, inverter stage 4 7 6 (Figure 4A) and latch 48 0 (Figure 4A)

98l8twf.ptd Page 22 1223925

between. Therefore, on the falling edge of LTCH-, the intact output is now at itchBuff 472 and inverter 476, and a clear comparison result is latched at the dead end. The output of the memory 4 8 0 Figure 5 is a schematic diagram of the full micromolecular comparator. The description here is similar to the micromolecular comparator 2 of Figure 2. The difference lies in the control of EQU. In addition, the present invention can also provide the power reduction control signal PD to a device such as a micromolecular comparator 500 ^ according to the time in the fourth β diagram. According to the implementation form of the present invention, when, for example, the double-stage comparator 400 is in a bit period stage, the equalization control signal EQU and the power reduction signal? 1) Available for micromolecular comparators 405, 406, 407, and 408. The equalization control signal EQU is suitable for the equalization structure 510, which will cause a voltage to be generated at the node 5200: a voltage Vb will be generated at the node 530. After the equalization, the next comparison phase can be accelerated. According to an embodiment of the present invention, the power reduction control signal PD controls a load circuit. The power reduction control signal PD is suitable for the micromolecular comparators 405, 406, and 407 # ports 408, and the inverter comparators 462, 464, and 466 foreign ports 4 68 to reduce power consumption. The power reduction signal PD is applied to the micromolecule comparators 405, 406, 407, and 408 to power down these sub-comparators before and after the conversion sequence described above. FIG. 6 shows a schematic diagram of a single-ended grounded inverter comparator 6 0 0. For example, it may correspond to the serially connected inverse of the last micromolecular comparator 4 0 8 in the serial micromolecular comparators 405, 406, 407, and 408. One of the phase comparator sub-comparators 4 6 2 and 4 6 4. In the described embodiment, the inverter comparator 6 0 0

9818twf.ptd Page 23 1223925 V. Description of the invention (19) Basically the same as the inverter comparator 200 shown in Fig. 2 except that the inverter comparator 600 further contains a signal Power reduction device 6 1 0. Using the power reduction control signal p D + to reduce the power consumption of the device 6 i 〇 can reduce or eliminate the leakage current existing in the inverter sub-comparator 200 shown in FIG. 2 of the prior art. The method used is when the power reduction control When the ## PD is in the "bit state", the input terminal is grounded, so that the transistor 6 10 can be in the "on state π". According to the implementation form of the present invention, the gain is increased by adding an inverter sub-comparator. At the same time, the addition of a power reduction device can reduce or eliminate current leakage. Figure 7 shows a latch-type micromolecular comparator 7 00 with an energized control signal and a simple self-bias design (for example, corresponding to Figure 4A). Schematic diagram of ItchBuff 472). A latch-type micromolecular comparator 700 is added as a 11ch Buff 4 7 2 to the complex comparator 4 0 0 in order to eliminate the possibility of unstable operation, which may occur in High-precision use cases ^, such as small analog input signals when the input voltage is in the unstable region of the digital inverter structure. When VLS I technology is used, the micromolecular comparators 405, 406, 407, and 408 Inverter sub-comparators 462, 464, 466, and 468 modules can be placed very close to each other when physically placed, so that it can be assumed and actually have almost the same common-mode voltage, while the output is only amplified and asked ^ I points In Figure 4A, ItchBuff 472 receives the output signals 4 6 9 and 4 7 1 from the inverter sub-comparators 4 6 4 and 4 6 8 respectively. Compared with the previous technology, it can provide additional Gain and more reliable output results. Because the time to energize to LtchBuf f 4 72 accounts for only a small part of the entire effective # & & shown in Figure 4B, adding LtchBuff 4 7 2 can be regarded as a smart Stubborn

9818twf.ptd Page 24 1223925 V. Description of the invention (20) Design plan. According to the above, it is obvious to those skilled in the art that the present invention provides a method and a circuit, which are characterized in that it can provide reliable voltage while offsetting environmental noise and eliminate input DC offset in the analog-to-digital converter. Voltage, reducing power consumption. The above several implementation forms are provided as examples only, and the present invention is not limited to these embodiments. For those skilled in the art, based on the content described above, they can make changes and modifications to the above implementation forms without contradicting each other. In addition, those skilled in the art may make other combinations, deletions, substitutions, and changes based on the contents of the patent specification described herein. Therefore, this patent is not limited to the several implementation forms described in the patent specification, but the content defined by the scope of the patent application shall prevail.

9818twf.ptd Page 25 1223925 Brief description of the diagram Figure 1 A shows the comparator circuit diagram using the previous technology to eliminate the input offset voltage. Chart 1B and Figure 1A are not intended to control the timing of the comparison circuit. Figure 2 shows a schematic diagram of a conventional all-micromolecular comparator. Figure 3 shows a conventional single-ended grounded inverter comparator. Fig. 4A shows that the comparator circuit is not intended after the performance is improved according to the embodiment of the present invention. Fig. 4B is a schematic diagram showing the operation control waveform of the comparator circuit in Fig. 4A according to the embodiment of the present invention. Fig. 5 shows a schematic diagram of an all-micromolecule comparator with functions of saving energy consumption and balancing control according to an embodiment of the present invention. Fig. 6 shows a schematic diagram of a single-ended grounded inverter comparator with a power reduction control function according to an embodiment of the present invention. Fig. 7 shows a schematic diagram of a latch type micromolecular comparator having an enable control signal. [Schematic description] 100: Comparator circuit, 4 0 0: Multiple comparator 105 > 106, 107, 108 > 200, 405, 406, 407, 408 ^ 500: Sub-comparator, 110, 111, 115, 116, 117, 118, 410, 411: circuits, 121, 122 > 123, 124 > 125 > 126, 421, 422, 423, 424, 425, 426, 463, 467, 469, 471: output Signal, 1 62, 164, 166, 168, 462, 464 > 4 6 6, 468, 600: inverter

9818twf.ptd Page 26 1223925 Schematic description of the sub-comparator, 173, 174, 175, 176: general-purpose digital inverter, 1 8 0, 4 8 0 ·. Latch, 201, 202, 203, 205, 206, 310, 320, 610: transistors, 472, 7 0: latch-type micromolecular comparator (ItchBuff), 474, 476: inverter, 51 0: equalization structure (device), 520, 530, Person, 8, ¥ 1111'-, ¥ 111 Ding +: node, 600: power reduction structure EN ·· enable control signal, EQU, EQU +, EQU-: equalization control signal, PD: power reduction control signal No., IN-, IN +, 301: input signals, LTCH: latch signals, OUT +, OUT-: output signals, PVin +, Pvin-, Pda +, Pda-: control signals,

Vcm: common voltage, Vda +, Vda-: electric reference signal, V i η-, V i η +: voltage input signal (analog signal),

VinX-, VinX +: input signal (voltage),

Rl, R2, R3, R4, R5, R6: switches, ΔΤ1, ΔΤ2, ΔΤ3: time delay.

9818twf.ptd Page 27

Claims (1)

1223925 VI. Patent application scope 1. A comparator circuit for comparing a first and a second input signal, characterized in that the comparator circuit includes: a plurality of all-micromolecule comparators connected in series; a plurality of inverters A sub-comparator connected to the all-micromolecule comparison m ·, a plurality of inverters connected to the inverter sub-comparators; and a plurality of power reduction control signal lines connected to the all-micromolecule comparators And at least one of the inverter sub-comparators. 2. The comparator circuit according to item 1 of the scope of patent application, characterized in that: the comparator circuit further comprises a latch-type micromolecule comparator connected to the inverter sub-comparators; and The inverter is connected to the inverter sub-comparators through the latch-type micromolecular comparator. 3. The comparator circuit according to item 2 of the scope of patent application, wherein the comparator circuit further comprises a plurality of equalization control signal lines connected to the all-micromolecule comparators. 4. The comparator circuit according to item 1 of the patent application scope, characterized in that the comparator circuit further comprises a plurality of equalization control signal lines connected to the all-micromolecule comparators. 5. The comparator circuit according to item 4 of the scope of patent application, wherein the power reduction control signal lines are connected to the all-micromolecule comparators and the inverter sub-comparators. 6 · The comparator circuit as described in item 4 of the patent application scope, its characteristics 9818twf.ptd Page 28 1223925 6. The scope of patent application is that it further includes: a power reduction control signal source; and an equalization control signal source. 7. The comparator circuit according to item 1 of the scope of patent application, characterized in that it comprises 4 all-micromolecule comparators connected in series. 8. The comparator circuit according to item 1 of the scope of patent application, wherein the all-micromolecule comparators are non-regenerative sub-comparators. 9. The comparator circuit according to item 8 of the scope of patent application, characterized in that it comprises two inverter sub-comparators. 10. The comparator circuit according to item 4 of the scope of patent application, characterized in that at least one of the equalization control signal lines is operated to cancel the offset voltage on at least one of the all-micromolecule comparators. 1 1. The comparator circuit according to item 10 of the scope of patent application, characterized in that before the bit period phase, a power reduction control signal passes through at least one power reduction control signal line to change at least one all-micro State of the molecular comparator. 1 2. The comparator circuit according to item 1 of the scope of patent application, wherein the power reduction control signal eliminates current leakage in at least one inverter sub-comparator through at least one power reduction control signal line. 1 3. The comparator circuit according to item 4 of the scope of patent application, characterized in that at least one of the equalization control signal lines operates to control a load circuit in the comparator circuit. 14. A comparator circuit for comparing a first and a second input signal, characterized in that the comparator circuit includes: 9818twf.ptd Page 29 1223925 VI. Patent application range: A plurality of all-micromolecule comparators connected in series; a plurality of inverter sub-comparators connected to the all-micromolecule comparators; and a latch-type all-micromolecule Comparators connected to the inverter sub-comparators. 15. The comparator circuit according to item 14 of the scope of patent application, further comprising: a plurality of inverters connected to the latch-type micromolecular comparator; and a latch connected to To the inverters. 16. The comparator circuit according to item 14 of the scope of patent application, further comprising a plurality of power reduction control signal lines connected to at least the micromolecule comparators and the inverter sub-comparators. A sub-comparator. 17 The comparator circuit according to item 16 of the scope of patent application, characterized in that the power reduction control signal lines are connected to the all-micromolecule comparators and the inverter sub-comparators. 18. The comparator circuit according to item 17 of the scope of patent application, further comprising a plurality of equalization control signal lines connected to the all-micromolecule comparators. 19 The comparator circuit according to item 16 of the scope of patent application, further comprising: a plurality of equalization control signal lines connected to the all-micromolecule comparators; and 9818twf.ptd Page 30 1223925 6. Scope of Patent Application A power reduction control signal source and an equalization control signal source. 2 0 — A method of comparing input signals using a comparator, characterized in that the method includes: sampling an input signal and holding the sampled input signal to compare the input signal with a voltage reference signal; using an equalization Controlling the signal to equalize an offset voltage in the comparator; reducing the control signal with an electrical energy to reduce or eliminate the electrical energy supplied to at least one element of the comparator during a period between the signal sampling phase and the comparison phase; and A latch is provided to maintain an output voltage when the latch is triggered. * 2 1 · The method for comparing input signals using a comparator as described in item 20 of the scope of patent application, characterized in that, when the equalization control signal is 1, it is in a high state. % M 奴奴 2 2 · The method of using a comparator as described in item 20 of the scope of patent application, wherein the equalization control signal is changed to a low state for at least part of the time of f n]. father 2 3 · The method for using a ratio input signal as described in item 20 of the scope of patent application, further comprising an enable control 1 comparison wheel for the latch 'delayed after the latch is triggered— After the segment, the enabling control signal is shifted to a high state to enable the =, and the-of the enabling control signal to reduce the latch power: y is reversed to a low state after a predetermined time. After conversion) 1223925 6. Application for patent scope 2 4. The method for comparing input signals using a comparator as described in item 20 of the scope of patent application, wherein the power reduction control signal is moved to a predetermined state to close at least at least the comparator Part of the operation to save electricity. 25. The method for comparing input signals using a comparator as described in item 20 of the scope of the patent application, wherein the latch includes a falling edge triggered latch that is maintained in a high state during the sampling phase. 2 6. The method for comparing input signals using a comparator as described in item 20 of the scope of patent application, further comprising an enable control signal, which is applied to the latch. During the sampling phase, the enable The control signal is in a low state to maintain the latch in a power-down mode; before the latch is triggered, the enable control signal is moved to a high state to enable the latch, and in the After the latch is triggered, after a predetermined delay time, the enable control signal is moved back to the low state, and the power of the latch is reduced. 2 7. The method for comparing input signals using a comparator as described in item 26 of the scope of patent application, characterized in that, between the sampling phase and the bit period phase, the power reduction control signal turns off at least a part of the comparator . 28. The method for comparing input signals using a comparator as described in item 20 of the scope of the patent application, wherein the power reduction control signal is used to reduce or eliminate a leakage current in the comparator. 9818twf.ptd Page 32