1223404 (1) 玖、發明說明 【發明所屬之技術領域】 本發明關於堆疊式金屬〜絕緣體-金屬電容器及其製 造方法，更具體而言，在積體電路製造中，形成嵌入於銅 嵌刻結構中的堆疊式金屬一絕緣體一金屬電容器。 【先前技術】 電容器爲積體電路中必要元件之一，在電路中扮演電 壓δ周整、濾波、等功能。在半導體積體電路中，常見的電 容器型式有多晶矽-絕緣體一多晶矽電容器、金屬一絕緣 體-金屬電容器等等。其中，金屬一絕緣體一金屬電容器 具有較低的接點阻抗，故其Rc値較低，常用於要求高速 的積體電路中’其也經常見於類比電路、混合電路等不同 應用中。 近年來’隨者積體電路微小化的顯著提升’在積體電 路製程中屬於後段製程之金屬化製程中的鋁導線，已逐漸 由導電係數較小的銅導線所取代，。此外，在現今的積體 電路製程中，舉例而言，在〇.丨8微米以下的製程中，已 廣泛使用雙嵌刻結構，以製造多層化的半導體積體電路。 所謂的雙嵌刻結構係指金屬沈積於已經在下介電層中圖型 化的導線孔及線中，隨後，在所謂的平坦化步驟中，以諸 如化學機械硏磨法等方法，將過量的金屬移除，以拋光晶 圓表面。 在 R. Liu 等於 pr〇c 2〇〇〇IITC，ρρ· 11 卜]1 3 (2 0 00)上 (2) (2)1223404 發表的 ’’Single Mask Metal-In sulator-Metal( ΜIM)1223404 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a stacked metal ~ insulator-metal capacitor and a method for manufacturing the same. More specifically, in the manufacture of integrated circuits, a copper embedded structure is formed. Stacked metal-insulator-metal capacitors in. [Previous technology] The capacitor is one of the necessary components in the integrated circuit, and plays the functions of voltage delta adjustment, filtering, and other functions in the circuit. In semiconductor integrated circuits, common types of capacitors include polycrystalline silicon-insulator-polycrystalline silicon capacitors, metal-insulator-metal capacitors, and the like. Among them, metal-insulator-metal capacitors have low contact resistance, so their Rc 値 is low, and they are often used in integrated circuits that require high speed. They are also often found in different applications such as analog circuits and hybrid circuits. In recent years, the "significant improvement in the miniaturization of the accompanying integrated circuit" has gradually replaced the aluminum conductor in the metallization process of the latter process in the integrated circuit manufacturing process with the copper conductor having a smaller conductivity. In addition, in today's integrated circuit manufacturing processes, for example, in the process below 0.8 micron, the dual-embedded structure has been widely used to manufacture multilayer semiconductor integrated circuits. The so-called double-etched structure means that metal is deposited in the wire holes and lines that have been patterned in the lower dielectric layer. Then, in a so-called planarization step, an excess of Metal is removed to polish the surface of the wafer. ‘’ Single Mask Metal-In sulator-Metal (ΜIM) published by R. Liu equals pr〇c 200000IITC, ρρ · 11 bl] 1 3 (2 00 00) (2) (2) 1223404
Capacitor with Copper Damascene Metallization for Sub-0.1 8 // m Mixed Mode Signal and S y s t e m - ο n - a - C h i p ( S o C ) Application”一文中，揭示配合銅製程以製造金屬—絕緣 體一金屬電容器之方法及結構。將參考圖3 A及3 B說明 此習知技藝。圖3 A中所顯示的結構係形成有金屬導電層 且經過化學機械硏磨法平坦化後的結構，其中，代號200 代表介電層，介電層中的溝槽201及202均由銅塡滿，分 別作爲導線及金屬-絕緣體一金屬電容器之下電極。接著 ，如圖 3B所示，以諸如電漿增強化學汽相沈積法 (PECVD)，在嵌亥U結構表面上，再沈積另一介電層20 3以 作爲金屬-絕緣體-金屬電容器之介電質，接著，在介電 層上，以物理汽相沈積法（PVD)，在介電層203上沈積諸 如鋁等金屬，以作爲上電極層204，最後，以微影法，蝕 刻移除金屬-絕緣體-金屬電容器區以外的上電極層，而 形成所需的金屬-絕緣體-金屬電容器。 上述習知的金屬一絕緣體-金屬電容器之結構是平板 電容器的結構，其電容値/單位面積之値較低，且其製造 方法，係在完成嵌刻結構金屬化及平坦化步驟之後，再沈 積介電層及上電極層’並以一增加的光罩執行微影法，以 圖型化上電極層而取得所需的金屬-絕緣體一金屬電容器 。由於此習知技藝並非在形成嵌刻結構金屬化製程期間， 形成所需的金屬-絕緣體-金屬電容器，所以，需要例如 金屬沈積、光罩、蝕刻等繁複的額外製程以形成金屬一絕 (3) (3)1223404 緣體-金屬電容器，故其成本高，效率低。此外，在形成 金屬-絕緣體一金屬電容器時，會在下一個的層間介電層 表面上造成表面地形，此表面地形會使得下一個導線層的 金屬嵌刻製程較難進行並因而在圖型化步驟之前，需要以 化學機械硏磨法，將介電層的表面平坦化。 鑑於上述習知技術之缺失，需要能夠提供成本低、效 率高之方法，以形成金屬-絕緣體一金屬電容器。 【發明內容】 慮及上述問題，本發明的目的係在金屬嵌刻結構金屬 化之過程中，在與導線相同的層中，形成堆疊式金屬一絕 緣體-金屬電容器，而不需要額外的製程步驟。 根據本發明之一態樣，提供堆疊式金屬一絕緣體一金 屬電容器之製造方法，其在形成具有嵌刻結構之多層銅導 線層中，同時形成堆疊式金屬一絕緣體一金屬電容器，該 方法包括下述步驟：底層金屬平板形成步驟，對形成於基 底上具有多個鎢栓塞的接觸層，執行圖型化及蝕刻，以形 成通至基底且深度與該接觸層的厚度相同的開口，再於該 開口中沈積鎢，僅部份地塡充該開口；底層介電層沈積步 驟，沈積介電質以覆蓋形成有底層金屬板的接觸層，作爲 底層介電層；底層介電層圖型化步驟，將底層介電層圖型 化’以形成與鶴检塞連通的導線區；底層介電層金屬化步 驟’於底層介電層上沈積銅，以塡滿該開口及導線區，以 分別形成與底層金屬平板平行之銅平板及與鎢栓塞電連通 -6- (4) (4)1223404 之銅導線；平坦化步驟，對已形成有銅平板及銅導線之底 層介電層執行化學機械硏磨，以使表面平坦化；疊層介電 層沈積步驟，於經過平坦化的表面上，沈積介電層以覆蓋 該平坦化的表面；疊層圖型化步驟，將該疊層介電層圖型 化及触刻成形，以在該疊層介電層中形成用於銅導線的導 線區及用於電容器之平板的開口，電容器平板開口配置成 正好疊置於下層銅平板上，以疊層介電層夾於其間；疊層 金屬化步驟，於經過圖型化及蝕刻成形的疊層介電層上沈 積銅’以塡滿電容器平板開口及導線區，以形成堆疊電容 器的平行銅板及銅導線；疊層平坦化步驟，對已形成有銅 導線及銅平板之疊層執行化學機械硏磨，以使表面平坦化 ;及依序重復執行多次疊層介電層沈積步驟、疊層圖型化 步驟、疊層金屬化步驟、及疊層平坦化步驟，藉以同時形 成多層銅導線層及堆疊式金屬-絕緣體一金屬電容器。 根據本發明，提供堆疊式金屬-絕緣體-金屬電容器 ，其形成於設有積體電路的基底中，基底中設有接觸層及 多層堆疊的第一組金屬嵌刻層及第二組金屬嵌刻層，每一 金屬嵌刻層均具有金屬平板區及導線區以及介電層，該堆 疊式電容器包括：底層鎢平板，形成於接觸層中；第一組 金屬平板，包含多個金屬平板，該多個金屬平板係分別形 成於對應的包含多層堆疊的第一組金屬嵌刻層中的平板區 ，且彼此電連接；第二組金屬平板，包含多個金屬平板， 多個金屬平板係分別形成於對應的包含多層堆疊之第二組 金屬嵌刻層中的平板區，且彼此電連接及與該底層鎢平板 (5) (5)1223404 電連接；及多層介電層’分別形成於該第一組及第二組金 屬嵌刻層中的個別金屬嵌刻層。 另外，根據本發明，介電層之材質爲選自s i N、及 組成的群類之一。而介電層係以電漿增強化學氣相沈 積法（PECVD )沈積而成。 此外，根據本發明，金屬嵌刻層是銅嵌刻層。 本發明能夠形成嵌入於多層金屬導線層中之堆疊式金 屬一絕緣體一金屬電容器。結果，本發明能夠不用增加製 程步驟、以更低的成本 '更有效率地製造金屬一絕緣體一 金屬電容器。而且，所製成的金屬-絕緣體一金屬電容器 之電容器介電質較厚，但是，其電容値/單位面積之値等 於或大於習知技藝之値，且可以大幅降低平板之間的漏電 【實施方式】 將於下參考附圖，說明根據本發明的實施例之製造金 屬一絕緣體一金屬電容器的方法。應瞭解下述說明僅作爲 舉例說明之用，並非用以限定本發明。此外，爲了提供更 淸楚的說明，圖示並未依比例繪製。 下述說明中，根據本發明的實施例的製程步驟及對應 結構，並未涵蓋製造完整的IC電路的完整製程，而是可 以配合半導體技術領域中不同的IC電路中的其它製程以 製造所需的完整I c電路。 將於下說明根據本發明的金屬-絕緣體一金屬電容器 (6) (6)1223404 之製造方法。 首先，參考圖1A，其顯示基底100上形成有接觸層 1 〇 2的結構，接觸層】〇 2中形成有鎢栓塞1 0 4。圖I A所 示的接觸層首先接受圖型化，接著進行微影蝕刻，以致於 如圖1B所示般，在接觸層1〇2中形成用於擬形成的電容 器之底層金屬板106的大開□(相較於金屬栓塞104而言） 。接著，舉例而言，使用化學汽相沈積法（以下簡稱爲 CVD )沈積鎢至此大開口中以作爲用於擬形成的電容器之 一金屬板1 06，因而形成如圖1 B所示的結構。 如同圖1 B所示般，所形成之大開口之深度與接觸層 的厚度實質上相等，但是，沈積於大開口中的例如鎢等金 屬的厚度遠小於鎢栓塞1 〇4的深度，舉例而言，鎢栓塞 1 0 4的深度爲7 〇 〇 0 A，而大開口中的鎢之深度爲3 0 0 0 A， 所以，所沈積的鎢僅塡充大開口下部。接著，參考圖1C ，說明同時形成用於電容器的另一金屬板與另一組金屬栓 塞。以例如P E C V D法，將第一層間介電層1 〇 8沈積於圖 1 B中所示的結構，而形成如圖1 C所示的結構。値得注意 的是，此時形成的第一層間介電層I 〇 8的表面幾何形狀係 符合圖1 B所示的結構之表面幾何形狀。 然後，如圖1 D所示，對第一層間介電層1 〇 8執行圖 型化及蝕刻而形成與鎢栓塞1 連通的導線孔。接著，將 銅沈積於第一層間介電層1 〇 8上及導線孔中，因而形成第 一銅板1 1 2及第一組銅栓塞1〗〇，然後執行化學機械硏磨 法以使表面平坦化，結果，形成如圖1 D所示的結構。 -9- (7) (7)1223404 之後，以同於參考圖1 C之上述方式，在圖1D之結 構上形成第二層間介電層1 1 4，再以同於上述參考圖4之 方式，形成第二組銅栓塞1 1 6、及第二銅板1 1 8，因而形 成如圖1 E所示之結構。注意，此時所形成之第二組銅栓 塞1 1 6係與上述第一組銅栓塞1 1 0相連通，且所形成之第 二銅板1 1 8係與第一銅板具有實質上相同的尺寸。在本實 施例中，金屬板1 〇 6、第一銅板1 1 2、及第二銅板1 1 8之 間的電連接關係爲金屬板1 06與第二銅板1 1 2電連接，但 此二者均未與第一銅板形成電連接（圖1C中並未顯示） 〇 値得注意的是，從上述圖1C至圖1E之第一或第二 銅板係與同層中的銅導線（銅栓塞）同時在相同步驟中形 成。換言之，在製造銅導線的步驟中同時形成用於電容器 之金屬平行板’但卻不需要特別針對金屬板增加任何額外 的光罩及步驟。 接著，根據需求，重覆上述參考圖1C至圖1E所述 的步驟，形成如圖1 F所示的堆疊式金屬一絕緣體-金屬 電容器1 2 0。如圖1 F所示，在每一形成有金屬平行板的 金屬嵌刻結構之導線層上又形成另一具有金屬平行板的金 屬嵌刻結構之導線層。重覆之次數係取決於所欲形成的電 路之需求。如此形成之用於擬形成的金屬電容器之金屬平 行板的總數爲導線層的總數加上接觸層之數目，在本實施 例中接觸層之數目爲一。 圖2係顯示根據本發明的實施例所製成的堆疊式多層 -10 - (8) (8)1223404 金屬-絕緣體-金屬電容器之電連接，其中，鎢板與第二 銅板、第四銅板、· · ·直至第（n - 1 )銅板係彼此電連接 ，等同於平板電容器之一金屬板，而第一銅板、第三銅板 、· · ·直至第η個銅板係彼此電接，等同於平板電容器 之另一金屬板。 將於下說明根據本發明的方法製成之電容器的電容値 〇 理論上，平板電容器的電容値爲： C = eA/d其中，ε是電容器介電質的介電常數，a 是金屬板的面積，d是這些板之間的間距。 根據此等式，可得知根據本發明所製成的堆疊式 ΜIM電容器結構雖然具有較大的d値，d値與導線孔的高 度相同，但是，平板的總面積爲ηΑ，η是銅導線層的數 目。注意，由於根據本發明，銅板係與銅導線層同時形成 ’所以’銅導線層的數目與銅板數目相同。所以，假使導 線孔的高度爲3 00 0Α且裝置具有5個銅金屬層時，則堆疊 的電容器之電容値將等於具有60〇Α厚的介電質之平板電 容器。 根據本發明之ΜΙΜ電容器製造方法具有之優點爲： 相較於導線的基本製程，不需要任何增加的光罩或製程步 驟，即可製成堆疊的電容器。 此外，根據本發明之ΜΙΜ電容器，較厚的的介電質 可fe供甚佳的平行板至平行板漏電保護並因而製成更堅固 可靠的裝置。 -11 - 1223404 Ο) 在上述說明中，以舉例方式說明本發明，但是本發明 並不限於上述之詳細說明，習於此技藝者在暸解上述說明 之後，在不悖離本發明的精神及範圍下，執行不同的變化 及修改。應瞭解本發明之範園係由後述之申請專利範圍所 界定。 【圖式簡單說明】· 從參考附圖之上述詳細說明中，可以更加淸楚地瞭解 · 本發明的上述及其它目的與優點，其中： 圖1 A - 1 F係剖面視圖’用以說明根據本發明的實施例 之堆疊式金屬-絕緣體-金屬電容器的製造方法； ' 圖2係顯示根據本發明的實施例製成之堆疊式金屬一 · 絕緣體一金屬電容器的各金屬平板間的電連接。 圖3A-3B係剖面視圖，用以說明習知的金屬—絕緣 體-金屬電谷益之結構及製造方法。 _ 主要元件對照表 1 00 :基底 1 〇 2 :接觸層 1 〇 4 :鎢栓塞 106 :底層金屬板 1 〇 8 :第一層間介電層 1 1 〇 :第一組銅栓塞 1 1 2 :第一銅板 ‘12- (10)1223404 1 1 4 :第二層間介電層 1 1 6 :第二組銅栓塞 1 1 8 :第二銅板 1 2 0 :堆疊式金屬-絕緣體-金屬電容器 2 00 :介電層 2 0 1 :溝槽 202 :溝槽"Capacitor with Copper Damascene Metallization for Sub-0.1 8 // m Mixed Mode Signal and System-ο n-a-C hip (S o C) Application" article, reveals the use of copper process to manufacture metal-insulator-metal capacitors Method and structure. This conventional technique will be explained with reference to Figs. 3 A and 3 B. The structure shown in Fig. 3 A is a structure formed by a metal conductive layer and planarized by a chemical mechanical honing method, where the code 200 represents The dielectric layers, the trenches 201 and 202 in the dielectric layer are filled with copper, respectively, as the wires and the lower electrodes of the metal-insulator-metal capacitor. Then, as shown in FIG. 3B, the chemical vapor phase is enhanced by, for example, a plasma. Deposition method (PECVD), on the surface of the embedded structure, another dielectric layer 20 3 is deposited as the dielectric of the metal-insulator-metal capacitor, and then, on the dielectric layer, a physical vapor deposition method is used. (PVD), a metal such as aluminum is deposited on the dielectric layer 203 as the upper electrode layer 204, and finally, the upper electrode layer outside the metal-insulator-metal capacitor region is etched and removed by lithography to form a desired of It belongs to the insulator-metal capacitor. The conventional metal-insulator-metal capacitor structure described above is a flat capacitor structure, which has a low capacitance / unit area, and its manufacturing method is to complete the metallization of the embedded structure and After the planarization step, a dielectric layer and an upper electrode layer are further deposited, and a lithography method is performed with an added photomask to pattern the upper electrode layer to obtain the required metal-insulator-metal capacitor. The technique is not to form the required metal-insulator-metal capacitor during the metallization process of forming the embedded structure. Therefore, complicated additional processes such as metal deposition, photomask, and etching are required to form the metal one. (3) (3) 1223404 Margin-metal capacitor, so its cost is high and efficiency is low. In addition, when forming a metal-insulator-metal capacitor, it will cause surface topography on the surface of the next interlayer dielectric layer. This surface topography will make the next wire layer The metal embedding process is difficult to perform and therefore, before the patterning step, the surface of the dielectric layer needs to be planarized by a chemical mechanical honing method. In view of the lack of the above-mentioned conventional technologies, it is necessary to provide a method with low cost and high efficiency to form a metal-insulator-metal capacitor. SUMMARY OF THE INVENTION In view of the above problems, the object of the present invention is to metalize a metal embedded structure. In the process, a stacked metal-insulator-metal capacitor is formed in the same layer as the wire without the need for additional process steps. According to one aspect of the present invention, a method for manufacturing a stacked metal-insulator-metal capacitor is provided. The method includes forming a stacked metal-insulator-metal capacitor in a multilayer copper conductor layer having an embedded structure. The method includes the following steps: a step of forming a bottom metal plate to contact a plurality of tungsten plugs formed on a substrate; Layer, performing patterning and etching to form an opening that leads to the substrate and has the same depth as the thickness of the contact layer, and then deposit tungsten in the opening to partially fill the opening; the underlying dielectric layer deposition step, Dielectric is deposited to cover the contact layer formed with the underlying metal plate as the underlying dielectric layer; the underlying dielectric layer pattern A patterning step of patterning the underlying dielectric layer to form a lead region communicating with the crane plug; a step of metalizing the underlying dielectric layer to deposit copper on the underlying dielectric layer to fill the opening and the lead region, A copper plate that is parallel to the underlying metal plate and a copper wire that is in electrical communication with the tungsten plug are formed respectively. The planarization step is performed on the underlying dielectric layer on which the copper plate and the copper wire have been formed. Chemical mechanical honing to flatten the surface; a stacked dielectric layer deposition step, depositing a dielectric layer on the planarized surface to cover the planarized surface; a stacked patterning step, the stack The dielectric layer is patterned and etched to form a lead area for copper wires and an opening for a capacitor plate in the laminated dielectric layer. The capacitor plate opening is configured to be stacked exactly on the underlying copper plate. With a stacked dielectric layer sandwiched therebetween; in the stacked metallization step, copper is deposited on the stacked dielectric layer that has been patterned and etched to fill the opening of the capacitor plate and the wire area to form a stacked capacitor Parallel copper plate and copper guide ; Lamination planarization step, performing chemical mechanical honing on the lamination where copper wires and copper flat plates have been formed to planarize the surface; and sequentially repeating multiple steps of lamination dielectric layer deposition steps and lamination patterns Forming step, stacking metallization step, and stacking planarization step, thereby forming a multilayer copper wire layer and a stacked metal-insulator-metal capacitor at the same time. According to the present invention, a stacked metal-insulator-metal capacitor is provided, which is formed in a substrate provided with an integrated circuit. The substrate is provided with a contact layer and a first group of metal embedded layers and a second group of metal embedded layers. Layer, each metal embedded layer has a metal plate area, a wire area and a dielectric layer. The stacked capacitor includes: a bottom tungsten plate formed in the contact layer; a first group of metal plates including a plurality of metal plates, the A plurality of metal flat plates are respectively formed in corresponding flat areas in the first group of metal embedded layers including a plurality of stacks, and are electrically connected to each other; a second group of metal flat plates includes a plurality of metal flat plates, and a plurality of metal flat plates are respectively formed. In a corresponding flat plate region in the second set of metal etched layers including a multilayer stack, which are electrically connected to each other and to the underlying tungsten flat plate (5) (5) 1223404; and a multi-layer dielectric layer is formed in each of the first Individual metal engraving layers in one and the second group of metal engraving layers. In addition, according to the present invention, the material of the dielectric layer is one selected from the group consisting of s i N and. The dielectric layer is deposited by plasma enhanced chemical vapor deposition (PECVD). In addition, according to the present invention, the metal embedded layer is a copper embedded layer. The invention can form a stacked metal-insulator-metal capacitor embedded in a plurality of metal wire layers. As a result, the present invention can more efficiently manufacture metal-insulator-metal capacitors at a lower cost without adding process steps. In addition, the dielectric of the fabricated metal-insulator-metal capacitor is relatively thick, but its capacitance 値 / unit area 値 is equal to or greater than that of conventional techniques, and the leakage between the plates can be greatly reduced. [Mode] A method of manufacturing a metal-insulator-metal capacitor according to an embodiment of the present invention will be described below with reference to the drawings. It should be understood that the following description is for illustrative purposes only and is not intended to limit the present invention. In addition, for better explanation, the illustrations are not drawn to scale. In the following description, the process steps and corresponding structures according to the embodiments of the present invention do not cover the complete process of manufacturing a complete IC circuit, but may cooperate with other processes in different IC circuits in the field of semiconductor technology to manufacture the required Complete I c circuit. A method for manufacturing the metal-insulator-metal capacitor (6) (6) 1223404 according to the present invention will be described below. First, referring to FIG. 1A, it shows a structure in which a contact layer 102 is formed on a substrate 100, and a tungsten plug 104 is formed in the contact layer 02. The contact layer shown in FIG. IA is first subjected to patterning, followed by lithographic etching, so that as shown in FIG. 1B, a wide opening of the underlying metal plate 106 for the capacitor to be formed is formed in the contact layer 102. (Compared to metal plug 104). Next, for example, a chemical vapor deposition method (hereinafter abbreviated as CVD) is used to deposit tungsten into this large opening as a metal plate 106 for a capacitor to be formed, thereby forming a structure as shown in FIG. 1B. As shown in FIG. 1B, the depth of the formed large opening is substantially equal to the thickness of the contact layer. However, the thickness of the metal such as tungsten deposited in the large opening is much smaller than the depth of the tungsten plug 104. For example, In other words, the depth of the tungsten plug 104 is 7000 A, and the depth of tungsten in the large opening is 300 A. Therefore, the deposited tungsten only fills the lower part of the opening. Next, referring to FIG. 1C, it is described that another metal plate for the capacitor and another group of metal plugs are simultaneously formed. The first interlayer dielectric layer 108 is deposited on the structure shown in FIG. 1B by, for example, the P E C V D method, to form the structure shown in FIG. 1C. It should be noted that the surface geometry of the first interlayer dielectric layer 108 formed at this time conforms to the surface geometry of the structure shown in FIG. 1B. Then, as shown in FIG. 1D, the first interlayer dielectric layer 108 is patterned and etched to form a wire hole communicating with the tungsten plug 1. Next, copper is deposited on the first interlayer dielectric layer 108 and the wire hole, thereby forming a first copper plate 1 12 and a first group of copper plugs 1 and then performing a chemical mechanical honing method to make the surface As a result of the planarization, a structure as shown in FIG. 1D is formed. -9- (7) (7) 1223404 After that, the second interlayer dielectric layer 1 1 4 is formed on the structure of FIG. 1D in the same manner as described above with reference to FIG. 1C, and then in the same manner as described above with reference to FIG. 4 A second group of copper plugs 1 1 6 and a second copper plate 1 1 8 are formed, thus forming a structure as shown in FIG. 1E. Note that the second group of copper plugs 1 1 6 formed at this time is in communication with the first group of copper plugs 1 1 0 described above, and the second copper plate 1 1 8 formed is substantially the same size as the first copper plate . In this embodiment, the electrical connection relationship between the metal plate 106, the first copper plate 1 12, and the second copper plate 1 1 8 is that the metal plate 106 and the second copper plate 1 12 are electrically connected, but these two None of them is electrically connected to the first copper plate (not shown in FIG. 1C). It should be noted that the first or second copper plate from the above-mentioned FIG. 1C to FIG. 1E is connected to the copper wire (copper plug) in the same layer. ) Formed in the same step at the same time. In other words, a metal parallel plate for a capacitor is simultaneously formed in the step of manufacturing a copper wire, but it is not necessary to add any additional masks and steps specifically for the metal plate. Next, according to the requirements, the steps described above with reference to Figs. 1C to 1E are repeated to form a stacked metal-insulator-metal capacitor 120 as shown in Fig. 1F. As shown in FIG. 1F, on each of the conductive layer of the metal embedded structure of the metal parallel plate, another conductive layer of the metal embedded structure of the metal parallel plate is formed. The number of repetitions depends on the demand of the circuit to be formed. The total number of metal parallel plates thus formed for the metal capacitor to be formed is the total number of wire layers plus the number of contact layers. In this embodiment, the number of contact layers is one. Fig. 2 shows the electrical connection of a stacked multilayer -10-(8) (8) 1223404 metal-insulator-metal capacitor made according to an embodiment of the present invention, in which a tungsten plate and a second copper plate, a fourth copper plate, · · · Up to (n-1) copper plates are electrically connected to each other, which is equivalent to one metal plate of a plate capacitor, and the first copper plate, the third copper plate, · · · · Up to the nth copper plate system are electrically connected to each other, which is equivalent to a flat plate Another metal plate of the capacitor. The capacitance of the capacitor made according to the method of the present invention will be described below. Theoretically, the capacitance of a flat capacitor is: C = eA / d where ε is the dielectric constant of the capacitor dielectric and a is of the metal plate. Area, d is the spacing between these plates. According to this equation, it can be known that although the stacked MIM capacitor structure made according to the present invention has a larger d 値, where d 値 is the same height as the wire hole, the total area of the plate is ηA, and η is a copper wire. The number of layers. Note that, according to the present invention, the number of copper wiring layers is the same as the number of copper plates because the copper plates are formed simultaneously with the copper wiring layers. Therefore, if the height of the conductive hole is 3 00 A and the device has 5 copper metal layers, the capacitance of the stacked capacitor 値 will be equal to a flat capacitor with a dielectric thickness of 60 A. The manufacturing method of the MIM capacitor according to the present invention has the advantages that, compared with the basic process of the wire, a stacked capacitor can be made without any additional photomask or process steps. In addition, according to the MI capacitor of the present invention, a thicker dielectric can provide excellent parallel plate to parallel plate leakage protection and thus make a more robust and reliable device. -11-1223404 〇) In the above description, the present invention is described by way of example, but the present invention is not limited to the above detailed description. Those skilled in the art will understand the above description without departing from the spirit and scope of the present invention. Next, perform different changes and modifications. It should be understood that the scope of the present invention is defined by the scope of patent application described later. [Brief description of the drawings] · The above and other objects and advantages of the present invention can be understood more clearly from the above detailed description with reference to the drawings, wherein: Fig. 1 A-1 F series cross-sectional views are used to explain the basis A method for manufacturing a stacked metal-insulator-metal capacitor according to an embodiment of the present invention; FIG. 2 shows the electrical connection between the metal flat plates of a stacked metal-insulator-metal capacitor made according to an embodiment of the present invention. 3A-3B are cross-sectional views for explaining a conventional metal-insulator-metal electric valley structure and manufacturing method. _ Main component comparison table 1 00: substrate 1 〇2: contact layer 1 〇4: tungsten plug 106: bottom metal plate 1 〇8: first interlayer dielectric layer 1 1 〇: first group copper plug 1 1 2: First copper plate '12-(10) 1223404 1 1 4: second interlayer dielectric layer 1 1 6: second group of copper plugs 1 1 8: second copper plate 1 2 0: stacked metal-insulator-metal capacitor 2 00 : Dielectric layer 2 0 1: Trench 202: Trench
2 0 3 :介電層 2 0 4 :上電極層2 0 3: Dielectric layer 2 0 4: Upper electrode layer
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