玖、發明說明： 【發明所屬之技術領域】 本發明是有關於一種與作業系統無關之遠端資料存 取方法與與使用該方法之電腦，特別是指一種利用處理器 5 之系統管理模式來進行遠端資料存取之方法與使用該方 法之電腦。 【先前技術】 由於電腦網路日漸普及，一但某電腦之需求不足，例 如需要進行應用程式、作業系統的更換、升級時，常會透 _ 過區域網路、網際網路等，自一遠端電腦上下載所需要的 程^，然而對於網路系統管理者而言，為了能夠有效地統 笞里狄莩握各電腦的情況，因此遂有藉由遠端電腦來統 一集中、管理所有軟體的觀念產生。 網路電腦（network computer，NC)，乃是一僅具備有簡 單之作業系統的終端電腦，在此電腦一開機後，它會自動 地連接到一遠端電腦（伺服器）進行資料存取，並自遠端的 電月6?下載其品執行的軟體，因此若所有的終端電腦需要進 善 行軟體的更新、升級等動作，僅需在遠端的伺服電腦上一 次進行以後，待下次網路電腦再捉取軟體時，即「彷彿」 -〇 已更新其自身的軟體（事實上，網路電腦並未具備有任何應 · 用程式）。但是，網路電腦的問題在於應用程式僅限於Java 或JavaScript，因此並不能採用現有的應用程式（例如 Microsoft Word)，使其功能大為受限。 另一種架構則是所謂的遠端安裝服務（rem〇te 4 1222291 5 aJ】atI0n SerViCes，Ris)，其概念是利用一⑽伺服 管理終端電腦所需要的軟體，然其缺點在於··在：行 =安裝的動作前，除了需要在R f s伺服器與終端電腦:: 女4有相同的作H統與相對應的RIS應用程式外，尚兩 對終端電腦作進—步設定（例如DHCP、DNS主機），另二 方面’由於資料在經由RIS伺服器傳送至終端電腦前，需 先經由RIS應用程式將其轉換成RiS格式，因此若所欲傳 达的資料具備有防拷保護機制而非標準的資料格式時在 此轉換的過程中即可能產生錯誤。 10 15 ^ 圖1所示之「資料映像系統」，其係在電腦500 中裝設有-模擬器(emu】ator)202,此模擬器2〇2是用來截 斷作業系統所發出6"/0訊號(讀/寫要求，read/write q )換。之，此杈擬器202之功能在於作為一虛擬硬 碟’且其自身並與遠端電腦（飼服器）2〇4透過網路連線，當 模擬器202 -旦接收讀寫要求時，即會先由自身實體硬： η"ί行搜尋並判斷資料是否為最新，若非最新則會透 過模擬器202自遠端電腦204之實體硬4 205中自動下載 最新㈣料至實體硬碟1則，自動完成更新、升級的動 作L雖此法較前述方法為佳’但由於此模擬器2〇22. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a remote data access method and a computer using the method independent of the operating system, and particularly to a system management mode using the processor 5 Method for remote data access and computer using the method. [Previous technology] Due to the increasing popularity of computer networks, once a computer's needs are insufficient, such as when applications, operating systems need to be replaced or upgraded, it will often pass through a local network, the Internet, etc. Download the programs you need on your computer ^ However, for the network system manager, in order to effectively control the situation of each computer, there is a unified and centralized management of all software by remote computers. Ideas arise. A network computer (NC) is a terminal computer with a simple operating system. When this computer is turned on, it will automatically connect to a remote computer (server) for data access. And download the software for its products from the remote electricity month, so if all terminal computers need to perform good software update, upgrade and other actions, you only need to do it once on the remote server computer and wait for the next time When the road computer captures the software, it is "as if" -〇 has updated its own software (in fact, the network computer does not have any application programs). However, the problem with network computers is that applications are limited to Java or JavaScript, so existing applications (such as Microsoft Word) cannot be used, limiting their functionality. The other architecture is the so-called remote installation service (remote 4 1222291 5 aJ) atI0n SerViCes, Ris. Its concept is to use a server to manage the software required by the terminal computer, but its disadvantages are: = Before the installation, in addition to the R fs server and the terminal computer :: Female 4 has the same operating system and corresponding RIS applications, there are still two pairs of terminal computers to make further settings (such as DHCP, DNS Mainframe), the other two aspects, because the data needs to be converted into RiS format by RIS application before being transmitted to the terminal computer through the RIS server, so if the data to be transmitted has a copy protection mechanism instead of standard Data may be formatted incorrectly during this conversion. 10 15 ^ The "data mapping system" shown in Figure 1, which is equipped with an emulator ator 202 in the computer 500. This simulator 202 is used to intercept the operating system. 6 " / 0 signal (read / write request, read / write q). In other words, the function of this simulator 202 is to act as a virtual hard disk and connect itself to a remote computer (feeder) 204 via a network. When the simulator 202 receives a read and write request, That is, it will first be hardened by its own entity: η " Search and determine whether the data is up-to-date. If it is not the latest, it will automatically download the latest data from the physical hard disk 4 of the remote computer 204 to the physical hard disk 1 through the simulator 202 , The automatic completion of the update and upgrade action L Although this method is better than the previous method ', but because of this simulator 202
20 需負責資料存取的全部過程’因此需要獨立的中央處理 器、，態P錢存取記憶體、控制單元...等構件，傲然成為 -具微型主機’故此模擬器搬之建置成本甚高，特別是 在具有多冑電腦500的網路架構下’若每台電腦則皆行 裝設’則其整體成本更甚可觀。 5 另外，上段中所述之更詳細内容，已進_步揭露於美 國專利$ 6,477,624料财巾，以下將其全文併入本案 作為參考資料。 〃 【發明内容】 由上述習知技術中可以了解，需要一種能夠以成本低 廉方式來建構模擬器’特別是，若能使模擬器獨立於作業 系、’先外工作，即錢得模擬^㈣相容於各式電腦而能增 加其使用彈性。 因此，本發明之目的即在於提供一種建置成本低廉， 並能夠獨立於作業系統外之遠端資料存取方法及使用該 方法之電腦。 …於是，在-較佳實施例中’本發明遠端資料存取方法 是藉由-電腦來存取一遠端電腦中的資料，其步驟是先接 收該電腦中之-處理器欲傳送至—硬碟之讀取要求，接著 利用-模擬器來中斷(trap)該讀取要求，在中斷該讀取要求 後，由該模擬器發送一中斷訊號至該處理器， 進入一與一作業系統無關之獨立作業模式。 /处 當該處理器進入該獨立作業模式後，自該遠端電腦之 -硬碟中讀取相對應之資料後儲存在一資料暫存器中，最 後模擬器即發送一中斷要求（IRQ)至回復至正常模式下的 該處理器，完成讀取動作。20 Responsible for the entire process of data access 'so components such as an independent central processing unit, state memory access memory, control unit, etc., proudly become-with a micro-host', so the simulator installation cost Very high, especially in a network architecture with multiple computers 500, 'if each computer can be installed', the overall cost is even more considerable. 5 In addition, the more detailed content described in the previous paragraph has been further disclosed in the US patent $ 6,477,624, which is incorporated herein by reference in its entirety.发明 [Summary of content] As can be understood from the above-mentioned conventional technology, there is a need for a simulator that can be constructed in a cost-effective manner. In particular, if the simulator can be independent of the operating system and 'external work, that is, money simulation ^ ㈣ Compatible with various computers to increase its flexibility. Therefore, an object of the present invention is to provide a remote data access method and a computer using the method which are low in construction cost and can be independent of an operating system. ... then, in the preferred embodiment, the method of remote data access in the present invention is to access data in a remote computer through a computer, the step of which is to first receive the processor in the computer to send to —Hard disk read request, and then use the simulator to interrupt the read request. After interrupting the read request, the simulator sends an interrupt signal to the processor, and enters an operating system. Irrelevant independent operation mode. After the processor enters the independent operation mode, the corresponding data is read from the hard disk of the remote computer and stored in a data register. Finally, the simulator sends an interrupt request (IRQ) Until the processor returns to the normal mode, the reading operation is completed.
在該較佳實施例中，本發明亦提供一電腦，此電腦是 與一遠端電腦相連線，該電腦包含一處理哭、I 口° 一" έ己憶體， 以及一模擬器。 1222291 在存有複數電腦程式碼’該等電腦程式碼是 :處'在一與一作業系統無關之獨立作業模式下所 執行。該模擬器是與該處理器相連接，並具有 及—緩衝記憶體。 以 5 該解碼器是能夠依據該處理器所發出之—讀取要 求’產生-觸發該處理器、進人該獨立作業模式之中斷訊 號：使該處理器於該獨立作模式下執行該等電腦程式碼， 並當該處理器自該遠端電腦捉取對應於該讀取要长之次 10 料並回復至-正常模式後，發送—中斷要求(卿至該處二 器。該緩衝記憶體則是絲職該處㈣自該遠端電腦中 所捉取的資料。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 15 以下配合參考圖式之一較佳實施例的詳細說明中，將可清 楚的明白。 / 20 參閱圖2與圖3 ’在本發明之系統架構下，一近端電 腦100是與一遠端電腦200相連線，且其連線方式可以I 透過區域網路（LAN)'廣i或區域網路(WLAN)或是網際網路 (Internet)等等，因此，近端電腦1〇〇能透過標準的網路傳 輸協定（例如TCP/IP)來與遠端電腦2〇〇相通訊。 近端電腦100中包含有一供實體網路連接的網路介面 卡（NIC)l、一與網路介面卡i相連接之處理器 (processor^、一唯讀記憶體3、一隨機存取記憶體（RAM， 或稱主記憶體）4。唯讀記憶體3中已存有複數電腦程式 7 1222291 碼，或稱為基本輸入/輸出系統（BIOS)，是當近端電腦100 開機時，由處理器2自唯讀記憶體3中加以捉取、執行， 以便進行自我開機測試（POST)等動作。 一般而言’上述各構件皆是設置在一主機板（圖未不） 5 上，且此主機板會提供有各式標準的擴充匯流排，例如 IDE、ISA、AGP···等等，供使用者擴充之用。特別是，一 般在近端電腦100上更要需有一安設在IDE匯流排300上 之硬碟（第一儲存裝置，圖未示），以便儲存作業系統，例 如 Microsoft Windows 98、Windows2000、WindowsNT 等 10 等，然而在本發明之架構下，實體硬碟則非必要，關於此 部分將於下文中再詳細說明。 特別要說明的是，處理器2特別是指Intel 80386以後 型號之處理器，例如Intel 80486、Pentium…，或是AMD K5、K6等具備有能夠在一獨立於作業系統外之獨立作業 15 模式的處理器2。所謂的獨立作業模式，乃是指處理器2 之運作能夠不涉及任何應用程式或作業系]统之作業模 式，一個例子是系統管理模式（system management mode, SMM)，起初是由Intel公司為了便於電源管理所設計的工 作模式，它僅需利用一系統管理中斷（SMI)信號來觸發處理 20 器2，即能使處理器2進入此模式，而在此模式下，處理 器2依然具備有支援網路驅動程式、系統週邊驅動程式、 資料安全監控等能力。 當處理器2由正常模式進入系統管理模式中時，會先 儲存正常模式下所執行之程式碼狀態，並進入主記憶體4 8 1222291 中一獨立的定址空間來執行相對應的SMM程式碼 (subroutines)，4列 士口圖 5 所示 3000:FFFh〜3000:0000h 間， 因此具有極高的安全性且與作業系統或應用程式皆無關 連，而當處理器2執行SMM電腦程式碼中之指令後， 5 即會回到原先正常模式下，繼續受到作業系統之控制。至 於處理器2於此系統管理模式下所執行的功能，端視SMM 程式碼之編寫内容而定。 另一個相類似的模式是線上模擬（in circuit simulator， ICE)模式，或稱偵錯模式（debugging mode)、探測模式 10 (probe mode)等，係為了便於進行程式的偵錯所設定之一 處理器模式，所能支援的功能大致與上述系統管理模式無 異，故不再贅述。不同的是，觸發處理器2進入線上模擬 模式之訊號是R/S#信號（以Intel Pentium處理器為例），若 欲使處理器2脫離線上模擬模式，則是在線上模擬模式下 15 所執行的電腦程式碼中加入「end profoe mode j指令，或 是以外部硬體使R/S#信號由高變低，再由低變高後（正緣 觸發），即能使處理器2脫離線上模擬模式而回復到正常模 式下。 因此，本實施例中更包含一與處理器2相連接之記憶 20 體（SMM handler)5，其内部儲存有複數SMM電腦程式碼， 這些SMM電腦程式碼並能夠分為多個模組，各個模組能 夠依據特定的I/O指令，對遠端電腦200中之一第二儲存 裝置（圖未示）進行讀取/寫入的動作。當然，這些SMM電 腦程式碼亦可與BIOS —併儲存在唯讀記憶體3中，待電 9 1222291 腦100開機後，即自動載入主記憶體4中，並當處理器2 進入系統管理模式後，才會由特定的記憶體定址空間中加 以捉取、執行。 此外，本實施例更包含一模擬器6，此模擬器6是裝 5 設在電腦100中，並具有一介面單元61、一解碼器 (decoder)62、一控制暫存器（control register)63、一 狀態暫 存器（status register)64、一錯誤暫存器（error register)65、 一計數暫存器（counter register)66 、 兩多工器 (multiplexer)67、68，以及緩衝記憶體（buffer RAM)69。 10 介面單元61，在本實施例中是指一 IDE介面，因此能 藉由此介面單元61，使得模擬器透過IDE匯流排300與處 理器2相連接。當然，其它諸如ATA、SCSI'ATAPI、ATA-E、 ESDI、USB等介面，亦屬本實施例之一簡單變化而已。 解碼器62是與介面單元61相連接，也就能接收來自 15 於處理器2的控制信號、資料信號以及位址信號，當然， 如圖3所示，此三種信號分別是由控制匯流排（control bus)、資料匯流排（data bus)，以及位址匯流排（address bus) 所傳送。當解碼器62接收到來自於處理器2的I/O信號 後，除了能依據該信號之内容，解碼為欲傳送至特定暫存 20 器63〜66上的控制信號外，尚能依據I/O信號而送出一系 統管理中斷（SMI)訊號至處理器2，使得處理器2能進入系 統管理模式並執行SMM電腦程式碼。待處理器2由系統 管理模式回復至正常模式時，解碼器62亦能發出中斷要 求（IRQ)。 10 5 %^6，之_要求_’其目的為通知作業 ^貧料傳送動作之告-段m的時機為每當計數暫 存器66倒數至零時（表示傳送成功）或SMM電腦程式碼將 U錯誤代碼填人錯誤暫#|| 65時（表㈣送失敗），俾使 作業系統能依據狀態暫存器64、錯誤暫存器65，以及計 數暫存器66之内容判斷資料傳送是否成功或失敗。中斷 要求陶)之種類依模擬之儲存裝置而定，在本實施例中因 板擬IDE介面裝置’故為IRQ14(第十四號中斷，為主要 10 IDE介面所使用）或IRQ15(第十五號中斷，為次要咖介 面所使用）。 15 控制暫存器63能依SMM電腦程式碼來控制資料的讀 取或寫入。狀態暫存器64是用來儲存目前模擬器6為輸 入（input)、凟出（readout)等狀態的資訊，以及緩衝記憶體 69是否為空位（empty)、滿溢（化⑴等狀態的資訊。錯誤暫 存器65是當錯誤發生時，即會儲存有表示「錯誤」的資 訊。計數暫存器66則是用來儲存讀取或寫入時，下一個 緩衝6己憶體69中資料的位址。這些暫存器ο〜66與一般 镛 暫存器的功能大致相同，且為熟知此技者所能輕易了解， 故不再詳細贅述。 20 緩衝記憶體69是用來儲存處理器2自遠端電腦200 中所讀取回來的資料，此部分將在下文中一併說明。在本 實施例中，緩衝記憶體69之儲存容量大小可以是512In the preferred embodiment, the present invention also provides a computer, which is connected to a remote computer. The computer includes a crying device, a mouthpiece, and a simulator. 1222291 In the presence of plural computer codes, these computer codes are: executed in an independent operation mode that is independent of an operating system. The simulator is connected to the processor and has and-buffer memory. 5 The decoder is able to generate-trigger the processor and enter the independent operation interrupt signal according to the "read request" issued by the processor: to enable the processor to execute the computers in the independent operation mode. Code, and when the processor captures the data corresponding to the read time from the remote computer and returns to-normal mode, it sends-an interrupt request (Qing to the second device. The buffer memory It is the information collected by the department from the remote computer. [Embodiment] Regarding the foregoing and other technical contents, features and effects of the present invention, a preferred embodiment with reference to the drawings below 15 In the detailed description, it will be clearly understood. / 20 Refer to FIG. 2 and FIG. 3 'Under the system architecture of the present invention, a near-end computer 100 is connected to a far-end computer 200, and the connection method can be I Through a local area network (LAN), a wide area network, a local area network (WLAN), or the Internet, etc., so the near-end computer 100 can pass a standard network transmission protocol (such as TCP / IP ) To communicate with the remote computer 2000. 100 includes a network interface card (NIC) 1 for physical network connection, a processor (processor ^) connected to the network interface card i, a read-only memory 3, and a random access memory (RAM (Or main memory) 4. The read-only memory 3 already has a plurality of computer program codes 7 1222291, or the basic input / output system (BIOS). When the near-end computer 100 is powered on, the processor 2 It is captured and executed in the read-only memory 3 to perform actions such as self-power-on test (POST). Generally speaking, the above components are all set on a motherboard (not shown) 5 and the motherboard Various standard expansion buses will be provided, such as IDE, ISA, AGP, etc., for users to expand. In particular, generally, the near-end computer 100 requires an IDE bus. 300 hard disks (first storage device, not shown) for storing operating systems, such as Microsoft Windows 98, Windows 2000, Windows NT, etc. 10, but under the framework of the present invention, a physical hard disk is not necessary. Some will be explained in more detail below In particular, processor 2 refers to processors of Intel 80386 and later types, such as Intel 80486, Pentium, etc., or AMD K5, K6, etc., which have 15 modes that can operate independently of the operating system. Processor 2. The so-called independent operation mode refers to the operation mode of the processor 2 without involving any application or operating system. An example is the system management mode (SMM). The working mode designed by Intel Corporation for the convenience of power management, it only needs to use a system management interrupt (SMI) signal to trigger the processor 2 to enable the processor 2 to enter this mode. In this mode, the processor 2 Still have the ability to support network drivers, system peripheral drivers, data security monitoring, etc. When the processor 2 enters the system management mode from the normal mode, it will first store the state of the code executed in the normal mode and enter a separate address space in the main memory 4 8 1222291 to execute the corresponding SMM code ( subroutines), as shown in Figure 5 at 4: 3000: FFFh ~ 3000: 0000h, so it has very high security and has nothing to do with the operating system or applications. When the processor 2 executes the instructions in the SMM computer code, After that, 5 will return to the original normal mode and continue to be controlled by the operating system. As for the functions performed by the processor 2 in this system management mode, it depends on the content of the SMM code. Another similar mode is the in-circuit simulator (ICE) mode, or debugging mode (probe mode), etc., which is one of the settings for the convenience of program debugging. Device mode, the supported functions are roughly the same as the above system management mode, so I wo n’t repeat them. The difference is that the signal that triggers processor 2 to enter the online simulation mode is the R / S # signal (take Intel Pentium processor as an example). If you want to take the processor 2 out of the online simulation mode, it is 15 in the online simulation mode. Add the "end profoe mode j" instruction to the executed computer code, or use external hardware to change the R / S # signal from high to low, and then change from low to high (triggered by positive edge), then the processor 2 can be disconnected. The online simulation mode returns to the normal mode. Therefore, in this embodiment, a memory 20 (SMM handler) 5 connected to the processor 2 is also stored, and a plurality of SMM computer program codes are stored therein. These SMM computer program codes It can be divided into multiple modules, and each module can read / write to a second storage device (not shown) in the remote computer 200 according to specific I / O instructions. Of course, these The SMM computer code can also be stored in the read-only memory 3 with the BIOS. When the computer 9 is powered on, it will be automatically loaded into the main memory 4 after it is powered on. After the processor 2 enters the system management mode, Space is addressed by specific memory In addition, this embodiment further includes a simulator 6, which is installed in the computer 100 and has an interface unit 61, a decoder 62, and a control unit. Register (control register) 63, a status register (status register) 64, an error register (error register) 65, a counter register (counter register) 66, two multiplexers (multiplexer) 67, 68, and buffer RAM 69. 10 The interface unit 61 refers to an IDE interface in this embodiment, so the interface unit 61 can be used to make the simulator communicate with the processor 2 through the IDE bus 300. Of course, other interfaces such as ATA, SCSI'ATAPI, ATA-E, ESDI, USB, etc., are just a simple variation of this embodiment. The decoder 62 is connected to the interface unit 61, and can receive data from 15 Control signal, data signal and address signal of processor 2. Of course, as shown in FIG. 3, these three signals are respectively a control bus, a data bus, and an address bus. (Address bus). When After the decoder 62 receives the I / O signal from the processor 2, in addition to being able to decode the signal to be transmitted to the specific temporary storage device 63 ~ 66 according to the content of the signal, it can also be based on the I / O. The signal sends a system management interrupt (SMI) signal to the processor 2 so that the processor 2 can enter the system management mode and execute the SMM computer program code. When the processor 2 returns from the system management mode to the normal mode, the decoder 62 can also issue an interrupt request (IRQ). 10 5% ^ 6, of which _request_ 'is for the purpose of notifying the operation ^ Report of poor material transmission action-The timing of segment m is whenever the counting register 66 counts down to zero (indicating successful transmission) or SMM computer code Fill the U error code into the error temporary # || 65 hours (the table fails to send), so that the operating system can determine whether the data transfer is based on the contents of the status register 64, the error register 65, and the count register 66 Success or failure. The type of interrupt request depends on the simulated storage device. In this embodiment, because the board is intended to be an IDE interface device, it is IRQ14 (the fourteenth interrupt, used by the main 10 IDE interfaces) or IRQ15 (the fifteenth No. interrupt, used by the secondary coffee interface). 15 The control register 63 can control the reading or writing of data according to the SMM computer code. The state register 64 is used to store information about the current state of the simulator 6 as input, readout, and other information, and whether the buffer memory 69 is empty, overflowed, or other states. The error register 65 stores information indicating "error" when an error occurs. The count register 66 is used to store the data in the memory 6 and the next buffer 6 when reading or writing. The addresses of these registers ο ~ 66 are roughly the same as general 镛 registers, and are easily understood by those skilled in the art, so they will not be described in detail. 20 Buffer memory 69 is used to store the processor 2 The data read from the remote computer 200, this part will be described below together. In this embodiment, the storage capacity of the buffer memory 69 may be 512
Bytes，或是 512 Bytes 的倍數（例如 1024、2048···)等等。 為了能夠使得處理器2在正常模式以及系統管理模式 11 1222291 二，：同的1/0痒進行控制信號與資料的傳輸，因 而夕工益67' 68來進行資料與位址路徑的切換，本 實施例中，多工器67是負責讀取/寫人緩衝記憶體的 5 枓路控的切換，多工器68収負責緩衝記憶體 址 路徑的切換。 Μ 10 a夕工杰66、67疋由解碼器' 62所控制，當處理器^ 正常模式下，是經由圖3中之實線箭頭來進行ι/〇她 傳遞”；當解碼器62已接㈣I/G信號，而發送系統管理— 心號給處理器2時，同時控制多工器67、68進行路名 切換，使得控制信號、資料錢，以及位址信號能夠㈣ 圖4中之虛線箭頭來傳送至各個暫存器63〜66與多工录 67 68上。因此在正常模式下，緩衝記憶體的之位址逼 擇’以及貰料的讀取/寫入是經由一路徑，而在系統管理指 式下，則是經由另一路徑，兩者並不互相抵觸。 15 20 荼閱圖5與圖6，當近端電腦1〇〇開機後，會先載入 唯讀記憶體3中之BI0S，並進行自我開機測試（P0ST)， 在自我開機測試無誤後，BIqS即會控制處理器、2送出讀 取要求（read request)來尋找開機程式，在一般的情況下， 疋透過IDE匯流排300來尋找硬碟中的開機程心此時 處理器2尚處於正常模式下，如圖5之路徑①所示。 在本實施例中，雖未具備有實體硬碟，然而，模擬器 之功用即在模擬一實體硬碟，換言之，由於模擬器6是 透過IDE匯流排300與處理器2相耦接，因此處理器二所 送出之讀取要求將會傳送至模擬器6上。 12 1222291 5 10 15 如步驟601所示，由於處理器2「以為」實體硬碟存 在於近端電腦1〇〇中，故透過IDE匯流排300所發出的讀 取要求亦包含了所欲讀取磁區（512 bytes)的位址與相關資 訊等等。接著，如步驟6〇2與路徑②所示，在解碼器62接 收到此一碩取要求後，換言之，即中斷（trap) 了處理器2之 讀取要求，並進一步產生系統管理中斷信號，使得處理器 2進入系統管理模式，並使處理器2得知所欲讀取資料之 位址。 如步驟603與路徑③、④，當處理器2進入系統管理 模式後，即會執行SMM程式碼，並嚐試自遠端電腦 中β取相對應位址的資料。若連線無誤且遠端電腦⑽運 作正常’貝U如步,驟604、605所示，會將所讀取的資料透 過圖5中之虛線路徑儲存在緩衝記憶體的中，如路徑⑤， 此時狀態暫存器64中並會同時儲存有緩衝記憶體69的狀 態0 20 、若因為網路連線錯誤，或是遠端電腦2〇〇故障等 、使得處理器2無法自遠端電腦2〇〇中順利讀取資料 Μ _所錯誤暫存器65中即會儲存有表 狀心的資汛，在此同時，完成自遠端電腦2〇〇 讀取資料的處理器2，由於執行到細指令，因此會自 回復到正常模式下，如步驟，。Bytes, or multiples of 512 Bytes (e.g. 1024, 2048 ...). In order to enable the processor 2 in normal mode and system management mode 11 1222291 II: The same 1/0 tick for control signal and data transmission, so Xiongyi 67 '68 to switch the data and address path, this In the embodiment, the multiplexer 67 is responsible for the switching of the read / write buffer memory, and the multiplexer 68 is responsible for the switch of the buffer memory address path. Μ 10a Xi Gongjie 66, 67 疋 are controlled by the decoder '62, when the processor ^ in normal mode, it is passed through the solid line arrow in Figure 3 ι / 〇 she passes "; when the decoder 62 has been connected ㈣I / G signal and send system management—when the heart number is sent to processor 2, control multiplexers 67 and 68 to switch the path name at the same time, so that the control signal, data money, and address signal can be ㈣ dotted arrows in Figure 4 To transfer to each of the registers 63 ~ 66 and multiplexing records 67 68. Therefore, in normal mode, the address selection of the buffer memory and the read / write of the data are through a path, and Under the system management finger, it is through another path, the two do not conflict with each other. 15 20 Read Figure 5 and Figure 6. When the near-end computer 100 is powered on, it will be loaded into the read-only memory 3 first. BI0S, and perform a self-boot test (P0ST). After the self-boot test is correct, BIqS will control the processor and send a read request to find the boot program. Under normal circumstances, 疋 through the IDE Rank 300 to find the boot process in the hard drive. At this point, processor 2 is still normal. In the formula, it is shown as path ① in Figure 5. In this embodiment, although there is no physical hard disk, the function of the simulator is to simulate a physical hard disk, in other words, because the simulator 6 is converged through the IDE Row 300 is coupled to processor 2, so the read request sent by processor 2 will be transmitted to simulator 6. 12 1222291 5 10 15 As shown in step 601, because processor 2 "thinks" the physical hard disk It exists in the near-end computer 100, so the read request issued through the IDE bus 300 also includes the address and related information of the desired magnetic sector (512 bytes) and so on. Next, as shown in step 602 and path ②, after the decoder 62 receives this master request, in other words, it interrupts the read request of the processor 2 and further generates a system management interrupt signal. The processor 2 is brought into a system management mode, and the processor 2 is informed of the address of the data to be read. If step 603 and paths ③ and ④, when the processor 2 enters the system management mode, it will execute the SMM code and try to obtain the corresponding address data from β in the remote computer. If the connection is correct and the remote computer is working properly, as shown in steps 604 and 605, the read data will be stored in the buffer memory through the dashed path in Figure 5, such as path ⑤, At this time, the state register 64 also stores the state 0 of the buffer memory 69 at the same time. If the network connection is wrong or the remote computer 200 is faulty, etc., the processor 2 cannot be sent from the remote computer. The data was successfully read in 2000. The error register 65 will be stored in the buffer memory. At the same time, the processor 2 that reads data from the remote computer 2000 is completed. To the fine instructions, so it will return to normal mode, such as steps.
能漸二ί ^路徑⑥與步驟_所示，解碼器62會依據狀 2 ^ 64、錯誤暫存器65,以及計數暫存器66等狀態， 回傳一中斷要求(IRQ)至已回復到正常模式下的處理器 13 1222291 5 2’因此對於BIOS而言，即已認為完成讀取的動作。如此， 對一個個磁區進行讀取，則能順利地載入作業系統，以及 其它應用程式，故對於近端電腦10〇而言，雖其自身並不 具備有實體硬碟，’然由於模擬器6之作用，則 電腦200中之資料在近端電腦1〇〇上執行。 ^ 另一方面，若當處理器2於正常模式下，將資料在主 6己憶體4中計异、處理完畢，欲寫入「硬碟」中時，是採 直接記憶體存取(DMA)方式，以一 DMA控制器（圖·"未^ 將此資料送至模擬器6。 10 15 此時真正的資料傳送動作，是由模擬器6送出一系统 管理中斷（SMI)訊號，使得處理器2執行Smm程式碼將此 資料由主記憶體4中透過網路介面卡i直接寫人遠端電腦 200中，至於模擬器6本身則擔任使得D M A控制器能夠正 常作動之標的，以及透過暫存器63〜66回報資料傳送動 作結果之用途，本身並不直接執行資料傳送之動作。如 此，對於DMA控制器本身和使用DMA資料傳送方式之作As shown in the path ⑥ and step _, the decoder 62 will return an interrupt request (IRQ) according to the status of the state 2 ^ 64, the error register 65, and the count register 66. The processor 13 1222291 5 2 'in the normal mode is therefore considered to have completed the reading action by the BIOS. In this way, reading one magnetic zone can smoothly load the operating system and other applications. Therefore, for the near-end computer 10, although it does not have a physical hard disk itself, Device 6, the data in computer 200 is executed on the near-end computer 100. ^ On the other hand, if the processor 2 is in normal mode, the data is stored in the main memory 6 and processed, and the data is to be written into the "hard disk". Direct memory access (DMA) is used. ) Method, a DMA controller (fig. &Quot; did not ^ send this data to the simulator 6. 10 15 At this time, the real data transfer action is that the simulator 6 sends a system management interrupt (SMI) signal, so that The processor 2 executes the Smm code and writes this data from the main memory 4 directly to the remote computer 200 through the network interface card i. As for the simulator 6 itself, it is the target for the DMA controller to operate normally. The registers 63 to 66 report the purpose of the data transfer action result, and do not directly perform the data transfer action. Therefore, for the DMA controller itself and the use of the DMA data transfer method
業系統，都不必施以任何修改，即能將遠端電腦2〇〇中之 資料在近端電腦100上予以存取。 20 因此，對於未配備有硬碟之近端 用本發明達到相同於網路電腦的目的 器2的系統管理模式，所以沒有不相容的問題 電腦100，即可以利 ，且由於是利用處理 只要是近 端電腦謂上配備有_匯流排300，都能夠透過近端+ 腦中之模擬器6來執行、開啟遠端電腦細上之作= 系統或應用程式。 μ 14 1222291 歸納上述，本發明遠端資料存取方法及使用該方法之 电細充分地利用了處理器2的功能，並僅利用數個暫存器 就能夠達到資料讀取的目的，更佳的是，由於模擬器6利 用一般電腦皆有配備之IDE匯流排來相連接，因此模擬器 5 6可適用於各式機型的電腦。 惟以上所述者，僅為本發明之較佳實施例而已，當不 旎以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明書内容所作之簡單的等效變化與修飾，皆 應仍屬本發明專利涵蓋之範圍内。 1〇 【圖式簡單說明】 圖1是-示意圖，說明美國第6,477,624號專利案所 述之資料映像系統； 圖2是一示意圖，說明運用本發明之一較佳實施例的 系統架構； 15 圖3是一方塊圖，說明該較佳實施例之一模擬器； '圖4是-示意圖，說明主記憶體中作業系統、:動程 式，以及SMM程式碼所佔據的位址； 、土圖5是一示意圖，說明一處理器、該模擬器，以及一 运端電腦間的作動；以及 2〇 圖6是-流程圖，說明該較佳實施例在進行資料讀取 時所進行的步驟。 15 1222291 【圖式之主要元件代表符號說明】 100 近端電腦 63 控制暫存器 200 遠端電腦 64 狀態暫存器 1 網路介面卡 65 錯誤暫存器 2 處理器 66 計數暫存器 3 唯讀記憶體 67 多工器 4 隨機存取記憶體 68 多工器 5 記憶體 69 緩衝記憶體 6 模擬器 601- -608 步驟 61 介面單元 62 解碼器 籲 16The industry system can access the data in the remote computer 2000 on the near-end computer 100 without any modification. 20 Therefore, for the near end that is not equipped with a hard disk, the present invention achieves the same system management mode as the target computer 2 of the network computer, so there is no problem of incompatibility with the computer 100, which is profitable, and because the It is said that the near-end computer is equipped with _bus 300, which can be executed by the near-end + simulator 6 in the brain, and the remote computer works = system or application. μ 14 1222291 To sum up, the remote data access method of the present invention and the electric device using the method make full use of the function of the processor 2 and use only a few registers to achieve the purpose of data reading, which is better. What's more, since the simulator 6 is connected by using an IDE bus provided in a general computer, the simulator 5 can be applied to various types of computers. However, the above are only the preferred embodiments of the present invention, and the scope of implementation of the present invention is not limited in this way, that is, the simple equivalent changes and modifications made according to the scope of the patent application and the content of the invention specification of the present invention , All should still fall within the scope of the invention patent. 1〇 [Schematic description] Figure 1 is a schematic diagram illustrating the data mapping system described in US Patent No. 6,477,624; Figure 2 is a schematic diagram illustrating a system architecture using a preferred embodiment of the present invention; 15 Figure 3 is a block diagram illustrating one of the simulators of the preferred embodiment; 'FIG. 4 is a schematic diagram illustrating the operating system, the operating program, and the address occupied by the SMM code in the main memory; It is a schematic diagram illustrating the operations among a processor, the simulator, and a terminal computer; and FIG. 6 is a flowchart illustrating the steps performed by the preferred embodiment when reading data. 15 1222291 [Description of the main components of the diagram] 100 Local computer 63 Control register 200 Remote computer 64 Status register 1 Network interface card 65 Error register 2 Processor 66 Count register 3 Read memory 67 Multiplexer 4 Random access memory 68 Multiplexer 5 Memory 69 Buffer memory 6 Simulator 601- -608 Step 61 Interface unit 62 Decoder 16