TWI222184B - Method with floating gate pull back process to improve the data retention of flash memory - Google Patents

Abstract

A novel method with floating gate pull back process to improve the data retention of Flash/EEPROM is provided. In this method, the floating gate is ""pulled back"" before or after performing cell source implantation, and then Vss oxide spacer deposition and etching, Vss plug deposition and CMP are done. If without pull back process, performing cell source implantation prior to Vss oxide spacer deposition will cause the edge of coupling oxide close to the Vss and floating gate be damaged when doing the cell source implantation. This method can prevent this and therefore improve the data retention.

Description

1222184 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for improving data retention in a memory element, and in particular, to a backward process using a floating gate (f 1 oa ti ng ga te) Ways to avoid data loss. '' [Previous technology] Memory components can be roughly divided into Random Access Memory (RAM) and Read-Only Memory (Read 〇nly)

Memory, ROM) two categories. The random access memory needs power supply to keep data. If the power is lost, the memory will also disappear, so it is also called vol at i le memory. Read-only memory is also called non-vol at memory because the data stored in it will not be lost due to power interruption. Read-only memory includes, but is not limited to, erasable and private Erasabie prc grammabie ROM (EPROM), and electrically erasable programmable read-only memory (ElectricaUy

Erasable Programmable ROM (EEPR0M), and Flash EEPR0M. ,mouth

EEPR0M and flash memory are different from EPR0M which uses UV to clear the chip memory. They are electrically biased to control the gate (control gate), and 40% of the electrons pass from the floating gate (t u η n e 1 i n g) to the control gate to clear the memory. Flash memory is widely used in, for example, memory cards of digital cameras and portable computers. Because of its small size and no moving parts, it is likely that in the future, it will replace the hard disk that stores data in the computer. The demand for it will increase significantly.

Page 5 and 4 (2), = ， In the process of F 丨 ash with self-aligned floating gate, the Vss (voltage source line = connected to the cell source) Unit cell source ions are doped to increase 'and two = resistance'. Refer to Figure 1A. The left side contains floating ㈣ = thick salt source. The thin Ϊ structure is first formed on a substrate 10 made of silicon, for example. Forming a thin 2 :: 102, this oxide layer can usually be referred to as a tunneling oxide fossil layer. Then, for example, a layer of nitrogen is formed by a deposition method to coat a photoresist layer 42: layer ... After the nitride layer m is formed, The lithography of the resist layer is performed. The non-nitrided silicon layer 1 06, _ ui ° scratches the resist layer and exposes a part of the siliconized layer 1 06 for etching | π / is an etching mask, floating the exposed nitrogen The interlayer 10: == formed-opening 110 to expose ... to form a stone oxide layer (cut the photoresist // and then, for example, deposit the square side wall, and the exposed part of the silicon layer 106, the opening no The etched layer 104 is removed by etch-back. Next, a part of the siliconized silicon layer is formed on the sidewall of the opening No., and on the night when it is shielded by the first spacer 108. , And etch the unchemicalized layer 102 in the opening 110. At this point, a dark f-crystalline silicon layer 104 is formed and a part of the tunneling oxygen is exposed. Figure 1A shows an opening 12o that can be selected in the cathodic layer. Cell source ion doping + further deposition of Vss interstitial layer 11 2 is often high energy before it is formed, which will cause penetration = f. In this source ion doping step, the oxide layer 1 0 2 is near the opening 1 2 0 Floating gate 1222184 V. Description of the invention (3) Damage at the edge of the pole layer 104, between the floating interpole and the source region-the injury Λ causes the element ^ to be maintained after the element is in operation. The reduction of the data when the path is undesired will promote the missed connection of the data. ^ The voltage across the graph, for example, 8 volts, is also used for cell polarizing ions after 11 2 ^: 0 cannot be selected in the deposition gap layer Oxide coupling% α Γ pole ion doping step. This kind of source ion doping = 2 ° damage to the gap layer 112, this damage will also occur-the data loss between the source region and the source region. The path decreases by%. "The system shows that you can choose to deposit the gap layer 112 and then do the second: the gap layer to form the second gap wall 112a and exposing After exposing part of the substrate, the unit cell source ion doping step is performed. 112a is usually an oxide, which is used as a Vss plug (not shown) deposited between the floating gate layer 10 and the two-gap soil. Isolation. The same: = source ion doping step will cause intermittent damage close to the opening 120 and reduce the data retention ability. Please refer to Figures 2A to 2D.

The figure shows a floating closed-pole stacked junction with an opening 220; step A) to form a second spacer 212a. Fig. 2D shows the doping of the H-knife etcher and subsequent deposition of Vss plug 214. #SERVICE = cell source ionization (―i Me — P〇llshlng # = 1 mechanically ground cell source ion The replacement system is deposited and the gap layer 2ib is further etched, so it will cause the second gap wall 21: near the opening 220, so that the floating gate and source regions will be used during the subsequent device operation. The phase-injury causes the missing path and reduces the maintenance of the data. The cause of this caution # @ & Health-data leakage The reason for this missing path is also ', Ming Xiongming (4) Including near floating Minor damage to the hole-by-hole formation layer 2 at the gate edge through the image [Content of the invention] ^ The invention provides a method for floating different types of tires and clothes to avoid the above-mentioned path degradation. Data retention, the structure of missing data caused by miscellaneous steps, and the definition method is to "% charge the first gap at the opening of the stack" ^ For example, the etching method will be close to the floating gate layer " backward & quot The dj gate τ layer is removed from the-part, and the second gap wall is formed after it is generated. Ion doping, son doping, and then retreating the floating gate layer, the damage to the source cell separation region is not later, and the cell source ion is carried out at the edge of the floating gate. After the second gap is carved, the second gap wall can be added as a floating gate layer and Vss interpolation. This method also produces a thick gap wall. _ The second part of the barrier between the soil

Vss phase / electrical / ^ isolation effect reduces the connection

Missing of data caused by electrons. [Embodiment] Here, the flow of the-and # ^ > of the present invention will be described. Among them, FIG. 3A 薄 n: According to the manufacturing process shown in FIG. 3, the thin structure is firstly formed, for example, in the stack 4 of Mengerkou—a layer of oxide layer 302, and this oxide layer may be generally referred to as tunneling. 1222184 V. Description of invention (5) Layer has the function of coupling. Furthermore, the tunneling oxide layer 302 is covered, such as; = means to form a floating closed pole can be Shi Xi, for example. Then, for example, the material of the electrode layer 304 is covered with the floating gate layer 304 JL // to form a nitrided dream layer 306. The photoresist layer & will be) covered with the nitrided layer. After formation, Coating-layer lithography step to remove part of the photoresist] 30 6 and then perform 3 06 on the photoresist layer, so as to define the active layer of the device The photoresist layer is cosigma / primary polar region. Next, the lithography is used to remove the rhyme and form-Eryi? = Nitride stone layer_ layer 304, and then the photoresist layer is removed.鈇 ^ ^. The oceanic gate electrode layer (not edged out) of Nimiri is covered with nitridation; for example, a two-layer method forms oxygen and the exposed part of the gate electrode layer 3 () / is over. Then, the sidewalls of G are removed in a manner to remove the formed silicon oxide layer. For example, the sidewalls 3G8 are formed by etching back the sidewalls (that is, remaining in the opening of the opening 31 ° is not etched by the first spacer 3). 8 silicon oxide layer), and exposed part of the tunneling oxide layer 302. ;:; = Open and close pole-side area opening 32o. At this point, the source 苐 3B shown in the figure is not shown in the reversed steps, such as the engraved method. This step is to remove a part of the gate layer 304 of the first gap wall near the opening 32 by means of, for example, isotropic dry etching, so as to produce a quenching effect. The effect of the "growth" of the "growth" of the gate electrode layer is followed by the doping of the cell source ions to generate a source region on the substrate 30. It should be noted that the floating gate layer is performed as described above. Page 9 of 304 1222184 V. Description of the invention (6) The back-off step and the unit cell source ionization are performed before the unit cell source ion doping, and the sequence of the heterogeneous steps is not limited. 302 may cause injury when ion doping is placed near the opening / mouth, but the edge W ^ 04 of the floating gate layer 304 after the damage of the floating gate layer 304 edge region is continuously carried out. The next step, so the part is retracted, so it will not cause the second call: to deposit a gap layer 312 on the substrate 3 and cover all the pieces, of which, the gap layer 3 and- ;-. ^ 0 # 3 Ε «V Λ "-Λ is specifically etched back to form a second gap 312 on the side wall of the opening 32 〇 Γ: part of the gap layer 312 under the 丨 ′ and exposed part of the source electrode Area soil 12 ": j a partition wall 312a is used as a barrier between the floating gate layer 304 and the Vss plug 314 of the next product. Because the floating gate layer is already thick, it can be seen in the figure that the part of the side wall of the floating gate layer 304, that is, the thickness of the gap 3 is thicker than the case where the floating gate layer has not receded, > Great effect. Fig. 3F shows the deposition of the Vss plug 314 and the chemical mechanical polishing for flattening. Examples of materials for VSS plug 3 1 4

Thought silicon. The relatively high voltage to which Vss is connected when the device is operating can be, for example, 8 volts.疋 歹 I Because the floating gate layer 304 recedes, the method of the backward process can avoid the damage of the tunneling oxide layer 3 2 at the edge of the floating gate near the opening 3 2 0, and excludes the deposition or Problems caused by doping cell source ions before further etching the spacer 3 1 2 a. So to avoid the problem of missing data ^

1 V.-S ____ 〆 * After the question,-the ability to hold the two materials at the same time will be improved accordingly. As mentioned earlier, the 郜 彳 1 of this piece was added as the spacer element of the floating gate layer 304 and the Vss plug 314, and the thickness of the gap wall 312a was increased to improve the isolation effect and thus reduce the Vss received at first. The leakage of floating gate data caused by the relatively high voltage of. The above is only one preferred embodiment of the present invention, and is not intended to limit the scope of application of the present invention. Any other changes or modifications made without departing from the spirit disclosed by the present invention shall be covered within the scope of Application 1 described later. Θ

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1222184 Schematic description [Schematic description] Figures 1A to 1C show the three steps of doping the source ion of the cell. FIG. 2A to FIG. 2D show the conventional process steps of doping the source ion of the unit cell. FIG. 3A to FIG. 3F illustrate an embodiment of the backward process method of the present invention. [Simple description of component representative symbols] 1 0 0 3 0 0 Substrate 1 0 2 2 0 2 3 0 2 Tunneling oxide layer 1 0 4 3 0 4 Floating gate layer 1 0 6 3 0 6 Silicon nitride layer 1 0 8 3 0 8 First wall 110 310 Open 120 220 320 Open 1 1 2 2 1 2 3 1 2 Space layer 112a 212a 312a Second wall 1 1 4 2 1 4 3 1 4 Vss plug

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Claims (1)

1222184 VI. Scope of patent application 1. A self-aligned floating gate manufacturing method is applicable to a substrate, and at least includes: forming a first dielectric layer in sequence, a first A conductor layer and a second dielectric layer are formed on the substrate, and a lithographic etching process is performed to remove a portion of the second dielectric layer to form a first opening, and the first opening exposes a portion of the first opening. A conductor layer; forming a first gap wall on a side wall of the first opening and exposing a part of the first conductor layer; performing a first remaining time to remove the exposed part of the first conductor layer and forming A second opening, the second opening exposing a portion of the first dielectric layer; performing a second etch to laterally remove a portion of the first conductor layer at the second opening and performing an ion doping to Forming a source region on the surface of the substrate under the second opening; forming a second gap wall covering the first gap wall and a side wall of the second opening and exposing a part of the surface of the source region; and forming a second conductor Layer fills the second opening and the first opening2. The method for manufacturing a self-aligned floating gate according to item 1 of the scope of patent application, wherein the first dielectric layer is a tunneling oxide layer. 3. The method for manufacturing a self-aligned floating gate as described in item 1 of the scope of patent application, wherein the first dielectric layer is made of silicon oxide. 4. The process of self-aligning floating gate as described in item 1 of the scope of patent application Page 13 1222184 VI. Patent Application Method, wherein the second dielectric layer is made of silicon nitride. 5. The method for manufacturing a self-aligned floating gate electrode as described in item 1 of the scope of patent application, wherein the material of the first gap wall is silicon oxide. 6. The method for manufacturing a self-aligned floating gate as described in item 1 of the scope of patent application, wherein the material of the second gap wall is silicon oxide formed at a high temperature. 7. The method for manufacturing a self-aligned floating gate as described in item 1 of the scope of patent application, wherein the material of the second gap wall is silicon. 8. The method for manufacturing a self-aligned floating gate as described in item 1 of the scope of patent application, wherein the material of the substrate is silicon. 9. The method for manufacturing a self-aligned floating gate as described in item 1 of the scope of patent application, wherein the material of the first conductor layer is silicon. 10. The method for manufacturing a self-aligned floating gate as described in item 1 of the scope of patent application, wherein the step of forming the first spacer comprises at least: forming a silicon oxide layer to cover the second dielectric layer, The side wall of the first opening and an exposed part of the first conductor layer; a part of the formed silicon oxide layer is removed by etch-back, and only the part of the side wall of the first opening is left Part of the silicon oxide layer to form the first spacer. Page 14 1222184 VI. Scope of patent application 11. The process for self-aligned floating gate described in item 1 of the scope of patent application, wherein the second etching is isotropic dry etching. 1 2. The method for manufacturing a self-aligned floating gate electrode as described in item 1 of the scope of patent application, wherein the step of forming the second spacer comprises at least: forming an oxide layer of approximately the same thickness to cover the second dielectric Layer, the first spacer, the side wall of the second opening, and an exposed portion of the first dielectric layer; a portion of the oxide layer formed is removed by etch-back, leaving only || A portion of the oxide layer covering the first gap wall and a side wall of the second opening forms the second gap wall. 1 3. The method for manufacturing a self-aligned floating gate according to item 1 of the scope of patent application, wherein the material of the second conductor layer is silicon. 1 4. The method for manufacturing a self-aligned floating gate electrode as described in item 1 of the scope of patent application, wherein the second conductive layer is planarized by using a chemical mechanical polishing method. The method for manufacturing a self-aligned floating gate electrode according to the item, wherein the first etching is performed by using the first spacer and the second dielectric layer as a mask. Page 15 looks like 184 " 'The two-pole gate of the gap range system for patent application should be placed and floated, the wall of the quasi-wall gap is the same material16, as described in item 1 of the scope of patent application. Fang to 'wherein the first dielectric layer and the first back-sin' are one of them. „17 _ • A floating gate structure of flash memory, including at least a source region! T a substrate surface, A first dielectric layer is located on the substrate and the two-knife source region is exposed. A floating gate is located on the first dielectric layer and partially overlaps the first and second regions. A second The dielectric layer covers a part of the floating gate. On one side, the gap wall is located on the side wall of the second dielectric layer and is located on the floating gate. The dielectric lies in that the floating gate is opposite to the first gate. A gap wall and the first and second sides are recessed—the second gap wall is located on the first dielectric wall covering the first dielectric layer and fills the side recess. The floating gate structure according to item 17, wherein the second dielectric layer is a tunneling oxide layer. 17 ^ ^ £ m ^ m ^ ^ ^ ^ only nitride nitride. U. Patent Park range of the floating first electrode structure 7 is set off, wherein the second - the spacer material is oxidized stone evening. Page 16 1222184 VI. Scope of patent application 2 2. The floating gate structure as described in item 17 of the scope of patent application, wherein the material of the second gap wall is silicon oxide formed at high temperature. 2 3. The floating gate structure according to item 17 of the scope of patent application, wherein the material of the second gap wall is silicon. 2 4. The floating gate structure according to item 17 of the scope of patent application, wherein the material of the substrate is silicon. 〇 2 5. The floating gate structure described in item 17 of the scope of patent application, wherein the material of the floating gate is Shi Xi. 2 6. The floating gate structure according to item 17 of the scope of the patent application, wherein the first dielectric layer, the first spacer, and the second spacer are made of the same material. Page 17