TWI222163B - Re-performed spin on process - Google Patents

Abstract

A spin on process able to be re-performed is provided, which comprises first performing a spin on process so as to form a first dielectric layer on a surface of a semiconductor wafer. An examining step of the first dielectric layer is then performed, and the first dielectric layer conforms to a predetermined condition. An etching process is performed so as to completely remove the first dielectric layer. Finally, the semiconductor wafer is baked, and the spin on process is re-performed so as to form a second dielectric layer on the surface of the semiconductor wafer.

Description

1222163

FIELD OF THE INVENTION The present invention provides a spin-coating method to avoid spin-coating and avoid repetitive spin-coating of the main body wafer. + Previous technical purpose = widely used in very large scaie mte circuits. ^ atwn (VLSI) multiple metallization process (inuiuievei metallization process) uses multiple layers of metal interconnects and low dielectric constant materials to serially connect each semiconductor element on a semiconductor wafer to form a stacked circuit architecture Therefore, in order to deposit a dielectric layer with good step coverage and no holes on the surface of the metal interconnects, the current VLSI manufacturing process mostly forms a sandwich type dielectric structure to solve this problem. Please refer to FIGS. 1 to 4, which are schematic diagrams of a process for forming a sandwich-type dielectric structure 22 on the surface of a conventional semiconductor wafer. As shown in FIG. 1, the semiconductor wafer 10 includes a stone substrate 12, a plurality of metal interconnects 14, and a plasma enhanced chemical vapor deposition (Plasma)

enhanced chemical vapor deposition (PECVD) process) A spin on process is performed to form a spin-on-glass (S0G) layer 18 on the surface of the semiconductor wafer 10, and the S0G layer 18 is

Page 5 1222163 V. Description of the invention (2)

Fill the trench 17 between the silicon dioxide layers 丨 6. As shown in FIG. 3, after the curing process of the SOG layer 18 is completed, an etching back process is then performed to uniformly remove a portion 50 (; layer 18) to reduce the thickness of the SOG layer 18. Finally, as shown in Figure 4, a pECVD process is used to deposit a silicon dioxide layer 20 on the surface of the SOG layer 28 to complete the fabrication of the sandwich-type dielectric structure 22. As the line width of the process shrinks, The width of the connection line 1 4 is also getting thinner and thinner, but in order to avoid the resistance value rising, the thickness of the metal interconnection line 4 cannot be relatively reduced accordingly, resulting in the metal interconnection line 1 4 having a larger south. The aspect ratio creates a severe topography. Therefore, when the SOG layer 18 is deposited on the surface of the semiconductor wafer using a spin coating process, uneven thickness problems tend to occur. In addition, the spin coating process After completion, an edge bevel rinse (EBR) process is usually performed to clean the edges of the semiconductor wafer 10, and the edge beve 1 rinse (EBR) process may cause S 0 G layers. 1 8 Surface contaminated by chemical solution However, in the conventional semiconductor manufacturing process, if the S 0 G layer 18 of the semiconductor wafer 10 has the above-mentioned poor thickness uniformity (thickness uniformity) or the surface is contaminated by chemical solutions, it will be The semiconductor wafer 10 is directly scrapped, resulting in a waste of production resources and an increase in manufacturing costs.

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V. Description of the invention (3) The main object of the present invention is to provide a spin coating process that can be repeatedly performed to solve the problems of the conventional techniques described above. The invention provides a repeatable spin coating process and a repeatable spin coating process. The steps include first performing a spin coating process to form a first dielectric layer on a semiconductor wafer surface, and then A detection step is performed on the first dielectric layer, and the first dielectric layer meets a predetermined condition, and then an etching process is performed to completely remove the first dielectric layer, and a wet brushing device (wet scrubber), cleaning the semiconductor wafer, finally drying the semiconductor wafer and performing a spin coating process again to form a second dielectric layer on the surface of the semiconductor wafer. The present invention provides a repeatable spin coating process. When a dielectric coating formed on the surface of a semiconductor wafer by a spin coating process has problems such as poor thickness uniformity or a surface contaminated with a chemical solution, the present invention The dielectric layer is removed by a wet etching process or a dry etching process, and then the remaining solution or particles (part 丨 C 1 e) remaining on the surface of the semiconductor wafer are cleaned by deionized water, and finally the The semiconductor wafer is dried and the spin coating process is performed again to re-shape the dielectric layer f. Compared with the conventional method, the present invention can avoid half! Rabbit shame- [by—see the spin coating process failed and was scrapped. In addition, the spin coating process repeated in the present invention will not cause the yield of the semiconductor wafer to decrease ', so it can be effectively applied to the manufacturing of semiconductor components.

Page 7 1222163 V. Description of Invention (4) Manufacturing. Embodiments Please refer to FIG. 5 to FIG. 7, which are schematic diagrams of the repeatable spin coating process of the present invention. As shown in FIG. 5, in the first embodiment of the present invention, the semiconductor wafer 50 includes a silicon substrate 52 and a plurality of metal interconnections 54, and then performs a spin on process to A first dielectric layer 56 is formed on the surface of the semiconductor wafer 50 to directly cover the metal interconnects 54. The first dielectric layer 56 is made of spin on glass (SOG) or HSQ (hydrogen silsesquioxane) ( k = 2.8) > Low dielectric constant materials such as MSQ (methyl silsesquioxane) (k = 2.7). Subsequently, a film thickness test and a cleanness test are performed on the first dielectric layer 56. When the thickness uniformity of the first dielectric layer 56 is poor, or the surface of the first dielectric layer 56 is cleaned due to crystal edges (edge bevel rinse, EBR) process is contaminated by chemical solution or particles are attached, which leads to the failure of the spin coating process. A preferred method of the present invention will completely remove the first step by using a dry etching process. Dielectric layer 56, and the dry etching process uses dichlorodi f luoromethane (CCL2F), Perfluoromethane (CF4), hexafluoroethane (perf, u 〇 〇 ^ C2F6), and Carbonization of fluorine gas such as perfluoropropane (C3F8)

Page 81222163 V. Description of the invention (5) After etching the first dielectric layer 56 as an etching gas 3η, the material conductor crystal J = in a fishing scrubbing device (wet scrubbed to use removal = water, Particles remaining on the surface are then dried using a heating pad (heating Pla / e) device to dry the semiconductor wafer 50. Finally, a second, transfer coating process is performed to re-form a first on the surface of the semiconductor wafer 50. " The electrical layer 58 covers each metal interconnect 54. Similarly, 58 is also made of low dielectric constant materials such as SOG or HSQ, MSQ. In addition, the thickness of the first dielectric layer 58 is uniform. The performance is still not good, or the surface of the first " electric layer 5 8 is contaminated by chemical solution again, the method of the present invention can still repeat the above steps until a good thickness uniformity is formed on the surface of the semiconductor wafer 50 by the spin coating process. The dielectric layer is used to form a conventional sandwich-type dielectric structure for the benefit. The present invention can also be implemented in the process of a composite dielectric layer structure. Please refer to FIG. 8. In the second embodiment of the present invention, Semiconductor wafer 100 It includes a silicon substrate 102, a plurality of metal interconnects 104, and a silicon dioxide formed on the surface of a semiconductor wafer 100 using a plaSma enhanced chemical vapor deposition (PECVD) process. Layer 1 06. Subsequently, the semiconductor wafer 100 was spun using a spin coating process! Service _ cleanliness testing, when the first dielectric layer 10 8 meets a poor thickness uniformity or the surface contains chemical solution pollution, etc. When the conditions are predetermined,

1222163

V. Description of the Invention (6) A preferred method is to use a wet etching process to completely remove 108, and the wet etching process uses a low dielectric constant material including a first dielectric layer 108 and a low dielectric constant material. The silicon oxide of the silicon dioxide layer i 〇6 has a high selectivity component, such as hydrofluoric acid (hydrolofluc acid, Hn or buffered hydrofluoric acid (BHF, HF / NHJVH)), as the etching solution. The silicon dioxide layer 106 is used as a barrier layer (barrier laye, r) to protect a plurality of metal interconnects i 04 and other components on the surface of the silicon substrate 102, and it is free from removing the first dielectric layer. Damaged during the wet etching process of 1.08. It is worth noting that when the first dielectric layer 108 is composed of a spin-on glass material, if a buffered hydrofluoric acid is used as the etching solution, the The spin-on glass material's remaining engraving rate (4500A / min) is much higher than the engraving rate of stone dioxide (60A / mi η), so a good removal effect can be obtained. Next, as shown in FIG. The steps of the first embodiment of the invention, and then placing the semiconductor wafer 100 In a wet scrubber, the particles and the etching solution remaining on the surface are cleaned with deionized water, and the semiconductor wafer 100 is dried using a heating pad device. Finally, as shown in FIG. 10, the process is performed again. A spin-coating process' to re-form a second dielectric layer on the surface of the semiconductor wafer 1000. Similarly, the second dielectric layer 110 is also composed of a low dielectric constant material such as SOG or HSQ, MSQ. In addition, Assume that the thickness of the second dielectric layer 1 1 0 is still poor, or that the surface of the second dielectric layer 1 10 is subject to chemical attack again— 一 _ ..- — — — — — — — — — — — — —.... — _ __ ....., ..- ·, liquid contamination, the method of the present invention can repeat the above steps until a thickness uniformity is formed on the surface of the semiconductor wafer 100 by a spin coating process. good

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A composite dielectric structure or a good dielectric layer is used to facilitate the subsequent formation of a conventional sandwich-type dielectric structure. ， 本 明 ^ The spin coating process that can be repeated is not limited to shape. / Composite or two Meiji type dielectric structures, any semiconductor structure formed by a spin coating process, such as a shallow trench isolation structure, are the scope of the present invention. x The present invention provides a repeatable spin coating process, a repeatable spin coating process, the steps of which include first performing a spin coating process to form a first dielectric layer on a semiconductor wafer surface, and then A detection step is performed on the first dielectric layer, and the first dielectric layer meets a predetermined condition, and then an etching process is performed to completely remove the first dielectric layer, and a wet brushing device (wet scrubber), cleaning the semiconductor wafer, finally drying the semiconductor wafer and performing a spin coating process again to form a second dielectric layer on the surface of the semiconductor wafer. The above are only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

1222163 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 are schematic diagrams of the process of forming a sandwich-type dielectric structure on the surface of a conventional semiconductor wafer. Figures 5 to 7 are schematic diagrams of a repeatable spin coating process according to the first embodiment of the present invention. Figures 8 to 10 are schematic diagrams of repeatable spin coating process according to the second embodiment of the present invention. Semiconductor wafer 14 Metal interconnect 17 Trench 5 0, 1 0 0 Semiconductor wafer 54, 104 Metal interconnect 58, 1 10 Second dielectric layer 12 Broken substrate 1 6, 2 0 Silicon dioxide layer 18 SOG layer 5 2 1, 10 2 silicon substrate 56, 108 first dielectric layer 106 silicon dioxide layer

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Claims (1)

1222163 VI. Scope of patent application 1 · A repeatable spin coating process includes the following steps: A spin coating process is performed to form a first dielectric layer on the surface of a semiconductor wafer; A first step is performed on the layer, and the first dielectric layer meets a predetermined condition; an etching process is performed to completely remove the first dielectric layer; the semiconductor wafer is cleaned by a wet scrubber; The semiconductor wafer; and performing a spin coating process again to form a second dielectric layer on the surface of the semiconductor wafer; wherein the semiconductor wafer surface is further formed with a plurality of metal layers, and the first dielectric layer covers the Wait for metal interconnects. Deep 'and 2 · As in the process of applying for item No. 丨 in the patent application range, wherein the detection step is thickness detection, and the predetermined condition is that the first dielectric layer has a thickness uniformity. Crossover 3 · The process of item 1 in the scope of patent application, wherein the cleanliness test, and the predetermined condition is that the first medium drawer is contaminated with a chemical solution or particles. Face contains A «_ .j. ...... ---------------------------------------- -------------------------------------------------- ----------- — • The manufacturing process of item 1 in the patent application scope, wherein the second and second dielectric layers are made of a spin-on glass (Spin 〇 ハ Page 13 1222163 料 的 组合。 Material composition. 5. The process of claim 1 in the scope of patent application, wherein the second dielectric layer is made of a low dielectric constant material. "Θ" The 6 · As in the scope of patent application Dry etching process. 7. If the scope of the patent application further includes a barrier layer and the first dielectric layer between the first dielectric layer, the process of the first item, in which the barrier layer is formed, the remaining process is-the surface of the semiconductor wafer is formed In the wire structure and manufacturing process, the barrier layer is formed by vapor deposition (CVD). 8 · For example, a chemical deposition process (chemically formed silicon oxide layer) in item 7 of the scope of the patent application. 9 · For example, in the process of claim 1 of the patent scope, the etching process is a wet etching process. 1 0 The process of the scope of application for patent No. 9 wherein the wet etching process uses buffered hydrofluoric acid (BHF) as the etching solution. Λ1 · A kind of repeatable — ^ _ 簠 ― —— —— ～ ___ ___ : Performing a chemical / product process to form a resistor on the surface of a semiconductor wafer Page 14 1222163 6. Scope of patent application " Separator layer; a spin coating process is performed to form a first electrical layer on the surface of the silicon oxide layer; a detection step is performed on the first dielectric layer, and the first A dielectric layer is in accordance with a predetermined condition; a process is performed to completely remove the first dielectric layer; the semiconductor wafer is cleaned by a wet scrubber; the semiconductor wafer is dried; and a A spin coating process is performed to form a second dielectric layer on the surface of the semiconductor wafer; wherein a plurality of metal interconnects are formed on the surface of the semiconductor wafer, and the silicon oxide layer covers the metal interconnects. 1 2 · According to the process of claim 11 in the scope of patent application, the detection step is film thickness detection, and the predetermined condition is that the first dielectric layer has poor thickness uniformity. 13. The process according to item 11 of the scope of patent application, wherein the detection step is a cleanness test, and the predetermined condition is that the surface of the first dielectric layer contains chemical solution contamination or particle contamination. 14 · If the process of applying for the scope of item 11 of the patent—factory, the second dielectric layer is made of a spin on glass (S0G) Page 15 1222163 VI. Scope of patent application Material composition. 15. The process according to item 11 of the scope of patent application, wherein the first dielectric layer and the second dielectric layer are composed of a low dielectric constant material. 16. The process of item 11 in the scope of patent application, wherein the etching process is a wet #etching process. 1 7. The process according to item 16 of the scope of patent application, wherein the wet etching process uses buffered hydrofluoric acid (BHF) as an etching solution. nm p. 16