TWI221967B - High efficiency redundancy architecture - Google Patents

Abstract

The present invention provides high-efficiency redundancy architecture. The present invention comprises a memory array including a redundancy block, a plurality of R/W buffers connected to the corresponding column in the memory array, a plurality of I/O circuits connected to the corresponding R/W buffers through a plurality of selecting circuits, and a plurality of determined blocks connected to the corresponding I/O circuits. A detective signal determine a defective column through the determined blocks.

Description

[Technical field to which the invention belongs] The present invention relates to a memory block architecture, and in particular θ _ ^, which is related to a redundancy architecture of a delta memory block. [Previous technology] As far as the current integrated circuit is concerned, with millions or even more, the yield control of the process is extremely flawed or a defect during manufacturing. It is eliminated. With such a high accumulation level and dense and defect-free requirements, there is currently a process to solve the problem of component defects as an additional backup component to replace the component technology, which can greatly increase production. The main application of this technology is in the design of memory chips. Single and two integrated circuit chips can contain components. At such a high level of integration, it is an important consideration. Any component on the chip will cause chip function. Damage, which will increase the cost of production of the product. However, it is difficult to achieve complete practicality under the arranged elements. One of the methods is to make defective components on the chip. By applying the yield of the backup product, it is widely used. The component process of the memory will be outside the original memory array. Redundancy memory cells (memory ce 1 1) of rows and columns are added, and after the process is completed, a functional test of the memory elements is performed during the chip test to detect defective elements. Defective memory cell is detected in a memory element. At this time, the defective memory cell can be replaced by a backup memory cell by changing the current path.

92109806 V. Description of Invention (2)

Year, month, and year _ There are two types of backup architectures for the modified cell. The first figure shows a schematic diagram of an array with a backup architecture, including the left memory cell array 100 and the right memory cell, and multiple round-in / out (I / 〇) Control circuit 1 08 is a circuit that uses the δ self-memory cell in I to perform read and write control. The read / write (R / W) buffer 1 06 is used as an input / output buffer for reading and writing data. The (I / 〇) control circuit corresponds to a line position. In this kind of memory backup architecture, a backup memory cell 1 0 will be constructed in each of them. In other words, if the memory cell in one of the row positions is damaged, the memory cell 1 can be backed up. 4 to replace, but in this architecture, a backup memory cell 104 is required for each location, which not only increases the manufacturing to increase the memory volume. Traditional memory memory cell array 102 is used for several readouts, and each memory cell array row position is based on each adjacent textbook. Another schematic diagram of the architecture of another memory cell array. 7 The biggest difference between this architecture and the first one is that all backup areas = 110 ## are established on the far right of the left array 100, in other words, Under this rack, if the memory cell in one row position is damaged, it will be replaced by a row memory cell in the backup block. When reading or writing this row position, the input / output (1 / 0) The control circuit 108 will bypass this damaged = memory cell and jump to the memory cell in the backup block η 〇 for access. However, in this architecture, the backup memory cell 110 is located in a fixed position, that is, no matter which memory cell is damaged, the memory cell in the backup block needs to be replaced by it. When the memory cell π 0 corresponding to the input / output (J / 0) control circuit 1 0 8 is damaged, it is necessary to access the backup block 11 0 through different path lengths. Such access through different path lengths will cause Read and write speeds are different.

The year ° is E No. 92109098. The year and month are amended. V. Description of the invention (3) [Summary of the invention] The main purpose of the present invention is to provide a highly efficient memory block backup architecture and method. To avoid reading and writing paths of different lengths. Another object of the present invention is to provide a highly efficient memory block backup architecture and method. Memory cells at each row address can be used as backup blocks of adjacent rows to avoid reading and writing of different lengths. Into the path. Another object of the present invention is to provide a high-efficiency memory block backup structure and method, which does not require a backup block to be constructed on each row, thereby reducing the memory volume. According to the above object, the high-efficiency memory block backup architecture of the present invention includes at least a memory cell array, where the memory cell array includes a backup block, a plurality of read / write (R / W) buffers, and is coupled to One row of memory cells, a plurality of input / output (I / 〇) control circuits, are coupled to corresponding read / write (R / W) buffers via a plurality of selection circuits. A plurality of judgment blocks are coupled to corresponding control circuits. When a corresponding memory cell is damaged, a detection signal is used to judge based on the judgment blocks. On the other hand, when the detection signal determines that a certain row of memory cells is damaged, a control signal is generated to adjust the selection circuit so that the input / output (I / 〇) control circuit and read / write (R / W) A new access path is created between the buffers. Due to the structure of the present invention, the memory cells at the address of each row can be used as a backup block of adjacent rows, so that reads and records of different lengths can be avoided.

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No. 92109806 needs to correct the entry path. In addition, the structure of the present invention does not require that a backup block be constructed on each row of addresses, thereby reducing the memory volume. Embodiment] Without limiting the spirit and application scope of the present invention, the following describes the implementation of the present invention with an implementation; those skilled in the art will be able to apply the memory area of the present invention after understanding the spirit of the present invention. The block structure is in various memories. With the structure of the present invention, the memory cell j at the address of each row can be used as a backup block of the adjacent row, so it is possible to avoid the generation and writing paths of different degrees. Moreover, the structure of the present invention does not require that a backup block be constructed at each row position ϋ λ, so the memory volume can be reduced. The application of the present invention is not limited to the preferred embodiments described below. A reference Sho credit% r · ^ Y ... drink, two brother diagram that illustrates an embodiment of the present invention in accordance with a preferred high ^^ backup memory block schematic diagram of architecture. The architecture includes a left memory cell array 3 0 0 and a right memory cell array 3 0 2. A plurality of input / output (丨 / 〇) control loops 3 0 R is used to make a selection on the selected memory cell. Read and write operations

The electric strategy 'a plurality of read / write (R / W) buffers 306 are used for reading and reading of the magong material I, and each input / output (I / O) control circuit is 0 U 8 For the location of a memory cell array in the identity architecture, respectively. On the right side of this kind of memory device, the 'injury memory cell 3 1 0 is constructed at the top of the left memory cell array 3 0. The biggest difference between the present invention and the traditional architecture is that each row of the address is recorded as I ^ Both can be used as backup blocks for adjacent rows. In other words, when the left hidden cell block 322 is

^ 丨 Heart and fat ρ early 歹 | J 1 η--υ 0 When the memory cell block 3 2 0 is damaged, the adjacent record can be used as a backup block of the memory cell block 3 2 0. similar

1 pass, 1 music%, page change, and the correction is more similar to Ι Υψ92109806 " ΐΤΙ · Ming said a month (5) of the "memory cell block in the right memory cell array 302 seems to occur adjacent memory cell area Tugui 326 It can be used as a backup block of the memory cell block. Therefore, if the memory block backup architecture of the present invention is used, it will not generate the read and write paths of different lengths, and each memory line address Each of them builds an additional backup block. To achieve the above-mentioned use of memory cells on adjacent row addresses as blocks of adjacent rows, the present invention uses a plurality of selection circuits to construct an access path. This selection circuit can be formed by multiple U 312, each of which The read / write I / R / W) buffer 306 can be read or written by two adjacent input / output (I / O) control circuits 308 via the multiplexers 312. A plurality of judgment blocks, which can be formed by fuse blocks 314, are respectively connected with corresponding input / output (I / O) control circuits 308, and the main purpose is that when a cell block is damaged, its The corresponding fuse block 314 will be blown. Suppose that when a memory cell block is damaged, its corresponding fuse block 3 丨 4 is blown out. 'When performing a memory block detection, a plurality of i0hit ^ will be sent to the plurality of fuse blocks. At this time, the corresponding number of the blown fuse will change from " to " i ". This iohi t signal will be combined with the 7-address' fuse block = Ning, so that the corresponding signal neihit will also follow. Becomes' and from the damaged memory cell block to the backup memory cell between 3 and 10. The ne ihit signal corresponding to the hidden block ^ will be transformed into "1" and control the multiplex mode 3 1 2 to change the transmission path. On the other hand, the untransformed ne 1 h 11 signal, that is, It is still a signal of "o" and does not change the transmission path of the original multiplexer 3 1 2. Take the memory cell block 324 in the right redundant memory cell array 302 as an example. First, the corresponding lyocell block 3 丨 4 will be cut off. At this time, the lysate 961 is cut off. Gong Yue _ No. 92109806 Amended on March 5, V. Invention Description (6) The i oh it signal corresponding to the silk will be transformed into " 1 ", and combined with the reden signal sent from the silk refining block 3 15 at the y address, and As a result, the corresponding signal nei hi t also becomes π 1π, and at the same time, the ne ihit signals corresponding to all the memory cell blocks between the memory cell block 324 to the backup memory cell 3 10 are also transformed into " 1 ". At this time for ne As for the memory cell block whose ihit signal is π 1 ", this ne ih 丨 seven signal will control the transmission direction of the corresponding multiplexer 3 1 2. For example, when writing, it will start from the corresponding input / output ( I / 〇) control circuit writes the read / write (R / W) buffer adjacent to the left side via the multiplexer 3 1 2. In other words, when writing to the memory cell block 3 2 4 Because the ne ihit signal corresponding to the memory cell block 3 2 4 is "1" at this time, the memory cell block 3 2 4 was originally The corresponding input / output (I / O) control circuit 308a writes the read / write (R / w) buffer 306a via the multiplexer 312. On the other hand, when data is read, it will be transmitted to the corresponding input / output control circuit through the multiplexer 3 1 2 via the read / write (r / W) buffer area adjacent to the left side. That is, it is re-sent from the read / write (r / W) buffer 3〇6a through the multiplexer 3 1 2 to the original corresponding input / output (I / 〇) control circuit 3 0 8a 〇 Each read / write (R / W) buffer area 3 0 6 can be read or written by two adjacent input / output (I / 〇) control circuits 3 0 8 through multiplexing 3 1 2. Therefore, the multiplexer 3 1 2 can be controlled by the neihit signal, and the input / output (I / 〇) control circuit 3 0 8 can skip the read / write (R / W) corresponding to the damaged memory address. Buffer 306 for access. Similarly, if the memory cell block 3 2 0 in the left memory cell array 3 0 0 is damaged, 'the corresponding fused silk block 3 1 4 will be cut off. At this time, the cut corresponding to the fused silk block will be cut off. The i 〇hit signal will be changed to "1" and dissolved with the y address

Page 11 1221967. 1 Zheng ·· page change ~-^ 3 i ^ t ^ 92109806 Correct the Λη (7) The reden signal sent by the silk block 31 5 is combined, so that the corresponding signal neihil also becomes ,, 1 n, ^ x The ne ihit signals corresponding to all the C memory cell blocks from 3 2 0 to the backup memory cell 3 2 0 are also transformed into " 1. This 1 h 11 signal will control the corresponding multiplexer. 3 丨 2 transmission direction, so when the memory cell block 32 is written, the original input / output (I / O) control circuit 3008b corresponding to the memory cell block 32 will pass through the multiplexer 312. Write to read / write (R / W) buffer 306b. On the other hand, when reading data, that is, sell / write (r / w) buffer 306b from 5, via multiplexer 312 Resend to the original corresponding input / output (1/0) control circuit 3008b. In other words, according to the above-mentioned preferred embodiment, the memory of the present invention includes a left memory cell array 300, a right memory When the cell array 302 and a backup cell ^ block are damaged, the memory blocks at all addresses from the damaged memory cell block to the backup memory cell block 310 are input / output. (^ ⑴ The control circuit will access the memory cell area of the memory cell area 302 of the adjacent address on the right side of it. The memory cell block at a certain row address will cause a bad memory cell. From the block to the backup memory cell block 31, all the memory blocks on Γί, its input / input (1/0) circuit B will store = the memory cell block on its left adjacent address. However The storage of the above input / output (I / 0) control circuit when the memory block is damaged can be returned according to the location of the backup memory cell block 3 1 0 ^ " It can be known from the above preferred embodiment of the present invention Apply the advantages of this issue, because the memory cells on each row of addresses can have the next block, so it can avoid generating different lengths of the first phase and the fourth phase. The structure of the present invention is not required in each line Bit path.

A _ _; _ is required to build a backup area 967, page 1 (): _ No. 92109806, month, month, day, month, month, month, month, month, month, month, month, month, month, and month Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

Page 13 im% 7u.g "B. ¾ Beb year b: month" No. 92109806_ year month month correction ^ m ^ WWnm * [Schematic description] In order to make the above and other objects, features, The advantages and advantages can be more obvious and easy to understand. The following is a detailed description of a preferred embodiment and the accompanying drawings: Figure 1 shows a schematic diagram of a traditional memory cell array with a backup architecture. Figure 2 Shown is a schematic diagram of another conventional memory cell array with a backup architecture.

FIG. 3 is a schematic diagram of a memory cell array with a backup architecture according to a preferred embodiment of the present invention. [Simple description of component representative symbols] 1 0 0 and 3 0 0 left memory cell array 1 0 2 and 3 0 2 right memory cell array 1 0 4, 1 1 0 and 3 1 0 backup memory cells 106, 3 0 6a, 3 0 6b and 3 0 6 read / write (R / W) buffers 108, 3 0 8a, 3 0 8b and 3 0 8 input / output (I / O) control circuits 3 1 2 multiplexer

3 2 0, 3 2 2, 3 2 4 and 3 2 6 memory cell blocks

Page 14

Claims (1)

1221967… ^ Case No. 92109806_Year Month Amendment_ i 六 丨 Application for Profit 1¾ 1. A high-efficiency memory block backup architecture, which includes at least: a memory cell array composed of a plurality of rows of memory cells, the The memory cell array includes a backup memory cell block; a plurality of read / write buffers respectively coupled to the corresponding row of memory cells; a plurality of selection circuits respectively coupled to the corresponding read / write buffers Zone 1 a plurality of input / output control circuits are respectively coupled to the corresponding selection circuits; and a plurality of judgment blocks are respectively coupled to the corresponding input / output control circuits. 2. The high-efficiency memory block backup architecture described in item 1 of the scope of patent application, wherein the selection circuit is formed by a multiplexer. 3. The high-efficiency memory block backup architecture described in item 1 of the scope of patent application, wherein the judgment block is formed by a fuse. 4. The high-efficiency memory block backup architecture described in item 1 of the scope of patent application, wherein the selection circuit can be controlled by a control signal to change the transmission path. 5. The high-efficiency memory block backup structure as described in item 1 of the scope of patent application, wherein the judgment block will show the first when the corresponding memory cell is damaged. On page 15, Xiu said 92109806_year, month, month, month, month, month, month, month, month, month, month, month, month, month. 6. The high-efficiency memory block backup architecture as described in item 4 of the scope of patent application, wherein when the judgment block shows the first condition, a control signal is generated to change the transmission path of the corresponding selected circuit. 7. The high-efficiency memory block backup architecture described in item 1 of the scope of the patent application, wherein any one of the input / output control circuits can be coupled to two adjacent read / write buffers via corresponding selection circuits. 8. The high-efficiency memory block backup architecture described in item 1 of the scope of the patent application, when any one of the rows of memory cells is damaged, a plurality of selection circuits corresponding to the damaged row of memory cells to the backup block will Change the transmission path. 9. An access method for a high-efficiency memory block backup architecture, wherein the backup architecture includes at least a memory cell array composed of a plurality of rows of memory cells, and the memory cell array includes a backup memory cell block, a plurality of The read / write buffer, a plurality of selection circuits, a plurality of input / output control circuits, and a plurality of judgment blocks. The method includes at least: Detecting whether the plurality of judgment blocks show the first situation, wherein the judgment blocks will show the first situation when the relative row memory cell is damaged; and changing the corresponding correspondence between the damaged row memory cell to the backup block The transmission paths of the plurality of selection circuits. Page 16 ·· :: 1221967: Ί 10 case number 92109806 amended the fT application scope 刼 10. Access to the high-efficiency memory block backup architecture as described in item 9 of the scope of patent application Method, wherein the selection circuit is formed by a multiplexer. 1 1. The access method of the high-efficiency memory block backup architecture as described in item 9 of the scope of patent application, wherein the judgment block is formed by a fuse. 12. The access method of the high-efficiency memory block backup architecture described in item 9 of the scope of the patent application, wherein the plurality of read / write buffers are respectively coupled to corresponding rows of memory cells. 13. The access method of the high-efficiency memory block backup architecture as described in item 9 of the scope of the patent application, wherein the plurality of selection circuits are respectively coupled to the corresponding read / write buffers. 14. The access method of the high-efficiency memory block backup architecture according to item 9 of the scope of the patent application, wherein the plurality of input / output control circuits are respectively coupled to the corresponding selection circuits. 15. The access method of the high-efficiency memory block backup architecture as described in item 9 of the scope of the patent application, wherein the plurality of judgment blocks are respectively coupled to the corresponding input / output control circuits. 16. The access method of the high-efficiency memory block backup architecture described in item 9 of the scope of patent application, wherein any one of the input / output control circuits Page 17 1221967, ... i, ... ', I ", ~~ p ..., ~! ^ It No. 92109806 _η Amendment VI, apply for the 17th model. The corresponding selection circuit is coupled to two adjacent read / Write buffer 17. The method for accessing the high-efficiency memory block as described in item 9 of the scope of the patent application, when any one of the rows of memory cells is damaged, the number of relatively bad rows of memory cells to the backup block is plural. A selection circuit will route. Backup architecture should be changed at this loss