TWI221960B - Test method of command cache memory - Google Patents

Abstract

A test method of command cache memory directly writes executable machine code into the memory to generate test functions. Therefore, while testing, the code quantity of the machine code is variable and controllable. The method comprises the following steps: first allocating a segment of memory space and then writing the executable machine code into the memory space; next treating the executable machine code as test functions to execute the test; evaluating the execution results and finally releasing the memory space.

Description

1221960 V. Description of the Invention (1) [Technical Field of the Invention] The present invention is a test method for instruction cache memory, and particularly a method for generating a test function by directly writing executable machine code into the memory, so that Testing method of variable code and controlled instruction cache memory of machine during test. [Prior art]

Cache is an indispensable part of the current central processing unit (CPU), because the processing speed of memory in computer systems is much lower than that of CPU. In order to compensate for the speed difference between the two, Cache must be added to the CPU. The basis for adding the C a c h e function is based on the principle of locality, that is, the program's address access stream has a strong timing correlation, and the next memory unit to be accessed by the CPU is mostly near the address of the last access.

The cache function mainly includes reading and writing by the media, which is completely completed by hardware. Generally, the CPU's access to the memory is divided into two types, one is to obtain the next instruction (machine code), and the other is to obtain data. Cache points in the CPU? Two levels, in the first level cache, are divided into instruction cache (Data Cache) and data cache (Data C a c h), respectively corresponding to the above two needs. When you do not get the content you want in the first level C a c h e (referred to as no hit), it will look in the second level cache. The secondary cache usually does not distinguish between Code and Data. If it still misses, it actually looks in the memory. For virtual memory systems, it is also possible to end up looking on magnetic disks. The CPU is generally tested by hardware-based cache when it leaves the factory, but

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1221960 V. Description of the invention (3) The code cannot be completely controlled. At this time, a method for testing the instruction cache memory with a variable amount of machine code and a controlled method for testing the above problems is needed. [Summary of the Invention] In view of this, the present invention proposes a test method of instruction cache memory to solve the above problem. The test function is generated by directly writing executable machine code into the memory to make the machine code Variable and controlled code makes test results more reliable.

The present invention provides a method for testing instruction cache and memory. The method includes the following steps: first allocate a memory space for the test, then write executable machine code into the memory space, and then save the memory The execution machine code is used as a test function to execute the test. Next, the execution result of the test function is verified, and the memory space is finally released.

Compared with the existing methods, the method provided by the present invention generates test functions by directly writing executable machine code into the memory, so that the code amount of the machine code is variable and controlled during the test, which avoids testing The difference in test results caused by different hardware and software environments also solves the problems that the amount of test machine code cannot be flexibly changed and the test process is not controlled. This can better simulate the actual operating environment and improve the test performance. Efficiency and quality ° The detailed content and method of the present invention are described below with reference to the drawings: [Embodiment] The present invention will be described in detail with reference to the drawings:

Page 6 1221960 V. Explanation of the invention (4) — ▲ Through “picture 1”, this figure is the overall flow chart of the test method of the memory of the present invention, which is explained as follows: s π, first is the test Allocate a piece of memory space (step 丨 1 iron; Ϊ Ϊ memory f write executable machine code (step 1 2 °) ;: use: bar code as a test function to perform the test: 2 down 'verify The execution result of the test function (step 14:13., Release the memory space (step 150) .-), take the test version of τ sleeve book! 明 Ming directly to the memory card Write; the amount can be controlled; the test function is-dynamic function:! &Quot; type allocation-segment memory space; then directly write: Ke: in the code for self-modification test (⑽Self_M〇di = 如 钱 器"Benefit code code" or machine code of other instruction cache memory ng); = = machine code is used as a test function to perform test generation ^ ^, when the machine code is written to the memory of the 5th memory, the library : = Root, test requirements are changed ... enclosed; :: test function 5 two kinds :, will be generated in fixed mode With fixed size and random I5, the random sophomore will be generated in machine mode. The register to be rewritten by function 2 can also be different at the same time according to requirements. For the same or after the test, the test results need to be performed. Which is through

1221960 V. Description of the invention (5) Check whether the content in the temporary register is correct to determine whether the cache is working normally. The process of the present invention is further described below. Please refer to "Figure 2", which is a flowchart of writing executable machine code into the memory space according to the present invention, which is explained as follows: First write the protection site and register initialization machine code (step 2 1 0); then repeatedly write the test function main machine code (step 2 2 0); then write the machine code that stores the register value in the stack (step 2 3 0); write the recovery field machine code (step 2 4 0 ); Finally write the return instruction (step 2 5 0). The initialization machine code of this test function contains a stack push instruction, which is used to protect the scene and push the contents of the current register onto the stack. The number of times the test machine code is repeatedly written in the memory space is related to the requirement for the length of the test machine code. When the machine code is required to be longer, the number of writes and executions is correspondingly larger, and vice versa. If the test machine code is a fixed-length code, the number of times is constant; if the length of the test machine code is randomly changed, the number of times is also continuously changed randomly. After that, write a piece of machine code that keeps the register values after the function execution is completed in the stack, so that they can be stored in the specified memory in the future, and then verified. Finally, write a piece to restore the registers before the test function is executed. The value is returned to the machine and the instruction is restored, and the function is exited. Please refer to "Figure 3", which is a flowchart of executing the test using the executable machine code as a test function according to the present invention, which is described as follows:

1221960 V. Description of the invention (6) First push the specified memory address on the stack (step 3 1 0); then execute this machine code to complete the execution of the test function (step 3 2 0); finally, pop the register value out of the stack. Store in the specified memory (step 3 3 0). Steps 3 0 and 3 3 0 are to store the value in the register at the end of the function execution into memory. First push the specified memory address into the stack. After the execution of step 3 2 0, the value in the register has been saved in the machine due to the execution of step 2 3 0. In the last step 3 3 0, the value of the register in the stack is saved. The value is stored in the specified memory.

Please refer to "Figure 4", which is a flowchart of releasing the memory space in the present invention, which is explained as follows: If the test has not been completed, return to the step of allocating a memory space for the test, and continue to perform other Steps to test the function (step 4 1 0); If the test is all completed, then end the step of the test (step 4 2 0). When a test is completed, the test function will confirm the test situation. When all tests have been completed, the test will end; otherwise, a section of memory space will be allocated for the tests that have not yet been performed, and the test will continue until Testing is complete. The following uses a preferred example to illustrate the process of the present invention.

The methods for testing the instruction cache memory usually include code re-setting test (C o de R e ρ 1 acement T es 1 :), code self-modifying test (C o de S e 1 f-M odifying T est) and code # , Test test (C ode Sn 〇p Test) and other methods. Let ’s use Code Self-Modifying Tes t? An example is provided to illustrate the process of the present invention. "Please refer to" Figure 5 ", which is the previous example of the present invention

Page 9 1221960 V. Description of the invention (7) The flow chart of performing C ode Se 1 f-M odifying test under the previous technology is explained as follows: Under the prior art, the traditional test method flow is to execute different Code Self- Modifying programs. These programs are executables of different sizes written and compiled in advance. You cannot change the size according to the actual test situation. Real-time generation of executables with different sizes is performed as follows: Execute C ode Se 1 f-Μ 〇difying test program 1 (step 5 1 0); running Code S e 1 f-Μ odifying test program 2 (step 5 2 0); running Code Self-Modifying test program 3 (step 5 3 0). Until all C o d e Se f-M d i f y i n g test program is completed. At the same time, the test program of Code S e 1 f-Μ ifying is relatively close to the main body of the program. When the program runs, the program only needs to jump from the main body to the function to run. The addresses of the two in the memory may be possible. Close enough that the contents of the instruction cache may not be refreshed. Please refer to "Figure 6", which is a flow chart of an example of the present invention using the method of the present invention to perform a Self Modifyin g test, which is described as follows: The method provided by the present invention, its execution process is as follows: First Allocate a piece of memory space for the test (step 6 1 0); then write the code (machine code) of the C ode Se 1 f-M odifying test into the memory (step, step 6 2 0); then execute Co ode Se f-odifying test program (step 6 3 Q); Next, verify the execution result of the test (step 6 4 0); finally release the memory space (step 6 50). Among them, the test program for executing C o d e S e 1 f-Μ o d i f y i n g further includes

Page 10 1. Description of the invention (8) ~~ Ϊ: heavy ΐ ΐ: ΐ machine code for function initialization 'such as pushing the stack number of times, grabbing' 'elf-M〇difying Code machine code, θ stack ：： Determined according to the required length of Dema; then write and store: 丨 the machine benefit code of the incoming letter and the machine code of the recovery site and the return = check-in and other processing. edx, och…, the code is as follows: and nop * dec nop dword ptr Γ. 1 The address of the * instruction e X] 'ebx change * instruction., decrement 1 to increment 丄 eax edit register eax decrement 1 As shown in the above code, the code of the eax register of the empty operation # ^ will be changed from the fourth sentence, the original content is correct, changed, incremented by 1, and finally repeatedly verified by checking the eax register彳 dry = confirm whether the cache function is normal. The above code will be determined by the length of the code when it is required to perform the test. Use other codes ^ ^ ^ Cach_. When testing in different aspects, you can modify the number of iterations to repeat * Μ 0 difyingc 〇de 'It is also possible to measure the overall code length through control.. 'Redirect to ^ = two days guard, 1 allocate memory first, execute in the stack of the system in Heap? Second write two, the machine code to be executed, and then the program jumps to the execution again and returns to the jump position. Execute the following instructions, or release the allocated memory and end the program.

1221960 V. Description of the invention (9) In this way, each jump will go to a different memory location, and the contents of the instruction cache memory will be refreshed, so that the test can be performed more efficiently. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention; that is, all equivalent changes and modifications made in accordance with the patents and scope of this creative application are within the scope of this creative patent. Covered.

Page 1212960 Brief description of the diagram. The first diagram is a test process diagram of the instruction cache memory of the present invention. The second diagram is a flowchart of the code in the memory space provided by the present invention. Figure 4 is a flowchart of testing the executable machine code according to the present invention; Figure 4 is a flowchart of releasing the memory space according to the present invention; Figure 5 is a previous example of the present invention; Flow chart of the Seli-Modifying test under the technology; and the overall flow of the method written into the executable machine as a flow chart between test functions; Execution Code Figure 6 is a flow chart of the Self Modifying test of the example mentioned in the present invention . [Illustration of symbolic symbols] Step 1 1 0 Assign a piece of memory to the test. Step 1 2 0 Write step 1 3 to the memory space. Use the executable machine code as step 1 4 0. Step 1 5 to verify the test function 0 Free up this section of memory step 2 1 0 Write protected field and register step 2 2 0 Repeat write test function main step 2 3 0 Write to save register value in step 2 4 0 Write to restore field machine code step 250 Write return instruction Step 3 1 0 Assign the specified memory address Step 3 2 0 Execute this machine code to use the method of the present invention to execute the body space into the executable machine as a test function result initializer to initialize the machine in the machine code stack Machine code count to execute test machine code push stack into test function execution

Page 13 1221960 Simple illustration of step 3 3 0 step 4 1 0 memory space step 4 2 0 step 5 1 0 step 5 2 0 step 5 3 0 step 6 1 0 step 6 2 0 code (machine step 6 3 0 Step 6 4 0 Step 6 5 0 Remove the register value from the stack and store it in the specified memory. If the test has not been completed, return to the step of assigning a segment to the test and continue executing other test functions. If the test is all completed, end the test execution C. 〇 de S e 1 f-Μ difying test program 1 Run Co ode S e 1 f-Μ odifying test program 2 Run Co ode S e 1 f-Μ odifying test program 3 Allocate a memory space to the test for memory Code written in the body 〇 de S e 1 f-Μ difying test) Run the Code Self-Modifying test program to verify the execution result of the test to free up this memory space

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Claims (1)

1221960 VI. Application Patent Scope 1. A test method for instruction cache memory. The method includes at least the following steps: Allocating a piece of memory space for testing; writing executable machine code into the memory space; The executable machine code is used as a test function to execute the test; verify the execution result of the test function; and free the memory space. 2. The instruction cache test method described in item 1 of the patent application scope, wherein allocating a memory space for the test is allocating a memory space for the test in the system stack. 3. The test cache memory test method described in item 1 of the patent application scope, wherein the executable machine code is a machine code that conforms to the specification of a function and can perform a corresponding functional test. 4. The method for testing instruction cache memory as described in item 1 of the scope of patent application, wherein the step of writing executable machine code into the memory space further includes the following steps: writing the protection site and register initialization machine code Repeatedly write the machine code of the test function body; Write the machine code that stores the register value in the stack; Write recovery field machine code; and write return instruction. 5. The method for testing the instruction cache memory as described in the scope of patent application. Item 4, wherein the initialization machine's code includes a stack push instruction. 6. The test party of the instruction cache memory as described in item 4 of the scope of patent application Page 15 1221960 VI. Patent Application Law, in which the test machine code is repeatedly written into the memory space and the execution is based on the length of the required test machine code to determine the number of repeated writes and execution times. 7. The test method for instruction cache memory as described in item 4 of the scope of patent application, wherein returning to execute other test function instructions is a step of returning the execution verification result of the test function. 8. The method for testing instruction cache memory as described in item 1 of the scope of patent application, wherein the step of executing the test by using the executable machine code as a test function further includes the following steps: pushing the specified memory address on the stack ; Execute this machine code to complete the execution of the test function; and pop the register value out of the stack and store it in the specified memory. 9. The test method for instruction cache memory as described in item 1 of the scope of patent application, wherein verifying the execution result of the test function is to determine the working condition of the cache by verifying the content in the register. 10. The method for testing the instruction cache memory as described in item 1 of the scope of patent application, wherein the step of releasing the memory space further includes a step of allocating a memory space for the test if the test has not been completed , Continue with the steps of other test functions. 1 1. The method for testing the instruction cache memory as described in item 1 of the scope of patent application, wherein the step of releasing the memory space further includes a step of ending the test if the test is all completed. Page 16