TWI221669B - Memory device with vertical transistors and deep trench capacitors and method of fabricating the same - Google Patents

Abstract

A memory device with vertical transistors and deep trench capacitors. This device comprises a substrate containing at least one deep trench and a capacitor deposited in the lower position of the deep trench. A sidewall trench is formed in the sidewall of the deep trench, wherein the sidewall trench intersects the deep trench to form a upper corner and a lower corner. A ring shape insulator is deposited on the sidewall and between the substrate and the conducting wire. A diffusion barrier is deposited on the sidewall of the deep trench on the ring shape insulator and the bottom and the sidewall of the sidewall trench except on the upper corner. A conducting wire is deposited on the capacitor and surrounded by the ring shape insulator and the diffusion barrier. A trench top isolation (TTO) is deposited on the conducting wire. A control gate, comprising a control gate layer and a gate dielectric layer, is deposited on the TTO. A buried strap is deposited within the substrate beside the conducting wire. A doping area is provided within the substrate beside the control gate. A manufacturing method for fabricating such memory device is also disclosed.

Description

1221669

[Technical field to which the invention belongs] The present invention relates to a memory device, and more particularly, to a memory device having a vertical transistor and a trench capacitor and a manufacturing method thereof. [Previous technology] The development technology of integrated circuits is changing rapidly. Its development trend is moving toward powerful functions, reduced size and faster speeds, and the same is true for the manufacturing technology of dynamic random access memory (DRAM), especially the increase of its memory capacity is the most important key. 8 ° ~ Most DRAM cells today consist of a transistor and a capacitor. As the current DRAM memory capacity has reached 256 million bits or even 512 million bits or more, the size of the redundant memory cells and transistors needs to be significantly reduced in the case of increasing component accumulation requirements. DRAM with higher delta memory capacity and faster processing speed is manufactured. However, the δ and δ modes of the traditional flat-panel valley will occupy too much surface area of the wafer and cannot meet the above requirements. Using three-dimensional process technology can greatly reduce the area occupied by transistors and capacitors on the semiconductor substrate. Therefore, three-dimensional technology has begun to be used in DRAM processes, such as vertical transistors and trench crack valleys. Device. Compared with the traditional flat-type transistor, which occupies a relatively large area of the semiconductor surface, it cannot meet the demand for integration of current vision, so it can greatly improve the shortcomings of conventional semiconductor memory cells, which will become the current and future semiconductor memory cells Major trends. However, as transistor sizes shrink, especially below 0 el i # m

1221669 V. Description of the invention (2) The "private, as the diffusion zone overlap of the buried strap (bs) of the transistor (called 65 Merge) also occurs, as shown in Figure} . The buried band 18 is formed by diffusion of the ions in the conductive layer 12 doped with a high concentration of ions in the wire structure 16 in the memory unit to the substrate through the conductive layer 14 doped with low concentration ions or non-doped ions. 10 (referred to as BS out-diffusion). If the diffusion region of the embedded band 18 is too large, it will overlap with the diffusion region of the adjacent trench 8 and cause a short circuit of the semiconductor memory cell. In order to avoid this phenomenon, it is necessary to reduce the ion / centreness in the conductive layer 12 doped with a high concentration of ions in the lead structure 16 of the memory cell or to concentrate the ion-doped region on the conductive layer 12 The center to prevent excessive ions from diffusing into the substrate i0, but this measure will cause the resistance between the conductive layer 12 and the electric valley below it to increase, which is not conducive to the access speed of the memory device. In view of this, in order to solve the above problems, the main object of the present invention is to provide a memory device having a vertical transistor and a trench capacitor and a manufacturing method thereof, which can be applied to a dram process of 0.1 m # or less. [Summary of the Invention] The object of the present invention is to provide a memory device having a vertical transistor and a trough valley device and a method for manufacturing the same, so as to solve the problem of BS Merge of buried regions. The main feature of the present invention is to propose a new structure memory device with a vertical transistor and a trench capacitor, using a diffusion barrier ring

0548-9920TWF (Nl); 91231; Felicia.ptd 1221669

It is set on the substrate and the wire junction, leaving only the wire structure. 'The substrate diffuses above the diffusion method and does not diffuse. Therefore, the problem of Merge) can occur around the structure, and the entire local area of the guide is directly embedded. When the strip is doped, the dopant is diffused in the wire structure to avoid being surrounded by the diffused wire structure embedded in the band, and the substrate is in contact, so that only the wire structure overlaps the side area surrounded by the barrier layer (BS is to obtain the above Aim, the present invention proposes a memory device with a vertical transistor and a trench capacitor, which mainly includes: a substrate, a trench valley device, a ring-shaped insulating layer, a diffusion barrier layer, a wire structure, a The top insulating layer of the trench and a control gate. The substrate has at least one trench, wherein a sidewall trench is provided on a sidewall of the trench, and upper and lower corners of the sidewall trench and the trench have an upper corner and a lower corner, respectively. In addition, a trench electric valley device is disposed at the lower part of the trench. Furthermore, a ring-shaped insulating layer is disposed at the surface of the sidewall of the trench above the trench capacitor. Furthermore, a diffusion barrier A layer is disposed on the bottom of the sidewall trench and a part of the sidewall and the surface of the ring-shaped insulating layer; and a wire structure is provided in an area surrounded by the ring-shaped insulating layer and the diffusion barrier layer; and the trench top insulating layer It is arranged on the wire structure. In addition, a control gate is arranged above the insulating layer on the top of the trench. Wherein, the diffusion barrier layer is not provided at the upper corner of the sidewall trench to make the wire The structure is in direct contact with the substrate at the upper corner. As mentioned earlier, the device of the present invention further includes an embedded band, which is placed in the substrate around the upper corner without the diffusion barrier layer as the Promise.

0548-9920TWF (Nl); 91231; FeHcia.ptd Page 9 1221669 ---------------------- 5. Description of the invention (4) As mentioned above, this The device of the invention further includes: a doped region disposed in the substrate around the control gate as a source. As mentioned above, the ring-shaped insulating layer is an oxide layer. The diffusion barrier layer is an oxide layer or a nitride layer. The mask layer is an oxide layer or a nitride layer. The trench top insulating layer is an oxide layer. As described above, the control gate includes a gate conductive layer and a gate dielectric layer disposed between the gate conductive layer and the substrate. The gate conductive layer is composed of a polycrystalline silicon layer, a tungsten silicon alloy layer, a metal layer, or a combination thereof, and the gate dielectric layer is composed of an oxide layer, a nitride layer, or a combination thereof. Make up. As mentioned earlier, the upper surface of the wire structure is lower than the upper corner. As mentioned earlier, the upper surface of the trench top insulation layer is higher than the upper corner. According to the present invention, the width of the upper corner where the diffusion barrier layer is not provided is generally 200 to 400 A. The invention also proposes a memory device having a vertical transistor and a trench capacitor, which is disposed in a substrate and mainly includes: a trench capacitor, a ring-shaped insulating layer, a wire structure, a diffusion barrier layer, a An insulating layer at the top of the trench and a control gate. A ring-shaped insulating layer is arranged above the edge of the trench capacitor. In addition, a lead structure is disposed above the trench capacitor and fills and protrudes from a region surrounded by the ring-shaped insulating layer. In addition, the diffusion barrier layer is interposed between the conductive wire structure protruding from the insulating layer and the substrate, and only the conductive wire is exposed.

0548-9920TWF (Nl); 91231; Felicia.ptd Page 10 1221669 V. Description of the invention (5) Part of the upper surface of the structure directly contacts the substrate. In addition, a trench top insulating layer is disposed above the middle region of the wire structure. Moreover, a control gate is disposed above the insulating layer at the top of the trench. As mentioned above, the upper surface of the middle region of the wire structure is lower than the position where the wire structure directly contacts the substrate. As mentioned above, the upper surface of the top insulation layer of the trench is higher than the position where the wire structure directly contacts the substrate. According to the present invention, the width of the area where the wire structure directly contacts the substrate is approximately 200 ~ 400 A. The invention also proposes the manufacture of a device for providing a semiconductor to form a trench electrical layer under the trench in a conductive layer in a domain. Then up. Then the surface. Then, the lower trench covered by the surface of the conductive layer is at the interface of the mask, the mask layer, and the boundary layer of the mask layer. The substrate has a method. Shape the container on the capacitor to form a trench and form a trench. Remove the trench. Next, a vertical method is formed at the lower boundary of the conductive layer and the curtain layer. The intermediate layer on the container is at least in the middle of the trench. The intermediate layer of the curtain layer forms a corner along the upper corner of the trench and a lower trench. . The side of the groove should be lowered to the middle to expose the side wall of the groove such as the groove, and then, in addition, the memory of the container is first raised. Next, a ring-shaped insulating connector is formed in a region surrounded by the layer of the ring-shaped insulating layer, the trench sidewall insulating layer and the underside of the cover layer to form a sidewall, sidewall trenches and grooves. The connection with the ring-shaped insulating crystal and the trench includes: forming a wall surface on the substrate. A ring-shaped insulating layer is formed above the conductive layer and the interlayer, and the substrate is engraved with the side groove and the cover is removed.

0548-9920TWF (Nl); 91231; Feii ^^^ 1 ^ · Page 11 1221669 V. Description of the invention (6): " "-curtain layer, then, along the side wall of the trench and the side wall A sidewall and a bottom of the trench conform to form a diffusion barrier layer. Next, an intermediate conductive layer is formed in the sidewall, the groove and the trench, wherein the upper surface of the intermediate conductive layer is lower than the upper corner. Then, the diffusion barrier layer located on the upper corner of the side wall of the trench is removed to form / side wall notches at the upper corner of the side wall trench. Next, an upper conductive layer is formed above the intermediate conductive layer to make the sidewall recess. Next, a trench top insulation is formed 'above the upper conductor. Finally, a control gate is formed above the insulation layer at the top of the trench. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in conjunction with the drawings. The detailed description is as follows: "[Embodiment]

In the following, please refer to FIG. 2 to FIG. 16 for cross-sectional views of the process, and the figure illustrates in detail one of the manufacturing methods of a dynamic random access memory (DRAM) structure having a vertical transistor and a trench capacitor according to the present invention. example. First, referring to FIG. 16, the structure of a dynamic random access memory (dram) having a vertical transistor and a trench capacitor according to the present invention will be described. The structure is mainly characterized by a diffusion barrier layer 23〇 & . Introducing this post? The structure mainly includes: a substrate 200, a trench capacitor 215, a bad insulation layer 220a, a diffusion barrier layer 23a, a lead structure 224a, 236, a trench top insulation layer 237, and a Control gate with? .

1221669 V. Description of the invention (7) The substrate 20 has at least one trench I, wherein one side of the trench I has one side, and the trench II is a sidewall trench. The upper edge of the trench I has an upper corner, respectively. II I and the lower corner π. In addition, the trench capacitor 215 is provided at the lower portion of the trench 1. Its structure includes a buried electrode plate (BP) 21 0, a compliant dielectric layer 2 1 2 and an electrode plate 2 1 4. In addition, the ring-shaped insulating layer 2 2 a is provided on the surface of the sidewall of the trench I above the trench capacitor 2 15, and the material includes an oxide layer. Furthermore, the diffusion barrier layer 230a is provided on the bottom and sidewalls of the side wall trench π and the surface of the side wall of the trench I above the ring-shaped insulating layer 23a, and the conductive structure 224a, 236 is doped by the thermal diffusion method When the diffusion of substances is driven into the substrate 200 to form a buried band, the diffusion barrier layer 2 3a surrounds the entire wire structure 2 24a, 236, leaving only a part of the area above the wire structure 22 4a, 236 directly with the substrate. The 200 contact, so the diffusion barrier layer 23a can be used to prevent the lateral diffusion of the dopant, so that the dopant diffuses only above the wire structure 22 4a, 23 6, which can avoid the overlap of the diffusion region of the buried band ( BS Merge) problem, and the material of the diffusion barrier layer 23a is, for example, an oxide layer or a nitride layer. In addition, the lead structures 22 ", 2 3, 6 are disposed in the area surrounded by the ring-shaped insulating layer 22 0a and the diffusion barrier layer 23 0a. The upper surfaces of the lead structures 2 2 4 a, 2 3 6 are preferably lower than the upper surfaces. Corner I &: Also, the trench top insulating layer 2 3 7 is provided on the wire structure 2 2 4 a, 2 3 6 and the trench top insulating layer 2 3 7 is, for example, an oxide layer, and the trench top edge layer 23 is The upper surface of 7 is preferably higher than the upper corner Π. In addition, the control gate 242 is provided above the trench top insulating layer 2 37. Among them, the side ditch & upper corner 111 is not provided with a diffusion barrier layer so that The wire structure is in direct contact with the substrate at the corner of ^, and no diffusion = stop is set at the upper corner Π.

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The width of the layer 230a is generally 200 to 400A. In addition, the control gate 242 includes a gate conductive layer 2 38 and a gate dielectric layer 2 40. The gate dielectric layer 240 is disposed between the gate conductive layer 238 and the substrate 2000. The gate conductive layer 238 is composed of a polycrystalline silicon layer, a tungsten silicon alloy layer, a metal layer, or a combination thereof, and the gate dielectric layer 240 is composed of an oxide layer, a nitride layer, or a combination thereof Made up. In addition, the structure of the dynamic random access memory (DRAM) with a vertical transistor and a trench capacitor of the present invention further includes an embedded band 3101, which is provided at a corner above the 23a where the diffusion barrier layer is not provided.丨 丨 1 in the substrate around it as the drain. In addition, there is still a doped region 3 02 disposed in the substrate 20 around the control interrogator 24 2 as a source. According to the present invention, the diffusion barrier layer 230a can surround the entire wire structure 2 24a, 236, leaving only a local area (the upper corner 111) above the wire structure 22 ", 236 directly in contact with the substrate 200. When the buried band 301 is formed by the diffusion method, the dopant will only diffuse from the lead structures 224a, 23 ^ to the upper substrate, and will not diffuse to the side of the lead structures 2 24a, 236 surrounded by the diffusion barrier layer 230a. Therefore, the problem of BS Merge of the buried region can be avoided. Next, with reference to the process cross-sectional views of FIGS. 2 to 16, a vertical transistor and a trench capacitor according to the present invention will be described. An embodiment of a method for manufacturing a structure of a dynamic random access memory (DR AM). First, please refer to FIG. 2 to provide a substrate 200, such as a silicon substrate. Formed in the substrate 2000 At least one trench. For example, a hard mask layer 202 is first formed on the substrate 200, and the hard mask layer 202 is formed of, for example, a pad oxide layer and nitrogen.

0548-9920TWF (Nl); 91231; Felicia.ptd Page 14 1221669 V. Description of the invention (9) Composition of broken layers, — groove pattern. ί = Trench chart, used to define 后续 " "Substrate 2 °°" to form a trench 1 on the base 215, and the bottom half of the direct-attach package &, / said to form a trench capacitor system, for example AN + Jing electrode plate 214. The doped region of the inside electrode plate 2 10 ^ electrode plate 2 14 Μ is located in the substrate 200 at the bottom of the trench 1. The material is, for example, a silicon oxide-silicon nitride (〇xide-nihide, nitrile 'layer). · Structure of 1 structure, or silicon oxide-silicon nitride-silicon oxide (. Xide-de-oxlde, abbreviated as) 〇) can be a conventional technique, and the method is, for example, 4 grooves / surface formation. A layer of, for example, an N + -type doped dielectric layer, such as arsemc S1iicate glass (referred to as ASG), and then filling the wire material f 'of t — y 罙 and removing the material that is not light I by engraving. The covered dielectric layer is removed, and then the photoresist material is removed, and then an insulating layer is deposited, such as tetraethoxy silicate (TE0s), to prevent: the thermal process of impurity ions in the post-processing It diffuses into the undoped trench 丨 the substrate 20 0 around the sidewall, and then passes through the rail process ς = ^ 盍 | The doped ions in the dielectric layer tend to enter the substrate 形成, and form, for example, = The doped region is used as the buried electrode plate 21G, and then the dielectric layer of the insulating layer is removed, and then a dielectric layer is deposited compliantly, and the trench I is filled to fill the trench I. The trench is removed by an etch-back process. The upper dielectric layer and the conductive layer on the stomach surface form a capacitor dielectric at the bottom of the trench. 0548-9920IWF (Nl); 91231: Felicia.ptd Page 15 1221669 V. Description of the invention (10) The layer 21 2 and the upper electrode plate 2 丨 4. ^ Refer to FIG. 3, and first use an appropriate deposition method, such as Chemical vapor dep0siti〇n; cvd, to conform An insulating layer made of a material such as silicon oxide is formed, and an anisotropic etching is used to remove the insulating layer above the mask layer 202 and the trench capacitor 215. 4 The insulating layer on the sidewall of the trench I is left to A ring-shaped insulating layer 2 2 0 is formed on the sidewall surface of the trench I. Next, a conductive layer is formed in the area surrounded by the ring-shaped insulating layer above the trench capacitor. Next, referring to FIG. 4, first A suitable deposition method, such as chemical vapor deposition (CVD), is used to comprehensively form a conductive layer to fill the trench 1. The material of the conductive layer is, for example, doped polycrystalline silicon or amorphous silicon, in which dopants For example, arsenic ions, the concentration of doped ions is about 1E15 ~ 5E15 atomic number / cubic centimeter, preferably 3E15 atoms ^ / cubic centimeter. Then, using chemical mechanical polishing (CMp) to planarize the conductive layer, an anisotropic etching is performed. Remove a portion of the conductive layer to a predetermined depth to leave a conductive layer 22 4 in the trench I. The conductive layer 2 24 is used as a mask, and the ring-shaped insulating layer 22 is selectively etched by anisotropic etching. The height of the trench I is slightly lower than that of the lower conductive layer 224. / 、 Next, please refer to FIG. 5. For example, first use chemical vapor deposition (C VD) 幵> to form an intermediate layer in the trench I, and then use an appropriate non-isotropic etching method to reduce the intermediate layer to A predetermined thickness is formed to form the middle 22 6 above the lower conductive layer 2 24 and the ring-shaped insulating layer 220 a. Among them, the material of the middle & second 226 is, for example, silicon oxide, and the intermediate layer 226 will be used to define the opening ^ page 16 0548-9920TWF (Nl); 91231; FeHcia.ptd 1221669 Description of the invention (11) into the sidewall groove The location of the slot. Next, referring to FIG. 6, a suitable deposition method, such as chemical vapor deposition (CVD), is used to conformally deposit a nitride or oxide on the sidewall and bottom surface of the trench, and then, By using an appropriate etching method, such as anisotropic dry etching, the nitride or oxide at the bottom of the trench I is removed, leaving only the nitride or oxide at the sidewall of the trench 丨 as a mask layer 2 2 8. Next, referring to FIG. 7, the mask layer 228 is used as a mask, and the intermediate layer 22 6 is selectively etched to expose the surface of the ring-shaped insulating layer 22a and the lower conductive layer + 2 2 4. Next, referring to FIG. 8, a portion of the lower conductive layer 2 24 and the substrate 200 of the sidewall of the trench I is isotropically etched along the trench I along the trench I, so that a sidewall trench II is formed on the mask. On the sidewall of the trench I below the curtain layer 2 2 8. The etchant is, for example, a selective ratio of nitride to polycrystalline silicon of about ≧ 25: 25 wt% /% ammonia water (NΗ40Η). An upper corner I 11 is formed at the boundary between the sidewall trench II and the mask layer 22 8, and a lower corner VI is formed at the boundary between the sidewall trench II and the annular insulating layer 22 0a. Next, referring to Fig. 9, the mask layer 2 28 is removed by using an appropriate etching solution. Then, along the sidewall of the trench I and the sidewall and bottom of the trench I 沟槽, for example, a chemical vapor deposition method (chemica 1 vapor deposit ion; CVD) is used to conformally form a material such as nitride. Diffusion barrier layer 2 3 0. Next, referring to FIG. 10, using an appropriate deposition method, such as chemical vapor deposition (CVD), an intermediate conductive layer 232 is formed on the remaining conductive layer.

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V. Description of the invention (12) The trench j wall trench or amorphous silicon above 224a and above the ring-shaped insulating layer 22os, T T rb day, day inside, and filling side. The material of the intermediate conductive layer 2 32 is, for example, an undoped polycrystalline spar. Then, please follow FIG. 11 and, for example, use chemical mechanical polishing and anisotropic etching to make the intermediate conductive layer 232 along the trench. 1 The recess is reduced to reduce the thickness, so that the upper surface of the intermediate conductive layer 232 is lower than the upper corner III. In this way, the diffusion barrier layer 230 at the upper corner II is exposed. Among them, the side wall trench is still filled with 0 by the middle conductive sound u 2. Then, referring to FIG. 12, a proper wet etching method is used to remove the diffusion barrier layer located on the side wall surface of the trench I and the upper corner 111 2 3 〇, a sidewall notch 300 is formed at a corner 111 above the sidewall groove 11. Then 'please refer to Figure 13' using an appropriate deposition method, such as chemical vapor deposition (CVD), to form an upper conductive layer 23 4 over the remaining intermediate conductive layer 2 3 2 a to fill the sidewall recess 3 0 0 and trench I. Next, please refer to FIG. 14, for example, by chemical mechanical polishing (c μ p) and anisotropic etching, the upper conductive layer 23 4 is recessed along the trench and the sidewall of the trench I to reduce the thickness, and the upper conductive layer is recessed. The upper surface of the layer 234 is preferably lower than the upper corner III. The remaining lower conductive layer 224a, the intermediate conductive layer 232, and the remaining upper conductive layer 236 together constitute a conductive structure. The thickness of each layer of the conductive structure can be adjusted according to the needs of the manufacturing process, and is not limited here. Next, a trench top insulating layer is formed over the upper conductive layer. Next, referring to FIG. 15, a trench top insulating layer 2 3 7 is formed in the trench I above the remaining upper conductive layer 236 for subsequent control.

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The insulation barrier between the gate and the entire wire structure.

Finally, referring to FIG. 16, a gate dielectric layer 24 〇, a gate conductive layer 238, and a gate conductive layer 238 are formed in the trench I above the trench edge layer 2 37 using conventional techniques. The material is, for example, a polycrystalline silicon layer, a tungsten silicon alloy, a metal layer, or a combination thereof. The material of the gate dielectric layer 24 is, for example, an oxide layer. The method is, for example, to use a thermal oxidation method to form a gate dielectric layer 24 on the sidewall of the trench I above the trench top insulating layer 2 37, and then in a region surrounded by the polar dielectric layer 2 40 A gate electrode conductive layer 238 is formed. In this embodiment, the gate dielectric layer 240 and the gate conductive layer 238 constitute the control gate 242 in the memory device of the present invention. A chicken implantation is then performed to form a doped region 302 in the substrate 200 above the periphery of the control gate 242 as a source of the vertical transistor. The formation of the buried band 3 01 is, for example, formed by expanding the ions into the substrate 2 0 by a subsequent thermal diffusion process. The relatively high concentration of ions doped in the lower conductive layer 224a diffuses from the intermediate conductive layer 232 or the upper conductive layer 23 6 into the surrounding substrate 2000 due to thermal diffusion, and the diffusion region is the intermediate conductive layer. 2 3 2 A semi-circular area with a center at the outer end. The diffusion radius above the area exceeds the thickness of the insulating layer 237 at the top of the trench and is connected to the control gate 242%. In this embodiment, the buried region 301 is used as the drain region of the vertical transistor. According to the memory device with a vertical transistor and a trench capacitor of the present invention, since the diffusion barrier layer 230 a is ringed around the substrate 200 and the lead structures 23 6 and 224 a, the entire lead structure 23 6 and 22 “is surrounded. Up, leaving only the local area above the wire structure 2 36, 224a directly connected to the substrate 20 ()

1221669 V. Description of the invention (14) In this way, when the buried band 3 0 1 is formed by the diffusion method, the dopant will only diffuse from the wire structure 23 6 and 224 a to the upper substrate 20 0 (upper corner 11 I ) 'Will not diffuse to the side of the wire structure 23 6, 224a surrounded by the diffusion barrier layer 2 30a, so that the problem of overlapping overlapping regions (BSMerge) of the buried band 3 001 can be avoided. Although the present invention discloses the scope of the present invention in a preferred embodiment, any person familiar with the spirit and scope can take various protection scopes as the attached application patent is disclosed above, but it is not intended to limit the artist. Without departing from the modifications and retouching of the present invention, the scope defined by the present invention shall prevail. a

1221669 Brief Description of Drawings Figure 1 is a cross-sectional view of a structure showing a conventional problem of diffusion overlap of buried bands. Figures 2 to 16 are cross-sectional views showing a process of a preferred embodiment of a memory device having a vertical type transistor and a trench capacitor according to the present invention. [Symbol description] 2 0 0 ~ substrate; _ 22 0 a ~ ring insulation layer; 2 3 0 a ~ diffusion barrier layer; 2 3 7 ~ trench top insulation layer; 2 4 2 ~ control gate; I ~ trench 1 I ~ sidewall trench; 11 I ~ upper corner; VI ~ lower corner; 2 1 5 ~ trench capacitor; 210 ~ buried electrode plate; 2 1 2 ~ capacitor dielectric layer; 21 4 ~ electrode plate 22 0a ~ ring insulation layer; 2 3 8 ~ gate conductive layer; 240 ~ gate dielectric layer; 3 0 1 ~ buried band;

0548-9920TWF (Nl); 91231; FeHcia.ptd Page 21 1221669 Brief description of the drawings 2 0 2 ~ hard cover curtain layer; 22 4 ~ lower conductive layer; 2 2 6 ~ middle layer; 2 2 8 ~ cover curtain layer 2 3 2 ~ middle conductive layer; 23 4 ~ upper conductive layer; 23 6 ~ upper conductive layer remaining; 3 0 ~ side wall notch; 224a ~ lower conductive layer remaining.

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Claims (1)

1221669 VI. Application Patent Set 1 · A memory device with a vertical transistor and a trench capacitor includes: a substrate having at least one trench, wherein a sidewall of the trench has a sidewall trench, and the sidewall The junction of the trench and the trench has an upper corner and a lower corner, respectively; a trench capacitor is disposed at the lower part of the trench; "annular insulation layer is disposed at the surface of the sidewall of the trench above the trench capacitor; _ w a diffusion barrier layer disposed on the bottom and sidewalls of the sidewall trench and a portion of the surface of the% insulation layer; a wire structure disposed in an area surrounded by the annular insulation layer and the diffusion barrier layer; A trench top insulating layer is disposed above the wire structure; and a control gate is disposed above the trench top insulating layer, wherein 'the diffusion barrier θ is not provided at the upper corner of the sidewall trench so that The wire structure is in direct contact with the substrate at the upper corner. 2 · The memory device with a vertical transistor and a trench capacitor as described in item 1 of Shenyan's patent scope, # further includes: —Buried tape 'is placed on the upper corner of the area where the diffusion barrier layer is not provided. This substrate is used as the drain. 2. The surname t is a memory device with a vertical transistor and a groove: a container as described in item 1 of the scope of the patent application, which further includes: a strainer with a “pushing miscellaneous area” disposed above the control gate. The substrate acts as a source. 1221669 6. Scope of patent application 4. The memory device with vertical transistor and trench capacitor as described in item 1 of the scope of patent application, wherein the ring-shaped insulating layer is an oxide layer. 5. The memory device having a vertical transistor and a trench capacitor as described in item 1 of the scope of the patent application, wherein the diffusion barrier layer is an oxide layer or a nitride layer. 6. The memory device having a vertical transistor and a trench capacitor as described in item 1 of the scope of the patent application, wherein the width of the upper corner without the diffusion barrier layer is generally 2000-4000 A. 〇 7. The memory device having a vertical transistor and a trench capacitor as described in item 1 of the scope of the patent application, wherein the top insulating layer of the trench is an oxide layer. 8. The memory device having a vertical transistor and a trench capacitor as described in item 1 of the scope of the patent application, wherein the control gate includes: a gate conductive layer; and a gate dielectric layer disposed on the gate Between the gate conductive layer and the substrate. 9. The memory device having a vertical transistor and a trench capacitor as described in item 8 of the scope of the patent application, wherein the gate conductive layer is composed of a polycrystalline silicon layer and a crane; A metal layer or a combination thereof. 10. The memory device having a vertical transistor and a trench capacitor according to item 8 of the scope of the patent application, wherein the gate dielectric layer is composed of an oxide layer, a nitride layer, or a combination thereof. 11. The memory device having a vertical transistor and a trench capacitor as described in item 1 of the scope of patent application, wherein the upper surface of the wire structure is lower than 0548-9920TWF (Nl); 91231; Felicia.ptd Page 24 1221669 Sixth, the scope of patent application This upper corner. 12. The memory device with a vertical trench capacitor as described in item 1 of the scope of the patent application, wherein the top of the trench must be lumped =-the surface is higher than the upper corner. Table 13 of the genus Arachnida · A device with a vertical transistor and a trench capacitor, which is arranged in a substrate, including a " trench capacitor; a ring-shaped insulating layer, which is arranged on the edge of the trench capacitor Above; a wire structure, which is disposed above the trench capacitor and fills and protrudes from the area surrounded by the ring-shaped insulating layer; a large diffusion barrier layer, pads the wire structure protruding from the ring-shaped insulating layer and Between the substrates, only a part of the upper surface of the wire structure is exposed to be in direct contact with the substrate; a trench top insulation layer is disposed above the middle region of the wire structure; and a control gate is disposed at the top of the trench for insulation Layer above. 1 4 · The memory device having a vertical transistor and a trench capacitor as described in item 13 of the scope of the patent application, further comprising: an embedded tape disposed above the wire structure directly in contact with the substrate The substrate acts as a drain. 1 5 · The memory device having a vertical transistor and a trench capacitor as described in item 13 of the scope of the patent application, further comprising: a doped region disposed in the substrate around the control blue electrode, Take as source. ^ 21669 VI. Please Lifan®, 16 · The memory device with vertical transistor and trench capacitor as described in item 13 of the patent application scope, wherein the ring-shaped insulating layer is an oxide layer. '1 7 · The memory device having a vertical transistor and a slot capacitor as described in item 13 of the scope of the patent application, wherein the diffusion barrier layer is an oxide layer or a nitride layer. 1, 8 · The memory device having a vertical transistor and a trench capacitor as described in item 3 of the scope of the patent application, wherein the width of the area where the wire structure directly contacts the substrate is approximately 200 to 40 °. 19. A memory device having a vertical transistor and a trench capacitor as described in item 3 of the scope of the patent application, wherein the top insulating layer of the trench is an oxide layer. 2 0. The memory device having a vertical transistor and a trench capacitor as described in item 13 of the scope of the patent application, wherein the control gate includes: a gate conductive layer; and a gate dielectric layer, It is disposed between the gate conductive layer and the substrate. 2 1 · A memory device having a vertical transistor and a trench capacitor as described in item 20 of the scope of the patent application, wherein the gate conductive layer is composed of a polycrystalline silicon layer, a tungsten silicon alloy layer, a metal layer or Composed of its combination. 22. The memory device having a vertical transistor and a trench capacitor as described in item 20 of the patent application scope, wherein the gate dielectric layer is composed of an oxide layer, a nitride layer, or a combination thereof. 23 · A memory device having a vertical transistor and a trench capacitor as described in item 3 of the scope of the patent application, wherein the middle area of the wire structure \ m 0548-9920TWF (Nl); 91231; FeHcia.ptd No. 26 Page 1221669 6. The upper surface of the scope of patent application is lower than the position where the wire structure is in contact with the substrate j :. 2 4 · The memory device having a vertical transistor and a trench capacitor as described in item 3 of the patent application scope, wherein the upper surface of the insulation layer at the top of the trench is higher than the position where the wire structure directly contacts the substrate . 25 · —A method for manufacturing a memory device having a vertical transistor and a trench capacitor, comprising: providing a semiconductor substrate; forming at least one trench in the substrate; forming a trench capacitor below and below the trench Forming a ring-shaped insulating layer on the surface of the sidewall of the trench above the trench capacitor; forming a lower conductive layer in a region surrounded by the ring-shaped insulating layer above the trench capacitor; forming an intermediate layer on the lower conductive layer Layer and the annular insulating layer; forming a mask layer on the surface of the sidewall of the trench above the intermediate layer; removing the intermediate layer to expose the surface of the annular insulating layer and the lower conductive layer; along the trench Isotropic etching does not cover the substrate of the mask layer and the sidewall of the trench, so that a sidewall trench is formed; the trench below? On the side wall, wherein the side wall groove and the boundary of the cover layer J form an upper corner, and the side wall groove and the ring-shaped insulation corner; Removing the cover layer; conforming along the sidewall of the trench and the sidewall and bottom of the trench 1221669 6. Apply for a patent to form a diffusion barrier layer; form an intermediate conductive layer in the sidewall trench and the trench 'where the upper surface of the intermediate conductive layer is lower than the upper corner; remove the surface located on the sidewall of the trench Forming the diffusion barrier layer with the upper corner to form a sidewall recess at the upper corner of the sidewall groove; forming an upper conductive layer above the intermediate conductive layer to fill the sidewall recess; Forming a trench top insulating layer over the upper conductive layer; and forming a control gate over the trench top insulating layer. Then 26. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of the patent application, which further includes: forming an embedded band in which the diffusion barrier is not provided and the barrier layer The bottom of the talk around the upper corner, as the endless. 27. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of the patent application, which further includes: forming a doped region in the substrate around the control gate, Take as source. 28. The method for manufacturing a memory device having a vertical transistor ❶ and a trench capacitor as described in item 25 of the scope of the patent application, wherein the ring-shaped insulating layer is an oxide layer. 2 9 · The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of patent application, wherein the lower conductive layer is a doped polycrystal;杂 的 # 晶石 夕 层. 30. A vertical transistor as described in item 25 of the patent application 0548-9920TWF (Nl); 91231; Felicia.ptd 1221669 6. Method of manufacturing patented memory devices for trench capacitors, wherein the intermediate conductive layer is a doped polycrystalline silicon layer or a doped amorphous silicon Floor. 3 1. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the patent application scope, wherein the upper conductive layer is a polycrystalline silicon layer or an amorphous layer. 32. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the patent application scope, wherein the intermediate layer is a polycrystalline silicon layer. 33. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the patent application scope, wherein the diffusion barrier layer is an oxide layer or a nitride layer. 34. The method for manufacturing a memory device having a vertical transistor and a trench capacitor according to item 25 of the scope of the patent application, wherein the mask layer is an oxide layer or a nitride layer. 35. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of the patent application, wherein the width of the trench notch is generally 2000 to 400 A. 36. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of the patent application, wherein the insulating layer at the top of the trench is an oxide layer. 37. The method of manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of the patent application, wherein the control gate includes: a gate conductive layer; and 0548-9920TWF (Nl); 91231; FeUcia.ptd Page 29 1221669 6. Scope of patent application A gate dielectric layer is disposed between the gate conductive layer and the substrate. 3 8. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 37 of the scope of the patent application, wherein the gate conductive layer is composed of a polycrystalline chip layer, a chopped alloy layer, A metal layer or a combination thereof. 39. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 37 of the scope of patent application, wherein the gate dielectric layer is composed of an oxide layer, a nitride layer, or a combination thereof Made up. 40. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of patent application, wherein the upper surface of the upper conductive layer is lower than the upper corner. 41. The method for manufacturing a memory device having a vertical transistor and a trench capacitor as described in item 25 of the scope of the patent application, wherein the upper surface of the insulating layer at the top of the trench is higher than the upper corner. ( 0548-9920TWF (Nl); 91231; FeUcia.ptd page 30