TWI221658B - Method for coding semiconductor permanent store ROM - Google Patents

Abstract

A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array and all transistors are initially in an ""ON"" state. A second dielectric layer covers at least one layer of metal interconnection formed over the first dielectric layer. The bit lines do not overlap the transistor sources. A coding photoresist layer is formed on the second dielectric layer and is patterned to form a plurality of apertures defining exposure windows exposing underlying field-effect transistors to be coded permanently to an ""OFF"" state. A code etching back process is implemented using the photoresist layer as a mask to etch the first and second dielectric layers, the sources of the MOSFETs, and a portion of the substrate through the exposure windows to form a deep trench, disconnecting the coded MOSFETs from the source lines.

Description

1221658 — _____________________ Room Width —.92114984 — ^ V. Description of the Invention (1) The technical field to which Long Ming belongs The present invention relates to a method for making a read-only memory device, especially a method of encoding a read-only code into a semiconductor read-only memory The later part of the system process can be used to shorten the product turn-around time. The feature of the present invention is that the read-only memory unit is edited by deep trench etching, instead of the conventional starting S pressure voltage implantation. It is a firmware, which is a type of integrated circuit that is first burned into a specific program or information during the production stage. Read-only notes [In addition to being used in computers, the thinking chip is also used in many electronic products. The process of writing a program or information into memory is also known as coding. Several coding methods have been developed for different stages of the memory process. • One of the widely used methods is called the starting voltage distribution method, which uses the ion distribution value to change the initial drop value of the transistor. For example, to encode an N-channel memory cell, a predetermined dose of a dopant such as Shi Peng is implanted into the transistor gate channel region, thereby increasing its initial voltage value, and storing the memory. The cell is switched to the “n OFF” state. Another coding method is to selectively open the contact hole connected to the transistor and the pole to form an open circuit state. This method is also known as the through-contact hole stylization technology (Thr 〇ugh-h ο 1 ec ο ntact Programming technique), because each transistor needs to be provided with 1221658 ............... .......... M 92114984 ____________________________ color ——... _____________ day _____________________ Youzheng V. Description of the invention (2) A contact hole, so it needs to occupy a large chip area. The implantation step is usually performed at the later stage of the memory system process. This is because the more read-only code writing or encoding is performed at the later stage of the memory system process, the shorter time can be used to complete wafer fabrication after encoding. Customers The client will usually require that the Within the shortest time to deliver the finished product to the customer hands, that is compressed to the shortest product delivery. In this case, the use of a shorter time to complete wafer producers can Huo was the shortest product delivery ..

Known technologies such as U.S. Patent No. 4,266,950, proposed by C h a 11 e r j e e et al., Disclose an N-channel MOS read-only memory system operation method, which can be programmed in the later stages of the process. The programming method uses a boron ion to pass through the protective silicon nitride layer, polycrystalline silicon, and gate oxide layer of the memory array to change the initial voltage of the transistor. For another example, US Patent No. 5 154 6 0 9 proposed by Chen et al. Discloses the manufacture of read-only memory, the encoding of which is performed before the metallization (me t a 1 1 i z a t i ο η) process. The coding system uses a read-only code dopant implanted under the selected gate, which passes through a dielectric layer and the gate. Another example is U.S. Patent No. 6,002,241, proposed by You et al., Which discloses a method for making a read-only memory, which can be code-implanted after the first layer of metal is completed, thereby shortening the product delivery time. The code implantation is to implant the replacement material through the first dielectric layer on the gate, the second dielectric layer on the first dielectric layer, and finally through the word line segment.

Page 9 1221658… ———— room collection—921149 fall ^ ^ V. Description of the invention (3) Cang Ming content The main purpose of the present invention is to provide a high-density read-only memory device f manufacturing method, which can shorten the product delivery time. . In a preferred embodiment of the present invention, a method for manufacturing a read-only memory device is disclosed, which can shorten the product delivery time. The method includes the following steps: providing a semiconductor substrate with a metal-oxide semiconductor field effect transistor (metal) -oxide-semiconductor field-effect transistor) array is disposed in a read-only memory region, and a dielectric layer t covers the gold-oxygen semiconductor field effect transistor array in the read-only memory region, wherein each of the gold-oxygen The semiconductor field-effect transistor has a gate, a source and a drain, and the gold-oxide semiconductor field-effect transistor is initially in an on state of π ΟΝπ; a coding photoresist layer is formed on the dielectric layer; lithography The coded photoresist layer is imaged to form a plurality of openings, which define a metal-oxide-semiconductor field-effect transistor in the read-only memory area below to be written and switched from the ON state to the OFF n 0FF1 state. The window of the crystal, wherein the window is located directly above the source of the metal-oxide-semiconductor field-effect transistor to be written; the coded photoresist layer is used as an etching mask to perform an etch-back During the etching process, the dielectric layer is etched through the window, the source of the MOSFET is to be written, and a part of the substrate is etched downward from the source. The etching depth must be lower than that to be performed. The junction depth of the source of the MOSFET is written, so that a deep trench is formed, so that the source and the FET of the MOSFET to be written are cut off.

Page 10 1221658 _ MM. _ 92114984 JF: Ά ^ _ a #i V. Description of the invention (4) Connection of the supporting wire; removing the coded photoresist layer; and depositing a trench filling layer on the dielectric, and Fill the deep trench. According to another preferred embodiment of the present invention, a method for fabricating a memory device is disclosed, which can shorten the product delivery time. The method includes a step of providing a semiconductor substrate having a metal-oxide semiconductor field on it. Each of the metal-oxide-semiconductor field-effect transistors in a read-only memory region and the first dielectric I field of the metal-oxide-semiconductor field-effect transistor array has a gate, A source is connected to the source line, and the metal oxide semiconductor field effect transistor is in an on state of π ON; a bit line is formed on the dielectric layer in the read-only memory region, where the The bit line is covered by a second dielectric t, which bypasses the metal-oxide semiconductor field effect transistor 绕 below to avoid overlapping with the source; a series of: and layers are formed on the second dielectric layer; This coded photoresist layer is formed to form a plurality of ports, which define the window of the metal-oxide-semiconductor 4 crystal which is to be written in the read-only memory area below and changed from the “0Nπ state to the“ n OFF ”state. ; Use the coded photoresist layer as an etch mask Mask, enter the code etch-back process, and etch the second dielectric layer, the dielectric layer, and the source of the FET field effect transistor to be written from the source down to a portion of the The depth of the substrate ^ must be low. The depth of the junction of the source of the FET semiconductor field-effect transistor to be written is formed so as to form a deep trench, thereby cutting off the source and source of the FET half-effect transistor to be written The connection of the epipolar lines; and removing the resistive layer. Finally, a trench filling layer is deposited on the second dielectric layer, and only the lower-effect electrical layer is overlaid on the second dielectric layer. The source of the first electrical layer is opened, and the first effective electrical line is opened. At this degree, the conductor coded light, and 1221658 said to modify ______________ room 2114 to 84. V. Description of the invention (5) The deep trench is really full. In order to achieve the above-mentioned object of the present invention, a preferred embodiment is given below. The features and advantages of the embodiments can be more obvious and easy.

Therefore, the preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 17. Those skilled in the art should understand that the semiconductor region t type and electrical properties, component layout, voltage polarity, etc. in the embodiments are for reference only and are not intended to limit the present invention. First, referring to FIG. 1, FIG. 1 shows one of the read-only memory arrays Lang Lang. The read-only code is written according to the method of the present invention. Read-only memory The hidden array includes many memory cells, and only four of them are shown for convenience. As shown in FIG. 1, the four memory cells illustrated are distinguished into memory cell (0, 0), memory cell (0, 1), and

Memory cell (1, 0) and memory cell (丨, i). Each memory cell is actually a metal-oxide-semiconductor (MOS) transistor with a gate 10, a drain 12 and a source 14. Gate 10 is a segment of word line w10, WL1. The drain electrode 12 is an N + squeeze region, and is electrically connected to a bit line or a γ output line BL0, BU. Sources 1 and 4 are N + doped ||, and 恍 鲋 a and drains 12 are defined simultaneously. According to the present invention's specific two-dimensional code (b i n a r y c o d e), a source-side encoding mask and an etch-back process are used to write the read-only memory array. Such as

Page 1212658 ......... 9211498 Born-Emperor Moon ......... Day. Amendment ............... ... — "… — · —— V. Description of the Invention (6) As shown in the figure, the source electrode 14 of the memory cell (0,0) is the original source and line that were cut off. Link to record digital information π 1 ". For other memory cells of digital memory" 〇 ", its source 1 4 still maintains the source line connected to ground or Vss bias (not shown) Electrically connected. /, Referring to FIG. 2 to FIG. 8, a first comparative embodiment of the present invention will be described in a cross-sectional view. As shown in FIG. 2, a semiconductor substrate 2000 is first provided with an upper surface including a plurality of the upper surface. MOS transistor 101, ι〇2 and ^

2 0 1. The upper surface of the semiconductor substrate 2000 is roughly divided into a read-only memory, a body region 301, and a peripheral region 302. The memory composed of many memory cells = the array is set in the read-only memory area 3 0 1 and only the memory cells 1 i = and 1 0 2 are displayed. The M 0 S transistor 201 ', which can be an active element in a peripheral circuit, is located in the peripheral region 3 02. Each of the thunder crystals located in the read-only memory region 301 includes a gate 401, a drain 402, and a source 403. The gate 401 is a word line or X. For the segment of the address line, the source 403 is a source line (not shown) connected to ground or to a V ss bias. As shown in Fig. 3, the read-only memory area 3〇 丨 and the peripheral area 3202 are not connected. It can be an LPCVD oxygen cut layer or a 叩% layer? Ϊ: Two, the layer is between 2 0 0 0 to 70 0 0 angstroms. / 、 Slave thickness

As shown in FIG. 4, a pattern 601 is formed on the dielectric layer 501. The coded photoresist layer 601 is then exposed to ultraviolet light and imaged with a reticle that blocks the customer's read-only code. Then develop ^ = I bake, wash away the unexposed photoresist layer 601, and leave the plural ^ < It defines the read-only memory area 3〇 丨 below to be written into =

1221658 V. Description of the invention (7) The window of the memory cell in the “n OFF” state. In this embodiment, the memory pack 1 0 2 is selected as the memory to be written to become the permanent n OFF π state » Cell, and only a single window 6 1 1 is shown in the figure. It should be noted that at this stage, the surrounding area 3 2 is still covered by the coded photoresist layer 6 0 1. Please refer to the figure, which is shown in Figure 4. The top view of the memory cell 10 2 and the window 6 1 1. As shown in Figure 圯, the length L of the window 6 1 1 must be greater than the width W of the memory cell 1 0 2 and the pole 4 0 3 to be written. As shown in FIG. 5, the code photoresist layer 6 0 1 is used as a mask to perform an I-insect process through the window 6 1 1 and the source of the dielectric layer 5 0 1 and the crystal 1 0 2 is performed. Electrode 4 0 3, and a part of the substrate 2 0 0 is etched downward from the source 4 3, the etching depth must be lower than the junction depth of the transistor 10 2 source 4 3, b this forms a deep trench 7 1 1. In other words, in order to successfully store digital information π Γ in transistor 102, the depth of deep trench 7 1 1 must be greater than the thickness of dielectric layer 5 0 1 and transistor 1 0 2 source 4 0 3 Joint Sum of depth. By describing the method of L, the source 4 0 3 of the transistor 102 can be switched from the original connection state to the cut-off state to store the digital information π 1 ''. As shown in FIG. 6, the coded photoresist layer 6 0 1 is then removed, and then the dielectric layer 701 is really inserted into the deep trench 7 1 1. As shown in FIG. 7, according to the first preferred embodiment of the present invention, read-only is completed. After the coding in the memory area 3 01, the metallization process is performed. Firstly, a photoresist layer 8 0 1 is covered on the dielectric layer 7 0 1 and an opening 8 1 1 is formed by a lithography process to define a read-only The positions of the contact holes in the memory region 3 0 1 and the peripheral region 3 2 0. Then, a process of etching is performed, and the dielectric layer is etched through the opening 8 1 1

1221658 ___________________________________________________, Case No. 921149y V. Description of the invention (8) Revise 7 0 1 and the dielectric layer 5 0 1 to expose part of the lower part, Λ < and pole 4 fi?, 荽 contact hole 9 1 1. The following metallization process includes technical Z metallization, formation of contact plugs

As for the definition of metal wire deposition and etching, since it is well-known to those of the 7X generation, they will not be repeated here. πquarrying stone corpse / T Please refer to Fig. 10 to Fig. 15 '. The following is a detailed description of the second preferred embodiment 7 of the present invention by using the schematic diagrams of Fig. 10 to Fig. 15 It follows the same convention as in the previous figure: as shown in & X, a semiconductor substrate 200 is provided first, with a list of ^ ~~. The surface angle L includes a plurality of MOS transistors 101, 102, and 201. Similarly, the upper surface of the semi-conductor substrate 200 is roughly partitioned into the read-only memory 7 area 3 0 ^ 乂 殳 peripheral area 3 2. A memory array composed of many memory cells is located in the memory region 3 0 1 ′, and only memory cells 1 Q 1 and 102 are displayed. The MOS transistor 201, which can be an active element in a peripheral circuit, has a side region of 302. Each Mos transistor located in the read-only memory area 3101 includes a gate 401, a drain 402, and a source 403. In the middle, = f = 0 1 is a character. A segment of a line or an X address line, the source electrode 403 is electrically connected to a source line connected to ground or Vss bias (not shown).

As shown in FIG. 11, then in the read-only memory region 3101 and the peripheral ubiquitous dielectric layer 501, it may be an LPCV_ oxygen layer or a PSG layer. Its preferred thickness is between 2000 and 2000. About 70 0 0 Angstroms. Inside

1221658 Amendment One by One_Case No. 92114984 ------------------------------------ ------------------- J________ J 4 V. Description of the Invention (9) — Sleep plug. As shown in the figure, the contact plug C is formed in the dielectric layer ii 1: 7 3001, and the first layer of metal is formed in the dielectric layer 50f. The bit lines are formed through i = ± formed in the dielectric layer 501. 2Electrically connect the M0S transistors 101 and 102 to the bottom electrode 402. 1 to 2 Figures: VI, which shows the top view of the spring layout pattern in Figure 12 in the read-only memory area 301. . The bit lines are generally arranged in an orthogonal manner below the other, but the bit lines must bypass the source region 2 below to avoid overlapping with the source region 403. A second & = wire M f is formed on the interlayer dielectric layer 5 0 2 forming the first layer of metal conducting green ΐ and is located in the peripheral region 3 0 2. The interlayer dielectric plug V in the interlayer dielectric two rain 02 is electrically connected to the first-layer metal interconnect. The interlayer y electricity ^ 5 0 2 also covers the bit line L in the read-only memory area 3 〇 丨 at the same time, after the metallization process is completed, then the second layer of metal interconnects m2, = f, the body area 3 The interlayer dielectric layer 502 in the 〇1 and the peripheral region 302 is covered with a second security layer 503. Subsequently, these semiconductor codes 2 ^ that have not been written into the read-only code are stored in the warehouse, waiting for further instructions from customers so that the read-only code data provided by each household can be used for the next memory editing operation. / Yi as shown in Figure 12 ’After receiving the customer ’s code-only content, enter I, horse, and enter actions. The coded photoresist layer 6 0 1 is first covered with a dielectric layer 5 0 1 and 11. The photoresist layer 6 01 is then exposed to ultraviolet light and imaged with a lithographic mask defined by a unique code. Then, development and subsequent baking are performed. The unexposed photoresist layer 60 丨 is washed away, leaving a plurality of openings.

Month, 1221658-_ said correction, "face" 2114984 V. Description of the invention (10) _ ί Stomach area 301 is to be written into the window of the memory cell of eternal 〇FF shape sadness. In this embodiment, the cell 102 is selected as the sister; 隹 ^-warehouse%, ° body cell, and Figure 2 is / dry order: to become the memory section of the QFF " state, peripheral area 302 V / port 611 is still being programmed. It should be noted that at this stage XVII, ΛΓΛ is under the cover of the resistance layer 601. Please refer to FIG. 17 for the top view of the memory cell 102 and the window 611 in FIG. 12 == not shown in FIG. 14, and then use the coded photoresist layer 6 〇 丨 as an inter-engraving process, and protect it through the window 611. Layer 503 ', 7f S Γίΐ ^ 2, dielectric layer 501, source 102 of transistor 102, transistor 02 source 4 {; connection of 3 " ^ 之 / 底 20 0 The depth of the touch engraving must be lower than the & 7 ^ joining angle, so a deep trench 7U is formed. ',, month b; electric day and sun body 1 0 2 stores digital information " 1 ", deep groove quasi 7 1 1 deep; # must be greater than protective layer 503, interlayer dielectric layer 502, and The sum of the junction depth of the transistor terminals 40 3. With the above-mentioned method, the source 40 3 of the transistor 102 can be switched from the original connected state to the cut-off state with the source line, thereby storing digital information. As shown in the figure, the coded photoresist layer 60 is removed, and then the dielectric layer 70 is filled in the deep groove Zhu 1. As mentioned above, the better the read-only code implantation step 4 is performed in the later stage of the memory system, the better. . This is to perform read-only code writing or encoding at the later stage of the memory system, and the wafer production can be completed in less time. The client usually requires the shortest time after the manufacturer receives the read-only code. The finished product will be delivered to the customer's hand, which will shorten the product delivery time to the shortest. The present invention encodes

1221658

92114984 η a J ^ SL V. Description of the invention (11) The postponement of the step is performed after the metallization process, which can achieve the purpose of minimizing the product delivery time. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent for the invention.

Page 18 1221658 Case No. 92114984 —Year Month Front _____________________________ Brief Description of the Drawings Brief Description of the Drawings Figure 1 shows a portion of a read-only memory array that is read-only coded according to the method of the present invention. Figures 2 to 8 are sectional views illustrating a first preferred embodiment of the present invention. Figure 9 is a top view of the memory cell and the window in Figure 4. 10 to 15 are schematic cross-sectional views illustrating a second preferred embodiment of the present invention in detail. Figure 16 shows the top view of the special bit line layout pattern in Figure 12 in the read-only memory area. Figure 17 is a top view of the memory cell and the window in Figure 13. Symbols of the drawings 10 Gate 12 Drain 14 Source 101 Transistor 102 Transistor 200 Semi-special substrate 201 Transistor 301 Read-only memory area 302 Peripheral area 401 Gate 402 Drain 403 Source 501 Dielectric layer 502 Dielectric layer 503 Protective layer 601 Encoded photoresist layer 611 Window α 701 Dielectric layer 1221658 Act Wei 92114984 ____________________ 羌 ―Month—Sunday ——..— Fengmao—Schematic description 711 Deep trench 801 Photoresist layer 81 1 Opening 91 1 Contact hole Page 20 11

Claims (1)

1221658 — Case No.—92114984, Dream Sixth, Patent Application Scope 1. A method of making a read-only memory device, which can shorten product delivery, the method includes the following steps: providing a semiconductor substrate with a gold-oxide semiconductor A metal-oxide-semiconductor field-effect transistor array is disposed in a read-only memory region, and a dielectric layer covers the metal-oxide semiconductor field-effect transistor array in the read-only memory region. Wherein each of the metal oxide semiconductor field effect transistors has a gate, a source region, and a drain, and the metal oxide semiconductor field effect transistors are initially in a state of 閛 π 0NΠ; and a dielectric layer is formed on the dielectric layer. Coding photoresist layer; Lithography imaging the coded photoresist layer to form a plurality of openings, which define a metal-oxide semiconductor field that is to be written in the read-only memory area below and is switched from the open π ΟΝπ state to the closed n OFF π state The window of the effect transistor, wherein the window is located directly above the source of the metal oxide semiconductor field effect transistor to be written; Using the coded photoresist layer as an etching mask, an etching process is performed, the dielectric layer is etched through the window, and a source of a metal oxide semiconductor field effect transistor is to be written, and the source is etched downward by one. For some of the substrates, the etching depth must be lower than the junction depth of the source of the FET semiconductor field to be written, so as to form a deep trench, so as to cut off the FET field area to be written. The connection between the source and the source line of the transistor; removing the coded photoresist layer; depositing a trench filling layer on the dielectric layer and filling the deep trench Page 21 1221658 Case 92114984 _______________________ Month-Day… .—_. Amendment ______________________________________________________ VI. Patent Application Channels; Form contact plugs in the trench filling layer and the dielectric layer; for the read-only memory Bits are formed on the trench filling layer in the body region. 2. The method of making a read-only memory device as described in item 1 of the scope of patent application, wherein the window has a window longer than the width of the source. 3. The method of manufacturing a read-only memory device as described in item 1 of the scope of patent application, wherein the thickness of the dielectric layer is between 2000 and 700 angstroms. 4. A method for making a read-only memory device can shorten the product delivery time. The method includes the following steps: A semiconductor substrate is provided with a metal-oxide-semiconductor field-effect transistor array, J is disposed in a read-only memory region, and a first dielectric layer covers the read-only The metal oxide semiconductor field effect transistor array in the memory region, wherein each metal oxide semiconductor field effect transistor has a gate, a drain, and a source connected to a source line, and the metal oxide semiconductor field effect transistor The transistors are initially in the η ΟΝπ state; a bit line is formed on the first dielectric layer in the read-only memory region, wherein the bit line is covered by a second dielectric layer, and the bit line is bypassed. Page 221221658 Cold 1 92114984 — Earth month day i is —————————— 6. Application scope of patent Each side of the metal-oxide semiconductor field effect transistor should be avoided. Avoid the source ’s heavy weight. A coded photoresist layer is formed on the second dielectric layer; the lithography imaged the coded photoresist layer to form a plurality of openings, which defines the lower read-only memory area to be written and is opened by the open rose "ΟΝπ The state transition becomes the window of the metal oxide semiconductor field effect transistor in the n OFF π state; using the coded photoresist layer as an etching mask, a code etchback process is performed, and the second dielectric layer, the first A dielectric layer is used to write the source of the metal-oxide-semiconductor field-effect transistor, and a part of the substrate is etched from the source sentence, and the etching depth must be lower than that of the metal-oxide semiconductor field to be written. The junction depth of the source of the effect transistor, so as to form a deep trench, so as to cut off the connection between the source and the source line of the FET field effect transistor to be written; remove the coded photoresist layer; and Sinking of the second dielectric layer A trench filling layer is accumulated, and the deep trench is filled, wherein a protective layer is further deposited on the second dielectric layer. 5. The method for manufacturing a read-only memory device as described in item 4 of the patent application scope, wherein the The window has a window longer than the width of the source. Page 23