1221009 玖、發明說明： (一） 發明所屬之技術領域 本發明係關於在矽晶片上成長高品質鍺薄膜之方法，該 方法結合各相關技術及觀念之改良，其運用了超高真空化 學氣相磊晶（UHVCVD)與配合即時高溫退火技術等，以成長 矽鍺磊晶並獲得高品質之鍺薄膜。 本發明亦關於一種能在矽晶片上成長高品質鍺薄膜之方 法’該方法藉由將差排缺陷侷限化並利用應變界面（ s t r a i n e d i n t e r f a c e s )阻擋該缺陷之傳遞而具有大幅降低 磊晶層之厚度、減少缺陷密度，及解決了表面粗糙度問題 等優點。由於這些優點使本發明之技術具有成本低廉、方 法簡單及產能高等特性，故本發明對於製作I V族高速元件 、光學元件以及整合I I I -〗V族積體電路之技術而言，非常 具有競爭力及產業上之利用價値與潛力。 (二） 先前技術 在矽表面上直接磊晶鍺層的缺點是，兩種晶體之晶格常 數（lattice constant)約有 4.1% 之晶格失配（misniatch )，及矽與鍺因熱傳導係數不同之熱失配等問題，其使得 矽鍺界面存在極高之缺陷密度及表面粗糙度。其中極高之 缺陷密度會增加電子元件之漏電流或抵銷光學元件之效率 ;極高之表面粗糙度會造成製程中整合之困難度。 以往在矽晶片上進行鍺磊晶之方法，大致上包括了鍺薄 膜直接在矽上成長技術、在矽晶片上使先具有S i 02窗口圖 案再進行鍺成長之技術，以及利用鍺組成漸變緩衝層之技 -6 - 1221009 術。類似技術所成長之矽鍺磊晶層分別存在缺陷密度過高 -或磊晶層太厚’或表面粗糙度過大甚或龜裂等問題。 舉例而言，美國專利US 5 2 5 9 9 1 8揭示採取鍺薄膜直接成 長技術，即直接在矽晶片上進行鍺的成長，其爲了降低鍺 在矽磊晶所生之線差排問題，其採用真空氣相磊晶法，並 於矽鍺磊晶進行即時高溫退火。然而，此種技術所獲得之 鍺磊晶層其線差排密度大於1 〇6 / cm 2，超過應用價値，故並 不利於元件之製作。 另外，E.A.Fitzgerald等人在其發表之文獻” High 9 quality Ge on Si by epitaxial necking”（Applied Physics Letters，Vol.76，No.25,19 June 2000)，以及 L.C.Kimerling 等人所發表之文獻” High quality Ge epilayers on Si with low threading-dislocation densities’’（Applied Physics Letters，Vol.75, No. 19,8 Nov. 1999)中曾提議在具有 Si 〇2 圖案的矽晶片上之鍺磊晶層之成長技術，其利用S i 02所形 成之窗口以抑制線差排之傳遞，從而達到降低線差排密度 之目的，但此種方法成長出來之鍺磊晶層只有於窗口上方 Φ 的部分單晶品質較佳，對於S i 02上方的鍺層則會變成複晶 或形成晶粒間隙，故這種方法之實用性及實施結果並不佳 〇 目前主要以採用鍺組成漸變緩衝層之技術（Ge graded S i i - xG e x b u f f e r )，例如特別以 E · A · F i t z g e r a 1 d 等人登載 於美國專利US 6 2 9 1 3 2 1、6 1 07 6 5 3所揭示者，及見於其歷 年所發表之相關文獻”Novel dislocation structure and -7- 1221009 surface morphology effects in relaxed Ge/Si- -1221009 (1) Description of the invention: (1) The technical field to which the invention belongs The present invention relates to a method for growing a high-quality germanium film on a silicon wafer. This method combines the improvement of various related technologies and concepts, and uses an ultra-high vacuum chemical vapor phase Epitaxial (UHVCVD) and the use of instant high temperature annealing technology to grow silicon germanium epitaxial and obtain high quality germanium thin film. The present invention also relates to a method capable of growing a high-quality germanium film on a silicon wafer. The method has a significant reduction in the thickness of the epitaxial layer by limiting differential defects and using strained interfaces to block the transmission of the defects. Reduce the defect density, and solve the advantages of surface roughness. Because of these advantages, the technology of the present invention has the characteristics of low cost, simple method, and high productivity. Therefore, the present invention is very competitive for the technology of manufacturing Group IV high-speed components, optical components, and integrated III-V group integrated circuits. And industrial utilization price and potential. (2) The shortcomings of the prior art direct epitaxial germanium layer on the silicon surface are that the lattice constant of the two crystals has a lattice mismatch of about 4.1%, and that silicon and germanium have different thermal conductivity coefficients. Thermal mismatch and other problems, which make the SiGe interface have extremely high defect density and surface roughness. Among them, the extremely high defect density will increase the leakage current of electronic components or offset the efficiency of optical components; the extremely high surface roughness will cause integration difficulties in the manufacturing process. In the past, the methods of performing germanium epitaxy on silicon wafers generally include the technology of growing germanium films directly on silicon, the technology of first forming Si 2 window patterns on silicon wafers and then growing germanium, and the use of germanium to form a gradient buffer. Layer Skill-6-1221009. The silicon-germanium epitaxial layers grown by similar technologies have problems such as too high defect density-or the epitaxial layer is too thick 'or the surface roughness is too large or even cracked. For example, the US patent US 5 2 5 9 9 1 8 discloses the use of a germanium thin film direct growth technology, that is, the growth of germanium directly on a silicon wafer. In order to reduce the problem of line difference caused by germanium in silicon epitaxy, its The vacuum vapor phase epitaxy method is adopted, and the high temperature annealing is performed on the silicon germanium epitaxy. However, the germanium epitaxial layer obtained by this technique has a linear differential row density greater than 106 / cm2, which exceeds the application price, and is not conducive to the fabrication of the device. In addition, EAFitzgerald et al. Published "High 9 quality Ge on Si by epitaxial necking" (Applied Physics Letters, Vol. 76, No. 25, 19 June 2000), and LCKimerling et al. " High quality Ge epilayers on Si with low threading-dislocation densities '' (Applied Physics Letters, Vol. 75, No. 19, 8 Nov. 1999) has proposed a germanium epitaxial layer on a silicon wafer with a Si 〇2 pattern The growth technology uses the window formed by S i 02 to suppress the transmission of the line difference row, thereby achieving the purpose of reducing the line difference row density, but the germanium epitaxial layer grown by this method is only a part of the Φ above the window. The crystal quality is better. For the germanium layer above Si 02, it will become polycrystalline or form grain gaps, so the practicability and implementation results of this method are not good. At present, the technology of using germanium to form a gradient buffer layer ( Ge graded S ii-xG exbuffer), for example, published in the United States Patent US 6 2 9 1 3 2 1, 6 1 07 6 5 3, especially as E · A · Fitzgera 1 d and others, and found in its calendar year Published in the relevant literature "Novel dislocation structure and -7- 1221009 surface morphology effects in relaxed Ge / Si- -
Ge(graded)/Si structures”（J.Appl.Phys.81(7)，l April 1997)、’’Controlling threading dislocation densities in G e on Si using graded SiGe layers and chemical -mechanical polishing’’（Applied Physics Letters,Ge (graded) / Si structures "(J.Appl.Phys.81 (7), l April 1997)," Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical -mechanical polishing "(Applied Physics Letters,
Vo 1 . 72，No . 14，6 Apr i 1 1 9 9 8 )，亦即利用鍺含量漸變式矽 鍺磊晶法（graded SiGe)，鍺含量從零漸增至高値後再成長 爲鍺薄膜，而此方法之鍺含量變化梯度不能過大，以使鍺 與矽晶片之失配慢慢地過渡，從而達到降低線缺陷密度之 · 目的，但其結果也因此使磊晶層之厚度高達十微米以上。 此外，上述資料中亦揭示出由於磊晶層內之缺陷堆積 (pile-up)，鍺薄膜表面不可避免地形成井狀圖案，因此會 造成過大之表面粗糙度，例如相對成長於偏角605矽晶片上 之鍺薄膜，其表面粗糙度爲1 5 0 A以上；而相對成長於無偏 角矽晶片上之鍺薄膜，其表面粗糙度爲450A以上。其中， 磊晶層厚度過大及因井狀圖案而產生過大之表面粗糙度， 均會增加磊晶之製造成本及元件之製造難度。 鲁 關於井狀圖案之去除技術，上述之文獻及專利中亦提出 了以化學機械硏磨法（CMP )加以解決，但其實質上亦額外地 增加了製程之成本及複雜性。 (三）發明內容 本發明之目的在於解決先前技術中有關於矽晶片上進行 鍺磊晶所面臨之問題，包括如何降低鍺薄膜之厚度、解決 高鍺含量磊晶層過大之表面粗糙度、及降低因爲晶格失配 1221009 所形成高缺陷密度等問題。 E.A.Fitzgerald等人之相關文獻與專利所揭不之丰導體 磊晶構造，係爲一鍺含量漸變緩衝層加上鍺含量均勻磊晶 覆蓋層，差排密度低，然而總磊晶層厚度卻達十微米以上 。其揭示之製造方法爲於矽晶片上，以分子束磊晶法（MBE )或超高真空化學氣相磊晶（UHVCVD )成長含有鍺含量漸 變緩衝層爲第一層，通常以每微米1 0 %鍺含量之漸變速率 (grading rate )，漸增至50%鍺含量後，接著利用CMP 技術平坦化該層表面，此時第一層之厚度約5微米；然後 再成長第二層，鍺含量由5 0%增至75% ，接著再用CMP技 術平坦化該第二層表面，此時第二層之厚度約2 . 5微米； 第三層後之高鍺含量磊晶層，改變其磊晶條件，包括調降 成長溫度及成長氣體分壓，此時之厚度約2.5微米以上。 故根據上述方法最佳實施例所製得之樣品爲：表面無龜裂 、線差排密度約106/cm 2、表面粒狀物密度約150/cm 2、粗 糙度2 4奈米及總磊晶厚度至少1 〇微米以上之磊晶層。 本發明方法特點之一爲，首先在矽晶片上成長一層高鍺 含量之ί夕鍺嘉晶層（如0.5至0.8微米之Sio.iGeog)，由 於本層與矽晶片存在之大的晶格失配，大量之線差排會產 生於界面處與本層之內。接著成長二至三層更高鍺含量之 矽鍺磊晶層（如0.5至0.8微米之Su.G5Gea.95、S1() Q2GeQ 98 )，利用各層之間因應力所形成的應變界面，以進一步阻 擋在第一層未湮滅掉而傳遞上去之線差排，最後成長爲總 磊晶厚度僅數微米之鍺薄膜磊晶層，例如3微米以下。 -9- 1221009 在上述成長過程中，對每一單層作即時之高溫退火處理 _ ，即於6 5 0至800°C下進行15至30分鐘，以進—步提高鍺 薄i吴之早晶品質。 與E.A.Fitzgerald等人之硏究相較，本發明係採取高含 量鍺’例如S 1Q. i G e . 9爲起始第一層之矽鍺磊晶，然後成長 更商鍺含量幕晶層，例如SiowGeQ.w、或視需要增加成長 第二Si〇.(nGe().98晶晶層，其目的係利用成長具有特定厚度 之第一層，使大量之晶格失配缺陷發生在該層內，然後再 成長第二或第三層，利用各層之間形成之應變界面阻擋第 一層之向上層傳遞的線差排，故本發明顯然相對於採每微 米漸增5 %或1 0 %鍺含量的成長方式係爲截然不同之技術觀 念’若依前者之漸變速率至1 〇 〇 % ，則其矽鍺磊晶層厚度無 法降低至丨〇微米以下，而本發明總磊晶層之厚度可降低至 約3微米以下。 其次’本發明之另一特點爲，本發明之方法採用超高真 空化學氣相磊晶技術，在磊晶溫度3 5 0至6 5 0 °C範圍，以高 純度之Sit或Sl2H6、GeH4爲成長氣體、成長氣體壓力2〇 · 至1 〇 〇毫托下’進行矽鍺磊晶之成長，其不論第一磊晶層 、第二層或視需要之第三層之高鍺含量成長均維持在特定 之ί木作條件下’僅改變成長氣體中砂或鍺其中之一的比例 。低溫之成長係避免磊晶過程形成島狀成長（1 S } a n d f 0 r mi n g )因而降低磊晶品質，而壓力因素則控制著磊晶的 成長速率’惟溫度與壓力兩者條件皆宜保持穩定。然而， 習知之鍺含量漸變技術，爲達成特定之鍺含量漸變要求卻 -10- 1221009 必須小心地控制其鍺含量漸增之速率，例如爲了降低線差 -排密度，則選擇較低之鍺含量漸增速率，但卻造成總磊晶 層厚度過高；但是如果選擇較高之鍺含量漸變梯度，例如 每微米漸增1 〇%鍺含量以上，則其線差排密度會增加。低 鍺含量之漸變梯度磊晶層中上述現象尙不明顯，但是達到 高鍺含量磊晶層，例如SiQ.25GeQ.75以上時，以超高真空化 學氣相磊晶技術於初期如7 5 (TC下成長，進入高鍺含量後需 降低成長溫度，例如5 5 0 °C，及更低之分壓，例如3毫托來 緩和。然而，本發明所採用之超高真空化學氣相磊晶技術 鲁 中，並不需改變其溫度條件及明顯之壓力變化，但仍可成 長高品質之鍺磊晶。 習知技術中更包括於每一層磊晶層成長階段之平坦化步 驟，例如以化學機械硏磨（CMP )消除其表面粗糙度並續行其 後一層之漸變成長；然而本發明可省卻CMP複雜之工序， 特別係從提供具有平整表面之矽晶片，及在每一磊晶層成 長階段間之即時高溫退火著手，以達到同樣甚或更佳之效 果。本發明中具有平整表面之矽晶片之提供，先以標準淸 ® 洗步驟潔淨，再於1 0%氫氟酸溶液中浸濕，然後去離子水 淸洗，最後再於800°C下進行預烘處理以去除倶生氧化層； 至於每一磊晶層成長階段間之即時高溫退火處理，係在 7 5 0 °C下進行0 . 2 5至1小時，以進一步降低差排密度提高 單晶品質。 本發明之又一特點在於透過本發明之方法，可製作I V族 高速元件、光學元件以及整合IV族與III-IV族積體電路 -11- 1221009 之技術。i v族高速元件/光學元件，例如爲鍺金氧半場效電 ~ 日日體（Ge M0SFET)、鍺光感測器（Ge photodetector)之 IV 族材料高頻元件/光學元件；I ][丨_丨V族之應用包括，例如利 用鍺與砷化鎵晶格匹配，在鍺爲緩衝層下以成長高品質之 砷化鎵材料，其可作爲Π ]； 1 V族材料之晶片以及作爲整合 I I I - I V族與I V族之整合晶片。上述之I I I _ I v族材料其應 用包括作爲異質接面雙極電晶體（HBT)、金半電晶體（MESFET) 、高電子遷移電晶體（HEMET)、發光二極體（LED)、雷射 (Laser )等結構之磊晶晶片。 φ (四）實施方式 本發明揭示如下列之實施例，但不受該實施例所侷限。 實施例 首先，利用標準淸洗步驟潔淨矽晶片，該潔淨處理包括 將矽晶片浸置於Η2〇2 ·· H2S04比例爲1 ·· 4之溶液中約1 〇分 舍里’然後取出以去離子水（D.I. water)淸洗1〇分鐘後， 再以1 0% HF溶液浸濕約3 0秒並隨之以去離子水淸洗之， 隨後馬上送進UHVCVD系中。進行成長以前先於800t下作 鲁 預烘（pre baking )約10分鐘以去除表面氧化層，再緩降 溫度至4 0 0 °C，待溫度穩定後立即成長磊晶層。該超高真空 化學氣相磊晶系統爲具有加熱裝置之石英爐管，背景真空 可用分子幫浦抽至5χ 10·δ托（tor 1：)以下。成長使用氣體 爲S i Η 4、G e Η 4，由質流控制器（M F C )控制成長流量，其中s i Η 4 之流量保持固定，每次僅調整GeH4之供應流量，在特定之 操作條件下，包括： - 1 2 - 1221009 (1) 嘉晶溫度朝圍· 350至650°C，$父佳爲400°C ; (2) 成長氣體壓力範圍：20至100毫托，較佳爲2〇毫 托； (3 )成長氣體種類：高純度之SiH4、GeH4氣體； 其次，更進一步地成長第二或第三層之更高鍺含量之石夕 鍺蓊晶層（每層厚度至少〇·1微米以上，較佳爲0.5至〇 8 微米’ ί寸佳爲〇·8微米之SiQ ()5Ge().95、SiG Q2GeG 98)以利 用所形成之應變界面更能阻擋在第一層未湮滅掉而傳遞上 去之線差排，最後成長爲一定厚度之鍺薄膜。 屬| 上述該成長過程中，每一單層應作即時（i η - s i t u )高溫 退火，即於6 5 0至8 0 0 °C，較佳爲7 5 0 °C下進行0 . 2 5至！小 時、退火之氛圍爲氫氣、壓力範圍爲5至20毫托，以進一 步提高鍺薄膜之單晶品質。 有關第一層之鍺含量至少大於70% ，較佳爲70%至90% 之間，特佳爲90% ;其次第二層之鍺含量爲80%至98%之 間，較佳爲9 5 % ;可視需要地進行第三層磊晶之成長，選 擇之鍺含量介於第二層與純鍺之間；最外層之鍺含量爲 ® 10 0¾° 有關本發明最佳之矽鍺磊晶成長結果，其中以鍺含量爲 9 0%之Si ^ We作爲起始第一層之矽鍺磊晶，在成長溫度 400 °C、成長氣體壓力爲20毫托下，成長厚度約0.8微米 ，然後於7 5 0 °C下退火15分鐘；接著以鍺含量爲95%之 Sio.osGea.^f爲第二層之矽鍺磊晶，在成長溫度400°C、成 長氣體壓力爲2 0毫托下，成長厚度約0 . 8微米，隨即於 -13-Vo 1.72, No. 14, 6 Apr i 1 1 9 9 8), that is, using the germanium content graded silicon germanium epitaxial method (graded SiGe), the germanium content gradually increases from zero to high radon and then grows into a germanium film The gradient of the content of germanium in this method must not be too large, so that the mismatch between germanium and silicon wafers slowly transitions, so as to reduce the density of line defects. However, the thickness of the epitaxial layer is as high as ten microns. the above. In addition, the above data also revealed that due to defect-up in the epitaxial layer, a well pattern inevitably forms on the surface of the germanium thin film, which will cause excessive surface roughness, such as relatively growing at an off-angle 605 silicon. The surface roughness of the germanium film on the wafer is above 150 A; and the surface roughness of the germanium film relatively grown on the silicon wafer without declination is above 450A. Among them, the excessive thickness of the epitaxial layer and the excessive surface roughness due to the well pattern will increase the manufacturing cost of the epitaxial layer and the difficulty of manufacturing the components. Regarding the removal of well patterns, the aforementioned documents and patents also proposed chemical mechanical honing (CMP) to solve it, but it also substantially increased the cost and complexity of the process. (3) Summary of the Invention The purpose of the present invention is to solve the problems in the prior art regarding germanium epitaxy on silicon wafers, including how to reduce the thickness of the germanium thin film, solve the excessive surface roughness of the epitaxial layer with high germanium content, and Reduces problems such as high defect density due to lattice mismatch 1221009. The EAFitzgerald et al. ’S undisclosed abundance of the epitaxial structure of the conductor, which is disclosed in the patent, is a buffer layer with a germanium content gradient and an epitaxial coating layer with a uniform germanium content. The differential density is low, but the total epitaxial layer thickness is up to Above ten microns. The disclosed manufacturing method is to grow a buffer layer containing a gradient of germanium content as a first layer on a silicon wafer by molecular beam epitaxy (MBE) or ultra-high vacuum chemical vapor phase epitaxy (UHVCVD), usually at 10 per micron. The grading rate of the% germanium content is gradually increased to 50% germanium content, and then the surface of the layer is planarized by CMP technology. At this time, the thickness of the first layer is about 5 micrometers; and then the second layer is grown with the germanium content. Increase from 50% to 75%, and then use CMP technology to planarize the surface of the second layer. At this time, the thickness of the second layer is about 2.5 microns; the epitaxial layer with a high germanium content after the third layer changes its epitaxy. The crystal conditions include adjusting the growth temperature and the partial pressure of the growth gas, and the thickness at this time is about 2.5 microns or more. Therefore, the samples prepared according to the preferred embodiment of the above method are: no cracks on the surface, linear differential row density of about 106 / cm2, surface particle density of about 150 / cm2, roughness of 24nm and total lei An epitaxial layer with a crystal thickness of at least 10 microns. One of the characteristics of the method of the present invention is that firstly, a layer of high-germanium-containing helium germanium crystal (such as 0.5 to 0.8 micron Sio.iGeog) is grown on the silicon wafer. Due to the large lattice loss between this layer and the silicon wafer, Matching, a large number of line differences will be generated at the interface and within this layer. Following the growth of two to three silicon germanium epitaxial layers with higher germanium content (such as 0.5 to 0.8 micron Su.G5Gea.95, S1 () Q2GeQ 98), the strain interface formed by the stress between the layers is used to further It blocks the line differential line that is passed up without being annihilated, and finally grows into a germanium thin film epitaxial layer with a total epitaxial thickness of only a few microns, for example, less than 3 microns. -9- 1221009 During the above-mentioned growth process, an instant high temperature annealing treatment is performed on each single layer, that is, 15 to 30 minutes at 6 50 to 800 ° C, to further improve the germanium thin layer. Crystal quality. Compared with the research of EAFitzgerald et al., The present invention adopts a high content of germanium, such as S 1Q. I G e. 9 as the first layer of silicon germanium epitaxy, and then grows a more germanium content curtain crystal layer. For example, SiowGeQ.w, or if necessary, grow a second Si (.nGe (). 98 crystal layer), the purpose of which is to grow a first layer with a specific thickness, so that a large number of lattice mismatch defects occur in this layer. And then grow the second or third layer, and use the strain interface formed between each layer to block the line difference transmission from the first layer to the upper layer, so the present invention obviously increases gradually by 5% or 10% relative to the thickness of each micrometer. The growth method of the germanium content is a completely different technical concept. If the gradient rate of the former is 100%, the thickness of the silicon germanium epitaxial layer cannot be reduced to less than 10 microns, and the thickness of the total epitaxial layer of the present invention It can be reduced to less than about 3 microns. Secondly, another feature of the present invention is that the method of the present invention uses ultra-high vacuum chemical vapor phase epitaxy technology, in the range of epitaxial temperature of 350 to 650 ° C, to a high The purity of Sit or Sl2H6, GeH4 is the growth gas, and the pressure of the growth gas is 20 to Under 100 millitorr, 'growth of silicon germanium epitaxy, its high germanium content growth regardless of the first epitaxial layer, the second layer, or the third layer as required will be maintained under specific wood conditions' only Change the proportion of sand or germanium in the growth gas. Low temperature growth avoids the formation of island growth (1 S} and f 0 r mi ng) during the epitaxial process and thus reduces the quality of the epitaxial process, while the pressure factor controls the epitaxial process. "Growth rate", but both temperature and pressure conditions should be stable. However, the conventional germanium content grading technology, in order to achieve specific requirements for germanium content grading, -10- 1221009 must carefully control the rate of increasing germanium content, such as In order to reduce the line-drain density, a lower germanium content increasing rate is selected, but the total epitaxial layer thickness is too high; but if a higher germanium content gradient is selected, such as a 10% increase per micron, Above the germanium content, the linear differential row density will increase. The above phenomenon is not obvious in the graded gradient epitaxial layer with low germanium content, but the epitaxial layer with high germanium content is reached, such as SiQ.25GeQ.75 or higher Vacuum Vapor phase epitaxy technology grows at an initial stage such as 75 ° C. After entering high germanium content, the growth temperature needs to be reduced, such as 50 ° C, and a lower partial pressure, such as 3 millitorr to ease. However, the present invention The adopted ultra-high vacuum chemical vapor phase epitaxial technology Luzhong does not need to change its temperature conditions and obvious pressure changes, but it can still grow high-quality germanium epitaxy. The conventional technology also includes each layer of epitaxy. The planarization step of the layer growth stage, for example, uses chemical mechanical honing (CMP) to eliminate its surface roughness and continue the gradual growth of the subsequent layer; however, the present invention can omit the complicated process of CMP, especially from providing a flat surface Silicon wafers, and real-time high-temperature annealing during the growth of each epitaxial layer are initiated to achieve the same or better results. The silicon wafer with a flat surface provided in the present invention is cleaned by a standard 淸 ® washing step, then dipped in a 10% hydrofluoric acid solution, then rinsed with deionized water, and finally pre-treated at 800 ° C. Baking treatment to remove the epitaxial oxide layer; As for the instant high temperature annealing treatment between the growth stages of each epitaxial layer, it is performed at 750 ° C for 0.2 to 1 hour to further reduce the differential density and increase the single crystal. quality. Another feature of the present invention is that through the method of the present invention, it is possible to fabricate Group I V high-speed components, optical components, and technologies for integrating Group IV and III-IV integrated circuits -11-1221009. Group iv high-speed elements / optical elements, such as germanium-gold-oxygen half-field-effect electric power ~ Group IV material high-frequency elements / optical elements of Ge photodetector (Ge photodetector); I] [丨 _丨 V applications include, for example, the use of germanium and gallium arsenide lattice matching, to grow high-quality gallium arsenide materials under germanium as a buffer layer, which can be used as Π]; 1 V group material wafers and as integrated III -Group IV and IV integrated chips. The applications of the above-mentioned III_I v materials include as heterojunction bipolar transistors (HBT), gold semi-transistors (MESFET), high-electron migration transistors (HEMET), light-emitting diodes (LEDs), lasers (Laser) and other structures of epitaxial wafers. (4) Embodiments The present invention discloses the following examples, but is not limited by the examples. Example First, the silicon wafer is cleaned using a standard cleaning step. The cleaning process includes immersing the silicon wafer in a solution of Η202 ·· H2S04 with a ratio of 1 ·· 4 and then removing the wafer for deionization. After DI water was rinsed for 10 minutes, it was soaked with 10% HF solution for about 30 seconds and then rinsed with deionized water, and then immediately sent to the UHVCVD system. Prior to growth, pre-bake at 800t for about 10 minutes to remove the surface oxide layer, and then slowly lower the temperature to 400 ° C. After the temperature stabilizes, grow the epitaxial layer immediately. The ultra-high vacuum chemical vapor phase epitaxy system is a quartz furnace tube with a heating device. The background vacuum can be pumped down to 5 × 10 · δ Torr (tor 1 :) with a molecular pump. The gas used for growth is Si Η 4, Ge Η 4, and the growth flow is controlled by a mass flow controller (MFC), where the flow of si Η 4 is kept constant, and only the supply flow of GeH4 is adjusted each time, under specific operating conditions Including:-1 2-1221009 (1) Jiajing temperature Chaowei · 350 to 650 ° C, $ 400 is 400 ° C; (2) Growth gas pressure range: 20 to 100 millitorr, preferably 2〇 MTorr; (3) type of growth gas: high-purity SiH4, GeH4 gas; secondly, further grow the second or third layer of higher germanium-containing stone germanium ytterbium crystal layer (each layer thickness is at least 0.1 Above micron, preferably 0.5 to 08 micron ', SiQ () 5Ge (). 95, SiG Q2GeG 98), which is preferably 0.8 micron, to make use of the formed strain interface to prevent the first layer from being annihilated Lines that are dropped and passed up, and finally grow into a germanium film of a certain thickness. Attribution | During this growth process, each single layer should be annealed (i η-situ) at high temperature, that is, at 0 5 0 to 8 0 ° C, preferably 7 5 0 ° C. 2 5 to! For one hour, the annealing atmosphere is hydrogen and the pressure ranges from 5 to 20 mTorr to further improve the single crystal quality of the germanium film. The germanium content of the first layer is at least greater than 70%, preferably between 70% and 90%, particularly preferably 90%; secondly, the germanium content of the second layer is between 80% and 98%, preferably 9 5 %; The third layer of epitaxial growth can be performed as required, and the selected germanium content is between the second layer and pure germanium; the outermost layer of germanium content is ® 10 0¾ ° The best silicon germanium epitaxial growth related to the present invention As a result, the silicon germanium epitaxial crystal with Si ^ We with a germanium content of 90% as the initial layer was grown at a growth temperature of 400 ° C and a growth gas pressure of 20 mTorr to a thickness of about 0.8 microns, and then Anneal at 750 ° C for 15 minutes; then use Siio.osGea. ^ F with 95% germanium as the second layer of silicon germanium epitaxy at a growth temperature of 400 ° C and a growth gas pressure of 20 millitorr , The growth thickness is about 0.8 microns, and then -13-