TWI220796B - Thin film transistor array panel and method for making the same - Google Patents

Abstract

A thin film transistor array panel comprises thin film transistors; a color filter array layer formed over the thin film transistors and exposes a predetermined region for forming contact; a overcoat layer formed over the color filter array layer covering the thin film transistors; pixel electrodes formed on the overcoat layer and located corresponding to the thin film transistors; and contacts formed in the overcoat layer in the predetermined region, wherein the pixel electrodes and thin film transistors are electrically connected together through the contacts. Since the contacts are formed in the overcoat layer but not in the color filter array layer, the contact dimension can be reduced.

Description

1220796 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a thin film transistor array substrate for a liquid crystal display (LCD) and a method for manufacturing the same, and more particularly, to a method for filtering a color filter. Optical array layer made of thin film transistor array (COA) substrate and manufacturing method thereof 0 [Previous technology] Liquid crystal display has high image quality, small size, light weight, low voltage driving, low power consumption and It has a wide range of applications, so it has been widely used in consumer electronics or computer products such as small and medium-sized portable TVs, mobile phones, camcorders, notebook computers, desktop displays, and projection TVs. And it gradually replaced the cathode ray tube (Cathode Ray Tube, CRT) and became the mainstream of the display. One way to do this on a Filter display today is to connect each thin. Connected to cover the contact window on the color film transistor array layer (Color is in the liquid crystal panel body, its linear array layer, the array layer is exposed to thin color light and formed by the color filter without array layer cracking In thin film electromyography, τ — on Array 'C0A) technology has also been widely used. This type of thin film transistor array substrate using COA technology first forms several thin film transistor film systems on a transparent substrate with corresponding scanning wirings and data to form a color filter array above the transparent substrate? ί! ί m: After that, a plurality of contact windows are formed in the patterned color filter color filter array layer, and then the regions. After that, the color electrode is t-connected to the corresponding t-crystal t crystal through the above-mentioned opening 1220796 V. Description of the invention (2). In the thin film transistor array substrate described above, a contact window opening for electrically connecting the day electrode and the thin film transistor is formed in the color filter array layer. However, due to the limitation of the process resolution of the color filter array layer, the size of the contact window openings formed in the color filter array layer will be quite large. As a result, the development of high pixel density panels will be limited. In addition, based on the consideration of the high aperture ratio of the LCD panel, the day electrode is usually defined as being very close to the data wiring, or even covering some data wiring. However, in order to avoid interference or even short circuit between the data wiring and the day electrode, the above purpose is usually achieved by increasing the thickness of the color filter array layer. However, the increase in the thickness of the color filter array layer will affect the transmittance of the liquid crystal display panel. [Abstract] Therefore, the object of the present invention is to provide a thin film transistor array substrate and a manufacturing method thereof. To solve the problem that the contact window formed in the color filter array layer is too large. Another object of the present invention is to provide a thin-film transistor array substrate and a manufacturing method thereof, in order to solve the conventional method in order to avoid interference or even short circuit between the data wiring and the day electrode, and increase the thickness of the color filter array layer. As a result, the transmittance of the liquid crystal display panel is reduced. The invention provides a thin-film transistor array substrate, which includes a plurality of thin-film transistors, a color filter array layer, a cover layer, and a plurality of day electrode.

9679twf.ptd Page 7 1220796 V. Description of the invention (3) and several contact windows. The thin film transistor system is disposed on a substrate, and the color filter array layer is formed on the thin film transistor, and one of the thin film transistors is exposed to form a contact window region. In addition, the cover layer covers the color filter array layer and covers the thin film transistor. The day element is arranged on the cover layer and corresponds to the thin film transistor configuration. In addition, the contact window is arranged in a cover layer in a region where the contact window is to be formed so that the day electrode and the corresponding thin film transistor are electrically connected. The invention proposes a method for manufacturing a thin film transistor array substrate. This method firstly forms a plurality of thin film transistors on a substrate. Next, a color filter array layer is formed over the thin film transistor, wherein the color filter array layer exposes one of the corresponding thin film transistors to form a contact window area. After that, a cover layer is formed on the color filter array layer and covers the thin film transistor. Subsequently, a plurality of contact window openings are formed in the cover layer intended to form the contact window region, exposing a part of the thin film transistor. Then, a plurality of pixel electrodes are formed on the cover layer, and the formed pixel electrodes are electrically connected to the corresponding thin, film transistors through the contact window openings described above. In the present invention, the contact window opening for electrically connecting the thin film transistor and the day element electrode is formed in the cover layer, instead of being formed in the color filter array layer, so that the size of the contact window opening formed can be Zoom out. In the present invention, since the color filter array layer is further covered with a cover layer, and this cover layer has a lower dielectric constant and a planarization effect, interference between the day element electrode and the data wiring can be avoided or even Short circuit. In addition, since the cover layer formed on the color filter array layer has

9679twf.ptd Page 8 1220796 V. Description of the invention (4) Excellent transmittance, so the method of the present invention can improve the aperture ratio and transmittance of the liquid crystal display surface. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the attached, b is described in detail as follows: Ｍ 八 作 平 [Embodiment] FIG. 1 is a schematic top view of a film transistor array substrate according to a preferred embodiment of the present invention. FIG. 2 is a green view showing a cross section taken from I-I ′ in FIG. 2. schematic diagram. Please refer to FIG. 1 ′ and FIG. 7 ^^ at the same time. First, a substrate 3 2 0 is provided. Next, a plurality of film transistors 240 are formed on the substrate 3 2 0. Among them, each thin film transistor 240 includes electrical connection with a "wiring (not shown)" and a data wiring 1 10, among which-a field data wiring 1 10 and each scanning wiring are enclosed. A day prime region '. In a preferred embodiment, the above-mentioned thin film transistor 24 is, for example, a thin film transistor with a gate on top (t 0 p g a t e). However, in the present invention, the form of the thin film transistor is limited, so that a 'gate bottom type, a bottom gate thin film transistor, or other forms of thin film transistors can be applied to the present invention. However, in order to explain the invention in detail, the gate-top-type (t 0 p g a t e) thin-film transistor is taken as an example to illustrate that the invention is generally formed before the gate-top-type thin-film transistor 2 4 0 is formed. A buffer layer 310 is formed on the surface of the substrate 3 2 0, and then an amorphous silicon layer (not shown) is formed on the substrate, and the amorphous silicon layer is converted by laser tempering ^ 3 1 0 Into a polycrystalline silicon layer 2 9 0. Thereafter, an ion implantation process is performed to form a source doped region in the polycrystalline silicon layer 290 (not invisible from the Lu-shan step) and

Ϊ220796 V. Description of the invention (5) The state between the electrode doped region (not shown, the channel region (not shown) and the source doped region and the drain doped region may be N-type low temperature.) This thin film transistor 240 is doped according to its doped /, transistor or complementary θ9, / x thin film transistor, P-type low temperature polycrystalline silicon, and then a gate insulating iron R temperature polycrystalline silicon thin film transistor is formed. Layer 2 9 0. Ran "Moxibustion, a polycrystalline layer 22 was formed by covering the polycrystals formed in Zhalai Gong 00 ', and a gate electrode 3 30 was formed on this layer 300. After that, a patterned dielectric layer was patterned. The electrical layer 2 ^ covers the gate electrode 3 3 0 and the gate insulating layer 3 0. This electrode doped region and the drain electrode are doped to form an opening (not shown), exposing the source electrode source metal layer 3 5 0. After that, the source metal layer 3 50 is electrically and 4 ^ drain metal layer 2 3 0 on the surface of the dielectric layer 2 2 0, and at the same time, it is defined that it penetrates into the opening formed above ^ Information / \ wiring 1 1 〇. At the same time, more than 280, so that the source ^ metal layer, and the contact window 34, 34 0s metal layer 35 and the drain metal layer 23 are formed. After forming a thin-film transistor 2 4 00 by contacting the source-doped region and the drain-doped ° port of the silicon layer 290 through the contact window, please continue to refer to FIG. 1 and In FIG. 2, a color filter array layer 1 2 0, 1 3 0, 1 4 0 is formed above the substrate 3 2 0. For example, the color filter array layer includes a red color filter layer, a green color filter layer, and a blue color filter. The light layer (R, G, B) is composed, and the arrangement of R, G, B can be mosaic, triangle, stripe or four-pixel RGGB configuration type, etc., and the color filter array layer 120, 130, 140 The thickness is, for example, less than 1.5 micrometers. In addition, a mesh-like gap (S pace) between r, G, and B further includes a black matrix layer (B 1 ack M atri X, B Μ) (not shown). (Illustrated). In particular, the color filter array layers 1 2 0, 1 3 0, and 1 4 0 formed by the present invention expose corresponding thin film electrodes.

9679twf.ptd

1220796 V. Description of the invention (6), one of the bodies 2 4 is intended to form a contact window area 4 0 0. In a preferred embodiment 榀 a, the contact window area 4 0 0 is determined to be a region corresponding to the drain connection f ′ 0 of the thin film transistor 240. In another preferred embodiment, the predetermined shape 40 is 2, ^ self-region can also correspond to the area where the entire thin film transistor is located, as shown in Figure 3, or even area 404 as shown in Figure 4. Mode, broad: color chirped array layer 1 2 0 , 1 3 0, 1 4 0 There are several configurations 1 3 0, 12 2 As shown in Figures 3 and 4 'Color filter array layer 1 2 0, in the prime area = expose the entire thin film transistor 24 0 It comes out and covers the color filter: 臈 U 臈 transistor 240. In addition, the color and the second picture, the arrangement of 12 Gan, 130, 140 can also be exposed as shown in Figure 1. In the future, only the drain metal layer 230 of the thin film transistor 24 is exposed. In the 4 denier region, the capping layer other than the electrodeless metal layer 230 is shown in FIG. 2 Formed over the substrate 32g-a transistor 24o. The material of the straight U light array layer 120, 130, 1440 and a thin film or an inorganic dielectric material cover layer 210 may be Polymer material transfer coating method or 1 = limp: the method of forming the cover layer 210 is, for example, using a polymer material to spin L; using formula 2. It is especially worth mentioning: material, its better card d Inorganic dielectric material is used as the cover] 2 layers 210, whose dielectric-is .5 micrometers. Here the dielectric constant is low, and the color filter array layers 120, 130, 14 < n 140 are high. The transmittance is higher than Color filter array layer 120, U〇1220796 V. Description of the invention (7) After forming a contact window opening 150 in the cover layer 210, the drain metal layer 230 of the thin film transistor 240 is exposed. Continued, on the cover layer The day element electrodes 160, 170, and 180 are formed on 210, and the day element electrodes 160, 170, and 180 are electrically connected to the corresponding thin film transistor 2 4 0 through the contact window opening 1 50 and the electrical properties are 2 3 0. And the material of the day element electrodes 160, 170, and 180 is, for example, indium tin oxide (IT 0). The thin film transistor array substrate of the present invention includes a plurality of thin film transistors 2 40 and a color Filter array layer 1 2 0, 1 3 0, 1 40, a cover layer 2 1 0, several daylight electrodes 160, 170, 180, and several contact windows 1 In the 50I, the thin film transistor 240 is arranged on a substrate 3200, and each thin film transistor 240 is electrically connected to the corresponding scanning cable and data wiring 1110. In a comparison In a preferred embodiment, the thin film transistor 240 is, for example, a gate-type thin film transistor or a gate-bottom thin film transistor. The color filter array layer 1 2 0, 1 3 0, 1 4 0 is formed. On the thin film transistor 240, and one of the corresponding thin film transistors 240 is intended to form a% contact window area 400 or 402 or 404. Among them, the composition of the color filter array layers 120, 130, and 140 and the arrangement manners thereof have been described in the previous manufacturing method ', and are not repeated here. In addition, the "covering layer 2 10" covers the color filter field array layers 120, 130, and 140, and covers the thin film transistor 24. The book electrodes 160, 170, and 180 are disposed on the cover layer 210, and are disposed corresponding to the thin film 240 and the crystal 240. In addition, the 'contact window 150 is arranged in a cover layer 210 which is intended to form a contact * area 400 or 402 or 404, so that the pixel electrode 160, $ 170, 180 and the corresponding thin film transistor 24 0 (drain electrode gold ^ Layer 23) is electrically connected. Tian,

1220796 V. Description of the invention (8) The cover layer 2 1 0 formed on the color filter array layer 1 2 0, 1 3 0, 1 4 0 according to the present invention has a flattened color filter array layer 1 2 0, 1 30, 14 0, and the dielectric constant of the cover layer 2 1 0 is lower than that of the color filter array layers 120, 130, 140, so it is formed in the cover layer 210 and the color filter array layers 120, 130, 140 The daytime electrodes 160, 170, 180 on the upper layer and the data wiring 110 on the lower layer are less likely to cause interference or even short circuit with each other. In addition, since the transmittance of the cover layer 210 is higher than that of the color filter array layers 120, 130, and 140, the method of the present invention can improve the opening rate and transmittance of the liquid crystal display panel. In addition, the present invention is used to make the contact window openings 1 50 which are electrically connected to the day electrode 16 0, 17 0, 1 80 and the drain metal layer 2 3 0 in the cover layer 2 1 0, and It is not formed in the color filter array layers 1 2 0, 1 3 0, 1 4 0. Since the resolution of the process for forming the openings in the cover layer 2 10 is higher than that of the process for forming the openings in the color filter array layers 1 2 0, 1 3 0, and 1 40, the resolution of the process in the cover layer 210 is higher. The size of the formed contact window opening 150 can be reduced, which will facilitate the development of high pixel density panels. To sum up, the present invention has the following advantages: 1. In the present invention, the contact window opening for electrically connecting the thin film transistor and the day electrode is formed in the cover layer, not the color filter In the array layer, the size of the opening of the contact window can be reduced. In the present invention, since the color filter array layer is further covered with a cover layer, the cover layer has a lower dielectric constant and The flattening effect can avoid interference between the daylight electrode and the data wiring, even 1 1 1 mm shorter

9679twf.ptd Page 13 1220796 V. Description of Invention (9) Road. 3. Since the cover layer formed on the color filter array layer has better transmittance, the method of the present invention can improve the aperture ratio and transmittance of the liquid crystal display panel. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

9679twf.ptd Page 14 1220796 Brief Description of Drawings Figure 1 is a schematic top view of a thin film transistor array substrate according to a preferred embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken from I-Γ in Fig. 1. Fig. 3 is a top view of a thin film transistor array substrate according to another preferred embodiment of the present invention. FIG. 4 is a schematic top view of a thin film transistor array substrate according to another preferred embodiment of the present invention. [Illustration of Graphical Symbols] 1 2 0, 1 3 0, 1 4 0; color filter array layer 1 50: contact windows 160, 170, 180: day element electrodes 1 1 0: data wiring 2 4 0: thin film electrical Crystals 400, 402, and 404: contact window regions 3 2 0: substrate 3 1 0: buffer layer, 3 0 0: gate insulating layer 2 2 0: dielectric layer 2 9 0 • polycrystalline silicon layers 340, 280: Contact window 3 3 0: Gate 210: Cover layer

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Claims (1)

1220796 VI. Scope of patent application 1. A thin film transistor array substrate, comprising: a plurality of thin film transistors arranged on a substrate; a color filter array layer formed on the thin film transistors, and exposing corresponding to the thin film transistors One of the thin-film transistors is intended to form a contact window region; a cover layer covering the color filter array layer and covering the thin-film transistors; a plurality of daylight electrodes arranged on the cover layer, and The thin film transistors are arranged correspondingly; and a plurality of contact windows are arranged in the covering layer in the region where the contact windows are to be formed, so that the day electrodes and the corresponding thin film transistors are electrically connected. 2. The thin film transistor array substrate according to item 1 of the scope of the patent application, wherein the predetermined contact window area is a partial area corresponding to the thin film transistors. 3. The thin film transistor array substrate according to item 1 of the scope of patent application, wherein the predetermined contact window area is a region corresponding to the location of the thin film transistors. 4. The thin film transistor array substrate according to item 1 of the scope of the patent application, wherein the dielectric constant of the cover layer is lower than the dielectric constant of the color filter array layer. 5. The thin film transistor array substrate according to item 1 of the scope of the patent application, wherein the transmittance of the cover layer is higher than that of the color filter array layer. 6. The thin film transistor array substrate as described in the first patent application 9679twf.ptd Page 16 1220796 The six-layer cover covers the material and the material is divided into one high-quality material. The cover covers the fan Zhongli, please be in the middle, Mi Wei ο 11 to Mi 2 ο, 1 is the first For the cover of the material layer of the material fence, please apply for the material such as the middle 7. The degree of the material of the thick plate base matrix crystal film ^ H None of the media is to cover the layer of 8 meters thick Micro 5 to meter 11 ο In the medium system, the matrix crystal ^ 00 The thin film described in item IX. Fan Li specially invited the Chinese, such as the method of the method of the low-rise system of the thick-layer array array light The crystal thin film color of this type is one of its 9 plate meters, which includes the array array crystals that define its pre-layer; the photoelectric volume film is thin, the color is thin, and some of the films are thin. The upper body is exposed to form a crystal-burst electrical system. The upper layer of the laminate is a thin array of bases. The light is covered in the color layer. The upper layer of light is formed. • The color window in the color range of the color range should be connected. Cover and connect the number The area of the window is formed by contact. • The solid pre-crystallizes the electricity in the thin film and the daytime. • In the domain, it is distinguished by the number of thin films in the daytime. The exposed cover layer is formed, and the opening should be on the window touchability & > > & ^ B bulk crystal ^ β The film should be thin and should be handled, and D should be opened to touch the window. This is a series of Fan Li specially asked Zhongru layer to cover the board made by its method. The board is a base or array of matrix material. Electric alpha method ": Fangji 11 made the base cloth coating array rotation spin crystal-electric film encapsulation method described in the layered items covered in the forming Fan Lizhuan 9679twf.ptd Page 17 1220796 6. Application for Patent Scope Law. 12. The method for manufacturing a thin film transistor array substrate according to item 9 of the scope of the patent application, wherein the material of the cover layer is a polymer material, and the thickness of the cover layer is between 0.2 m and 10 Microns. 1 3. The method for manufacturing a thin film transistor array substrate according to item 9 of the scope of the patent application, wherein the material of the cover layer is an inorganic dielectric material, and the thickness of the cover layer is between 0.1 m and 5 microns . 1 4. The method for manufacturing a thin film transistor array substrate according to item 9 of the scope of patent application, wherein the thickness of the color filter array layer is less than 1.5 micrometers. 9679twf.ptd Page 18