TWI220539B - Manufacturing method of regularly arranged nanometer dot array - Google Patents
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1220539 五、發明說明(l) 發明所屬之技術領域·· 本發明係有關於奈米點陣列的製作方法 =-種利用陽極氧化處理技術製作規則排:寺別是有關 米點陣列的方法。 |屬氧化物奈 先前技術: 最常被採用於製作半導體奈米點的方式 Stranski - Krastanow 成長模式(s —K m〇de)。此制 選用適當的基材進行異質磊晶成長,當磊晶=乍方式需 有較大的晶格常數差異且沉積超過一定厚度後〃 2基材具 無法承受應變,磊晶材料將會自發性地自纟聚集由於晶格 (sel f-assembly)形成奈米尺寸之量子點結構以降 能量。然而,以此方式製作之量子點的空間排列-正 寸分佈不均。此外,Stranski—Krastan〇w成長模式⑺K «lode)僅適用於少數高晶格應變的異質磊晶系統,例如,1220539 V. Description of the invention (l) The technical field to which the invention belongs ... The present invention relates to a method for making a nano-dot array =-a method for making a regular row by using anodizing technology: a temple is a method related to a rice-dot array. | Oxide Nanotechnology Prior technology: The most commonly used method for making semiconductor nano- dots Stranski-Krastanow growth mode (s —K m〇de). This system selects an appropriate substrate for heteroepitaxial growth. When the epitaxial = first method requires a large difference in lattice constants and the deposition exceeds a certain thickness 〃 2 the substrate can not withstand the strain, the epitaxial material will Ground self-aggregation forms nanometer-sized quantum dot structures due to sel f-assembly to reduce energy. However, the spatial arrangement-in-squareness distribution of quantum dots made in this way is uneven. In addition, Stranski-Krastan〇w growth mode ⑺K «lode) is only applicable to a few heteroepitaxial systems with high lattice strain, for example,
InAs QDs/GaAs sub· 、InAs QDs/InP sub·以及Ge QDs/Si sub·等系統。至今仍未有一高效率且能有效控制量子點之 成長方式’因此限制了量子點元件的應用性。 為了有效地控制量子點的成長,具有規則排列之奈米 孔洞的1%極氧化|呂(anodic aluminum oxide,ΑΑ0)經常被 使用做為 >儿積^:子點材料時的模板(^ e m p 1 a ^ e )。若將純I呂 置於電解液中,加以適當電壓進行陽極氧化即可獲得多孔 性(porous)的陽極氧化鋁。孔洞的形成機制主要為電場輔 助溶解氧化鋁與氧化鋁生成的競爭反應,當氧化鋁的生成InAs QDs / GaAs sub ·, InAs QDs / InP sub ·, and Ge QDs / Si sub · and other systems. Until now, there has not been a high-efficiency and effective way to control the growth of quantum dots', thus limiting the applicability of quantum dot elements. In order to effectively control the growth of quantum dots, 1% polar oxidation of nano-holes with regular arrangement | Lu (anodic aluminum oxide (ΑΑ0) is often used as a template for child dots ^: dot material (^ emp 1 a ^ e). Porous anodized alumina can be obtained by placing pure ions in an electrolyte and applying an appropriate voltage for anodization. The formation mechanism of the pores is mainly the electric field assisting the competitive reaction between dissolved alumina and alumina production.
1220539 五、發明說明(2) 下發展的直通奈米孔 ’孔洞的排列方式為 ’而孔洞深度最高可 比丄因此具有極大的 ,氧化的條件可以精 ^化叙非常適合做為 皆使用鋁箔製作陽極 紹箔上剝離 於奈米孔洞内選區沉 製程無法配合,為解 基材上製作陽極氧化 與浴解的速率達到平銜拉 、n甘, J十衡時,即形成向 洞?、孔洞直徑由十至數百奈米不等 六邊形(heXag0nal )的最密堆積排列 達數百微米,與陽極氧化的時間成正 深寬比(aspect ratio)。藉由改變 確地控制奈米孔洞的尺寸,因此陽極 控制量子點成長的模板。然而,一般 氧化銘,所得之陽極氧化鋁必須先由 (lift-off),將其吸附在基底上,再 積里子點。此法製程效―率低且盘現有 決此問題,本發明提出以鋁膜直接於 鋁,使其相容於目前半導體薄膜製程 發明内容: 有鑑於此,本發明的目的在於提供一種奈米點陣列的 製作方法,藉調整陽極氡化製程條件以控制陽極氧化紹孔 洞之尺寸,進而控制奈米點尺寸,以達成在任何基底上製 作規則排列之奈米點陣列。 根據上述目的’本發明提供一種規則排列奈米點陣列 的製作方法’包括下列步驟:提供一基底;形成一導電層 於上述基底上;形成一金屬層於導電層上;進行陽極氧化 處理步驟,於表面將金屬層氧化形成一奈米級孔洞陣列之 氧化物模板;持續進行陽極氡化處理步驟,並透過奈米級 孔洞陣列之氧化物模板’將導電層表面氧化形成與奈米級1220539 V. Description of the invention (2) Straight nano-holes developed under '2 The arrangement of pores is' and the depth of the pores is the highest comparable. Therefore, it has great oxidization conditions. The oxidation conditions can be refined. It is very suitable to use aluminum foil for anode The process of peeling the foil from the nano-holes in the selective process of the sink cannot cooperate. The rate of anodic oxidation and bathing on the substrate is equal to the pull rate, n, and when J is ten, a hole is formed? The diameter of the pores ranges from ten to several hundred nanometers. The densest packing arrangement of hexagons (heXag0nal) reaches several hundred microns, and it has a positive aspect ratio with the anodizing time. By changing the size of the nanopores, the anode controls the template for quantum dot growth. However, in general, the anodized aluminum must be lift-off, adsorbed on the substrate, and then accumulate neutrons. The efficiency of this method is low, and the current problem is solved. The present invention proposes to use aluminum film directly on aluminum to make it compatible with the current semiconductor thin film manufacturing process. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to provide a nanometer dot. The manufacturing method of the array is to adjust the anode anodizing process conditions to control the size of the anodized pores, and then control the size of the nano dots, so as to achieve the production of regularly arranged nano dot arrays on any substrate. According to the above purpose, the present invention provides a method for manufacturing a regularly arranged nano-dot array, which includes the following steps: providing a substrate; forming a conductive layer on the substrate; forming a metal layer on the conductive layer; performing an anodizing step, The metal layer is oxidized on the surface to form a nano-scale hole array oxide template; the anode anodizing step is continuously performed, and the conductive layer surface is oxidized to form a nano-scale through the nano-scale hole array oxide template
1220539 五、發明說明(3)1220539 V. Description of the invention (3)
物奈米點陣列1及移除奈 根據上述目的,本發明亦 列的製作方法,包括下列步驟 於上述基底上;形成一導電層 導電層上;進行陽極氧化處理 形成一奈米級孔洞陣列之氧化 處理步驟,並透過奈米級孔洞 層表面氧化形成與奈米級孔洞 奈米點陣列;移除奈米級孔洞 未氧化之部分,留下金屬氧化 氧化物奈米點陣列為罩幕,蝕 點陣列。 提供一種規則排列奈米點陣 :提供一基底;形成一薄膜 於薄膜上;形成 '一金屬層於 步驟,於表面將金屬層氧化 物模板;持續進行陽極氧化 陣列之氧化物模板,將導電 陣列相對應之一金屬氧化物 陣列之氧化物模板及導電層 物奈米點陣列;以及以金屬 刻薄膜使薄膜轉換成一奈米Nanometer dot array 1 and nanometer removal According to the above purpose, the manufacturing method of the present invention includes the following steps on the above substrate; forming a conductive layer on the conductive layer; and performing anodizing treatment to form a nanometer-level hole array. Oxidation treatment step, through the surface oxidation of the nano-level hole layer to form nano-point hole nano-point array; remove the non-oxidized part of the nano-level holes, leaving the metal oxide oxide nano-point array as a mask, etch Point array. Provide a regularly arranged nano-matrix: provide a substrate; form a thin film on the thin film; form a metal layer in the step, and place a metal layer oxide template on the surface; continue to perform an anodic oxide array oxide template, and conduct a conductive array Corresponding oxide template and conductive layer nanometer dot array of a metal oxide array; and a metal etched film to convert the film to a nanometer
以下配合圖式以及較佳實施例,以更詳細地說 明。 實施方式: 實施例一 奈米點陣列可廣泛應用光電元件、氣體感測器、光觸 媒、^光元件、磁記錄媒體以及太陽能電池等。本發明之 第一實施方式係以規則排列氧化鈦奈米點陣列為例,來說 明本發明,但並非限制本發明。第卜4圖係顯示本發明第 一實施例之規則排列氧化鈦奈米點陣列的製程剖面圖。 凊參閱第1圖,提供一基底丨〇 〇,例如矽基底、玻璃基In the following, the drawings and preferred embodiments are described in more detail. Embodiments: Embodiment 1 The nano-dot array can be widely used in photovoltaic elements, gas sensors, photocatalysts, optical elements, magnetic recording media, and solar cells. The first embodiment of the present invention uses the regular arrangement of titanium oxide nano-dot arrays as an example to illustrate the present invention, but does not limit the present invention. FIG. 4 is a cross-sectional view showing the process of the regularly arranged titanium oxide nano-dot array according to the first embodiment of the present invention.凊 Refer to Figure 1 to provide a substrate 丨 〇 〇, such as silicon substrate, glass substrate
1220539 五、發明說明(5) ' 鉻酸1· 5 wt%,溫度60 °C,時間2小時。 根據本發明之較佳實施方式,將基底1 0 0置於電解液 中’例如草酸(〇· 3〜0· 4M)或硫酸(1· 2M),加以適當電壓, 如4 0伏(V ),在室溫下進行陽極氧化反應,即可獲得多孔 性(porous)的陽極氧化鋁,直徑由20〜60奈米。孔洞的形 成機制主要為電場辅助溶解氧化鋁與氧化鋁生成的競爭反 應’當氧化鋁的生成與溶解的速率達到平衡時,即形成向 下發展的直通奈米孔洞。其孔洞的排列方式為六邊形 (hexagonal)的最密堆積排列,而孔洞深度最高可達數百 微米與陽極氧化的時間成正比,因此具有極大的深寬比 (aspect ratio) 〇 第5圖係顯示陽極氧化反應時電流密度與時間(j — T )的 關係圖。A點係指陽極氧化銘(a n 〇 d ^ c a 1 u m i n u m ο X i d e, A AO)生成時之陽極電流密度。當陽極氧化鋁孔洞丨4 2發展 至金屬紹層1 4 0與氮化鈦1 2 0介面時,陽極電流密度開始急 遽下降(B點)’接著氮化鈦1 2 0之陽極氧化反應開始進行(◦ 點)’形成規則排列氧化鈦奈米點陣列丨2 2,最後陽極電流 也度降至最低值代表陽極氧化反應結束(D點)。 規則排列氧化鈦奈米點陣列丨2 2之尺寸與陽極氧化鋁 (^nodic aluminum oxide,AA0)孔洞 142 之尺寸相似,可 藉由陽極氧化參數加以有效控制,結果如下表所示··1220539 V. Description of the invention (5) 'Chromic acid 1.5 wt%, temperature 60 ° C, time 2 hours. According to a preferred embodiment of the present invention, the substrate 100 is placed in an electrolyte, such as oxalic acid (0.3 ~ 0.4M) or sulfuric acid (1.2M), and an appropriate voltage is applied, such as 40 volts (V). , Porous anodized alumina can be obtained by performing an anodizing reaction at room temperature, and the diameter is from 20 to 60 nanometers. The formation mechanism of the pores is mainly the competitive reaction between electric field-assisted dissolution of alumina and the formation of alumina '. When the rate of alumina generation and dissolution reaches equilibrium, a through-going nano-pore is formed. The arrangement of the holes is the closest packing of hexagonal, and the depth of the holes can be up to several hundred microns, which is proportional to the time of anodizing, so it has a great aspect ratio. Figure 5 It shows the relationship between current density and time (j — T) during anodization. Point A refers to the anode current density at the time of generation of the anodized inscription (a n o d ^ c a 1 u m i n u m ο X i de e, A AO). When the anodic aluminum oxide hole 4 2 develops to the interface between the metal shale layer 140 and the titanium nitride 120, the anode current density starts to decrease sharply (point B). Then the anodic oxidation reaction of titanium nitride 12 20 begins. (◦ point) 'forms a regular array of titanium oxide nano-point arrays 丨 2 2 and the final anode current is also reduced to the lowest value to represent the end of the anodization reaction (point D). The size of the regular array of titanium oxide nano dot arrays 丨 2 2 is similar to that of anodic aluminum oxide (AA0) holes 142, which can be effectively controlled by the anodic oxidation parameters. The results are shown in the table below.
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電壓 電解液 電解液溫度 奈米點/孔洞直徑 40 V 草酸,0.3M 室孟 60 nm 30 V 單酸,0.4M 1 〜5〇C — —--- 40 nm 15 V 硬·酸:,1.2M 5 〜ΙΟ。。 20 nm --:---Voltage electrolyte electrolyte temperature Nano point / pore diameter 40 V oxalic acid, 0.3M room temperature 60 nm 30 V monoacid, 0.4M 1 ~ 5〇C — —--- 40 nm 15 V hard acid: 1.2M 5 to ΙΟ. . 20 nm-: ---
第6a及6b圖係顯示鋁/氮化鈦雙層薄膜在經過陽極 化處理後之SEM照片,其中第仏圖顯示陽極氧化鋁奈米孔 洞的上視SEM照片,第6b圖顯示陽極氧化鋁奈米孔洞的剖 面SEM照片。如第6a圖所示,自我組裝之陽極氧化鋁孔洞 尺寸分佈均一性極佳(〜6〇nm)且排列規則,在同一領域 (domai η)内的奈米洞為接近完美的六角形排列,而領域 (domai η)的尺寸隨著陽極氧化處理的時間增加而成長。 第7a圖係顯示陽極氧化鋁孔洞底部與氮化鈦介面之 TEM照片’第7b圖顯示陽極氧化鋁孔洞底部與氮化鈦介面 之剖面圖。顯示陽極氧化鋁與氮化鈦間,存在一孤立的圓 形島狀物。經電子能量損失光譜儀(Electr〇n EnergyFigures 6a and 6b are SEM images of the aluminum / titanium nitride double-layered film after anodizing. The second image shows the top-view SEM image of the anodized aluminum nanopores, and the sixth image shows the anodized aluminum nanocrystals. SEM photograph of a section of a meter hole. As shown in Figure 6a, the self-assembled anodized aluminum pores have excellent uniformity of hole size distribution (~ 60nm) and regular arrangement. The nano-holes in the same area (domai η) are nearly perfect hexagonal arrangements. The size of the domain (domai η) grows as the time of the anodizing treatment increases. Figure 7a is a TEM image showing the bottom of the anodized aluminum hole and the titanium nitride interface. Figure 7b is a cross-sectional view of the bottom of the anodized aluminum hole and the titanium nitride interface. It is shown that there is an isolated circular island between anodized aluminum and titanium nitride. 1. electron energy loss spectrometer
Loss Spectrometer,EELS)分析證實此島狀物A之組成為 氧化欽’介面B之組成為氧化鈦以及氮化鈦,底層c之組 為氮化鈦。 第8圖係顯示餘刻移除陽極氧化鋁之後所得氧化鈦奈 米點陣列之SEM照片。如第8圖所示,氧化鈦奈米點的尺寸y 分佈與排列方式與陽極氧化鋁孔洞相對應,顯示氮化鈦層 的氧極氧化反應僅發生在奈米孔洞内。利用本發明所備製 之氧化鈦量子點的密度極高,而量子點的尺寸又可藉由陽 極氧化參數加以控制。Loss Spectrometer (EELS) analysis confirmed that the composition of this island A was oxidized oxide 'interface B was composed of titanium oxide and titanium nitride, and the group of the bottom layer c was titanium nitride. FIG. 8 is a SEM photograph showing the titanium oxide nano-dot array obtained after the anodized aluminum is removed at a later time. As shown in Fig. 8, the size y distribution and arrangement of the titanium oxide nano-points correspond to the anodized aluminum pores, showing that the oxygen-polar oxidation reaction of the titanium nitride layer occurs only in the nano-pores. The density of the titanium oxide quantum dots prepared by the present invention is extremely high, and the size of the quantum dots can be controlled by the anode oxidation parameters.
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實施例二 本發明之第二實施例係以第一實施例之規則排列氧化 鈦奈米點陣列122為罩幕,蝕刻下層薄膜11〇以形成一尺 $排列相同而材料不同之奈米點陣列。第9〜12圖係顯示本 發明弟二實施例之規則排列奈米點陣列的製程剖面圖。 請參閱第9圖,提供一基底1〇〇,例如石夕基底。沉積一 薄膜110,例如SiGe或ΙΠ-V族化合物半導體,於基底ι〇〇 上。接著,沉積一導電層12〇,例如Ti、TiN、c〇、Zn、Embodiment 2 The second embodiment of the present invention uses the regular arrangement of the titanium oxide nano-dot array 122 as a mask in the first embodiment, and etches the lower film 110 to form a nano-dot array with the same arrangement and different materials. . Figures 9 to 12 are cross-sectional views showing the process of a regularly arranged nano-dot array according to a second embodiment of the present invention. Referring to FIG. 9, a substrate 100 is provided, such as a Shixi substrate. A thin film 110, such as SiGe or a III-V compound semiconductor, is deposited on the substrate ιo. Next, a conductive layer 12 is deposited, such as Ti, TiN, co, Zn,
以、Cr、W、V、Cu、Mo、Fe 或111,較佳者為Ti 或TiN,於 薄膜11 0上。較佳的沉積方法為濺鍍法或反應性離子濺鍍 法,沉積溫度40 0〜500 °C,厚度1〇〇〜3〇〇埃(A)。接著,形 成一金屬層140,例如金屬鋁,於導電層12〇上。較佳者為 以熱蒸,法,沉積溫度2 00〜30(rc,厚度5〜6微米(Cr, W, V, Cu, Mo, Fe or 111, preferably Ti or TiN, on the film 110. A preferred deposition method is a sputtering method or a reactive ion sputtering method, with a deposition temperature of 400 to 500 ° C and a thickness of 100 to 300 angstroms (A). Next, a metal layer 140, such as metal aluminum, is formed on the conductive layer 120. The preferred one is by thermal evaporation, deposition temperature of 200 ~ 30 (rc, thickness of 5 ~ 6 microns (
接著,將基底100置於真空退火爐中,以500 π退火8 小時,使金屬铭層140的結晶結構緻密完整。然後以電解 拋光步驟進行金屬鋁層14〇之表面平坦化過程。上述電解 拋光步驟較佳者為,以過氣酸/乙醇溶液為電解液,過氣 酸:乙醇係1 : 4,電壓40伏(V),於室溫中進行5〜1〇秒。 請參考第1 0圖,進行金屬鋁層丨40之陽極氧化處理步 ,,,金屬鋁層140氧化成具有規則排列之奈米孔^142的 % 極氧化銘(anodic aluminum oxide,ΑΑΟ)140,,用以做 為後續形成氧化鈦奈米點陣列的模板(template)。當陽極Next, the substrate 100 is placed in a vacuum annealing furnace and annealed at 500 π for 8 hours, so that the crystal structure of the metal layer 140 is dense and complete. Then, the surface polishing process of the metal aluminum layer 14 is performed by an electrolytic polishing step. The above-mentioned electrolytic polishing step is preferably performed by using a peroxyacid / ethanol solution as an electrolyte, a peroxyacid: ethanol system of 1: 4, a voltage of 40 volts (V), and performing the process at room temperature for 5 to 10 seconds. Please refer to FIG. 10 for the anodic oxidation treatment step of the metal aluminum layer 丨 40, and the metal aluminum layer 140 is oxidized to a% anodic aluminum oxide (ΑΑΟ) 140 with regularly arranged nanopores ^ 142, , Used as a template for the subsequent formation of titanium oxide nano-dot array. When the anode
1220539 五、發明說明(9) 當視後附之申請專利範圍所界定者為準。 第14頁 0522-10162TWF(Nl);jamngwo.ptd 12205391220539 V. Description of the invention (9) Subject to the scope of the attached patent application. Page 14 0522-10162TWF (Nl); jamngwo.ptd 1220539
第1〜4圖係顯示本發明第一實施例之規則排列氧化鈦 奈米點陣列的製程剖面圖; 第5圖係顯示陽極氧化反應時電流密度與時間(j — t)的 關係圖; ,6a圖顯:陽極氧化鋁奈米孔洞的上視SEM照片; 第6b圖顯不陽極氧化鋁奈米孔洞的剖面SEM照片; TEM照片; 第7a圖係顯示陽極氧化鋁孔洞底部與氮化鈦介面之 圖; •第7b圖顯示陽極氧化鋁孔洞底部與氮化鈦介面之剖 面 第8圖係顯示蝕刻移除陽極氧化鋁之後所得氧化鈦太 米點陣列之SEM照片;以及 不 第9〜1 2圖係顯示本發明第二實施例之規則排 陣列的製程剖面圖。 不木點 [符號說明] 100〜基底; 11 0〜SiGe薄膜; 11 2〜奈米點陣列;Figures 1 to 4 are cross-sectional views showing the process of a regular array of titanium oxide nano-dot arrays according to the first embodiment of the present invention; Figure 5 is a diagram showing the relationship between the current density and time (j-t) during the anodization reaction; Figure 6a: Top view SEM photo of anodized aluminum nanopores; Figure 6b shows SEM photo of cross section of anodized aluminum nanopores; TEM photo; Figure 7a shows the bottom of the anodized aluminum hole and the titanium nitride interface Figures: • Figure 7b shows the cross section of the bottom of the anodized aluminum hole and the titanium nitride interface. Figure 8 shows the SEM photograph of the titanium oxide terameter dot array obtained after etching and removing the anodized aluminum; FIG. Is a cross-sectional view showing a process of a regular array according to a second embodiment of the present invention. Non-wood dots [Symbol description] 100 ~ substrate; 11 0 ~ SiGe film; 11 2 ~ nano dot array;
120〜導電層; 1 2 2〜氧化鈦奈米點陣列; 1 4 0〜金屬層; 140 〜陽極氧化鋁(an〇dic aluminum oxide,AA〇); 1 4 2〜陽極氧化鋁孔洞。120 ~ conductive layer; 1 2 ~ 2 titanium oxide nano dot array; 1 40 ~ metal layer; 140 ~ anodized aluminum oxide (AA〇); 1 2 2 ~ anodized aluminum hole.
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