1220486 五、發明說明（i) 發明所屬之技術領域 本發明係有關於一種硬體設計之驗證（Verification) 方法，且特別有關於一種可以支援分支（Branch)與中斷 (Interrupt)指令之硬體模擬的硬體設計之隨機功能驗證 方法。 先前技術1220486 V. Description of the invention (i) The technical field to which the invention belongs The present invention relates to a verification method for a hardware design, and particularly relates to a hardware simulation that can support Branch and Interrupt instructions Random function verification method of hardware design. Prior art
在開發半導體積體電路如大型積體電路（Large Scale Integrated circuit，LSI)的過程中，係利用一電腦輔助 設計（Computer Aided Design，CAD)工具來進行設計。如 此使用電腦輔助設計工具的設計環境也可以用在電子設計 自動化（Electronic Design Automation，EDA)環境。在 此包含電腦輔助設計工具的半導體開發過程中，期望之半 導體電路可以利用硬體描述語言（Hardware Description Language，HDL)，如VHDL與Verilog來建立為大型積體電 路。 、 在大型積體電路的設計階段之後，實際的大型積體電 路裝置被送至半導體製造廠中製造（Tape 〇ut)，且大型積 體電路產σ口被半導體測试糸統’如大型積體電路測試器進 行測試來決定是否此大型積體電路裝置可以適當地執行預 期的功能。大型積體電路測試器提供一測試樣本（Test Pattern)給大型積體電路裝置來測試，且將大型積體電路 裝置所輸出的結果與一期望的資料進行比對來判斷此大型 積體電路裝置是否是成功的。 為了較高等級功能性與密集地測試大型積體電路裝In the development of semiconductor integrated circuits such as Large Scale Integrated Circuits (LSIs), a computer aided design (CAD) tool is used for design. The design environment using computer-aided design tools can also be used in the Electronic Design Automation (EDA) environment. In this semiconductor development process that includes computer-aided design tools, it is expected that semiconductor circuits can be built as large integrated circuits using Hardware Description Language (HDL) such as VHDL and Verilog. After the design phase of the large-scale integrated circuit, the actual large-scale integrated circuit device is sent to a semiconductor manufacturing plant (Tape Out), and the large-scale integrated circuit production σ is tested by the semiconductor test system. The bulk circuit tester performs tests to determine whether this large scale integrated circuit device can properly perform the intended function. The large integrated circuit tester provides a test pattern to a large integrated circuit device for testing, and compares the output output of the large integrated circuit device with a desired data to determine the large integrated circuit device. Whether it was successful. For higher-level functionality and intensive testing of large integrated circuit devices
0697-8164twf(nl);p2002-016;yianhou.ptd 第5頁 1220486 五、發明說明（2) 置’應用至大型積體電路裝置之測試樣本必須相應地複雜 ^冗長，結果巨幅地導致工作的負荷與工作時間的增加來 =成此測試樣本。因此，當被測試之大型積體電路裝置被 只際製造時’尤其是具有較短生命週期之大型積體電路裝 置被實際製造時來產生測試樣本是不恰當的，因為將會導 致延誤其上市的時間。0697-8164twf (nl); p2002-016; yianhou.ptd Page 5 1220486 V. Description of the invention (2) Test samples applied to large-scale integrated circuit devices must be correspondingly complicated ^ lengthy, and the results greatly cause work The increase in load and working time comes to this test sample. Therefore, it is not appropriate to produce test samples when large integrated circuit devices being tested are manufactured only, especially when large integrated circuit devices with short life cycles are actually manufactured, as it will cause delays in their market launch. time.
因此’為了改善半導體積體電路整體的測試效率與生 產率’在半導體積體電路的實際測試中通常會使用透過一 軟體模擬器之指令所產生的資料。此軟體模擬器係用以評 估半導體電路之功能性。為了驗證一設計，必須提供包含 預期結果的可執行測試情節（S c e n a r i 〇 s )、倚靠軟體或硬 體設計模型來模擬這些測試情節、比對預期結果與由模擬 所貝際传到之結果、並評估測試情節的適當性與品質。 稱為隨機碼產生（Random Code Gene rat i on )之隨機測 試與微處理器變異（Vari ant )已經被廣泛地使用來驗證複 雜設計的正確性。所有隨機測試的一個關鍵型態係使用假 (Pseudo)隨機數目產生器來協助建立刺激來運作設計。隨 機測試產生器的有用與否直接地與測試情況的品質有關。 習知隨機碼產生之設計具有規則來限制測試中使用之 不可測性之數量，以避免不合法的情況且專注於設計中關 注的情況。純粹的隨機測試產生太多的非法情況且不能夠 徹底地著重於複雜的設計來滿足實際的情況。舉例來説， 分支與中斷係非常困難來應付的’因為分支位移為隨機地 且分支指令與其目標間的間隔間也充滿了並未執行的指Therefore, 'in order to improve the overall test efficiency and productivity of the semiconductor integrated circuit', in the actual test of the semiconductor integrated circuit, data generated through instructions of a software simulator is usually used. This software simulator is used to evaluate the functionality of semiconductor circuits. In order to verify a design, an executable test scenario containing expected results must be provided, software or hardware design models must be used to simulate these test scenarios, the expected results must be compared with the results transmitted by the simulation, And assess the appropriateness and quality of the test plot. Random tests called Random Code Gene rat i on and microprocessor variants (Variant) have been widely used to verify the correctness of complex designs. A key form of all random tests is the use of pseudo random number generators to assist in building stimuli to operate the design. The usefulness of the random test generator is directly related to the quality of the test situation. The design of the conventional random code generation has rules to limit the amount of untestability used in the test to avoid illegal situations and focus on situations that are of concern in the design. Purely random testing produces too many illegal situations and cannot focus thoroughly on complex designs to meet actual situations. For example, branches and interrupts are very difficult to cope with because the branch displacement is random and the interval between the branch instruction and its target is filled with unexecuted instructions.
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五、發明說明（3) 令，此外，也由於中斷的非同步本質，因此，確保正常1 息期間中斷訊息的正確優先處理順序，如鑑別程式部^ 非常重要的。 ° 發明内容 有鑑於此’本發明之主要目的為提供一種可以支援分 支與中斷指令的硬體設計之隨機功能驗證方法。 &刀 為了達成本發明之上述目的，可藉由本發明所提供之 硬體設計之隨機功能驗證方法來達成。V. Description of the invention (3) The order, in addition, because of the asynchronous nature of the interrupt, it is very important to ensure the correct priority processing order of the interrupt messages during the normal period of time, such as identifying the program department ^. ° SUMMARY OF THE INVENTION In view of this, the main purpose of the present invention is to provide a random function verification method for a hardware design that can support branch and interrupt instructions. & Knife In order to achieve the above purpose of the invention, it can be achieved by the random function verification method of the hardware design provided by the present invention.
依據本發明實施例之硬體設計之隨機功能驗證方法， 首先，提供一第一記憶體區域，用以儲存一測試^本 ' 與 一第二記憶體區域，用以儲存中斷指令。接著，將儲疒^ 第一記憶體區域中之測試樣本進行硬體模擬。 ：：子 如果測試樣本進行模擬時接收到一外部中斷， a 憶體區域被存取且其中之中斷指令被進行硬體模 °己 後，中斷指令的模擬結果被自我測試來得到—第一給=社 果，且依據第一驗證結果來驗證硬體設計。 此外，當測試樣本模擬時接收到外部中 令數目的一標籤被設定。當硬體設計依據第一二 證之後，第-記憶體區塊被存取且由標 ;= 硬體模擬。接著’當測試樣本的模擬完成時， 應測試樣本之一第一模擬結果。 』Μ仟到 之後，得到測試樣本以軟體模擬之一 接著’比對第一模擬結果與第二模擬結果來得到一第： 證結果，且依據第二驗證結果來驗證硬體設計。According to the random function verification method of the hardware design of the embodiment of the present invention, first, a first memory area is provided for storing a test copy and a second memory area for storing interrupt instructions. Then, perform a hardware simulation on the test sample in the first memory area of the storage device. :: If the test sample receives an external interrupt while the simulation is in progress, a memory area is accessed and the interrupt instruction is executed in the hard mode. The simulation result of the interrupt instruction is obtained by self-test-first = Social fruit, and verify the hardware design based on the first verification result. In addition, a tag that receives the number of external commands when the test sample is simulated is set. After the hardware design is based on the first and second certificates, the -th memory block is accessed and marked by the; = hardware simulation. Then, when the simulation of the test sample is completed, the first simulation result of one of the samples should be tested. After the arrival of the test sample, one of the test samples is obtained by software simulation. Then, the first simulation result and the second simulation result are compared to obtain a first verification result, and the hardware design is verified based on the second verification result.