TWI220314B - Manufacturing method of deep sub-micron meter process of electrostatic discharge protection apparatus - Google Patents

Abstract

The present invention reveals a kind of manufacturing method of deep sub-micrometer process of electrostatic discharge (ESD) protection apparatus. In the deep sub-micrometer process, self-aligned silicide is applied in the transistor source/drain regions including the ESD-protection device, and non-uniformly high current causes damage of ESD protection device; to improve the problem, a self-aligned silicide blocking-manner is adopted in the present invention. Inside the ESD protection device region, no silicide is formed; and a resistance buffer region is disposed between the drain contact and polysilicon gate such that it is capable of having one more uniform manner to eliminate the high current generated by ESD, so as to prevent the ESD protection structure from being damaged.

Description

1220314 V. Description of the invention (1) '----- [Technical field to which the invention belongs] The present invention relates to a method of manufacturing an electrostatic discharge protection device (ESD Pl ^ teCtion device), and more particularly to a method which will be used in a subtle manner. The self-aligned metal silicide (Sel f — al igned Si 1 leide 'Salicide' in the manufacturing process is applied to the manufacturing method of the electrostatic discharge protection device), and at the same time, the electrostatic discharge structure is prevented from being damaged. [Previous technology] According to the structure of N-type or P-type transistor (N / P m〇S), such as gg (gate-ground) N / PM0S, gc (gate-control) N / PM0S element or other similar The structure is widely used in current deep sub-micron electrostatic discharge protection device components. N / PM0S is mainly due to the element characteristics of its parasitic bipolar transistor (B i ρο 1 ar). When a high voltage occurs for a moment, its parasitic bipolar transistor will be triggered to properly guide its high voltage. High current to Vss or Vdd. Using the ggN / PMOS element in the integrated circuit as the electrostatic discharge protection device 10, the circuit structure is shown in the first figure, and the instantaneous forward high voltage will start the parasitic bipolar element of NM0S 12 to direct the high current to the Vss terminal; The instantaneous reverse high voltage activates the parasitic bipolar element in PM0S 14 and directs high current to the Vdd terminal. This application principle is shown in the second figure. When an electrostatic discharge event occurs at a pad of an input terminal, the ggN / PMOS will be triggered and enter the snapback region. And, in this sudden turning area, the ggN / PMOS will clamp a low potential voltage across itself and maintain a high current, so that the electrostatic discharge current can be effectively guided out.

Page 5 1220314 V. Description of the invention (2)-When a ggNMOS device is applied to a static electricity protection device manufactured by a non-self-appreciating metal silicide (Salicide) process, the structure is shown in the third figure. There is a buffer distance between the drain contact 16 and the poly gate 18 as a resistance ballast. When the NPN transistor 20 is triggered, its high current can be relatively uniform. (H 〇m 〇gene 〇us) were excluded. However, in the deep sub-micron process, the self-aligned metal silicide 22 is applied to the polycrystalline silicon gate 18 and the source / drain regions M and 16 in the electrostatic discharge (ESD) protection structure, such as the fourth As shown in the figure, this will cause a few resistors between the drain electrode 16 and the polycrystalline silicon gate 18-point resistance buffer. When a static high voltage is generated, causing the parasitic NpN (or PNP) transistor in the protective structure to be triggered, the current generated by the high voltage can be discharged,

0W However, the collector N of the NPN transistor (Collect0rn, equivalent to the drain in ggNM0s) does not have a resistance buffer. In addition, it is a structural design with an i junction. The flow of high current will Will be uneven (ingenesis), causing local / current and local heating phenomena near the drain, leading to potential damage to the ESD protection structure and electrical discharge protection. The present invention is directed to the above-mentioned problems, and a method for manufacturing a deep-level micro-electrostatic discharge protection device is provided to effectively solve the aforementioned problems. [Summary of the invention] The main purpose of the lightning amplifier invention is to provide a method for manufacturing an electrostatic discharge protection device for a deep sub-micron process.

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Another aspect of the present invention is that the electric current of the electric discharge protection device effectively guides the electric current and the local heating phenomenon to be destroyed. = Fang Li Zai-a kind of deep sub-micron process ^ /, /, is the high electrostatic voltage generated 'to avoid local high near the drain region' so it can effectively prevent the electrostatic discharge protection structure from becoming There are compartments and the body substrate for electrical discharge on the mask field. After the formation of electrical protection, the above-mentioned η is reached, and the structure and doping # ΐ 明 系 * on the semiconductor substrate are source / immortal. Well The basic structure such as a Λ interlayer structure and a light ion doping form a% doped region; and then a half of each patterned photoresist ... this patterned light is a non-static discharge of the semiconductor substrate. Electrical protection element = layer, and The remaining thin layer is overlying the region of the semiconductor substrate, and then the patterned photoresist is removed. The polysilicon gate, source / Remove the remaining thin layer on the surface of the drain region. 71

In the following, detailed descriptions are provided by specific embodiments in conjunction with the accompanying drawings, so that it is easier to understand the purpose, technical content, characteristics and achievement of the present invention: effects. [Embodiment]

1220314 V. Description of the invention (4) The present invention is to improve the shortcomings of the electrostatic discharge (ESD) protection element in the process of self-aligning metal silicide, using self-aligning metal silicide block method, so that The formation of polysilicon gates in the ESD protection element area and the absence of metal silicide on the source / drain regions makes a resistance delay between the electrode contact (drain contract) and the polycrystalline gate. The impact ballast (resistance ballast) can allow the high current generated by electrostatic discharge to be eliminated in a more uniform way, so no local high current and local heating phenomenon will occur near the drain.

The fifth (a) to fifth (e) diagrams are sectional views of the structure of each step in the production of the transistor of the internal circuit and the electrostatic discharge protection device according to the preferred embodiment of the present invention. The type of transistor (guan os) is Example, detailed process. An esdYi Λ five (a) diagram * 'A semiconductor substrate 30 is provided with an Λ 4 domain 32 and a thin protective element region inside & = advance: ί early; a standard process of deep sub-micron, here 』(P-Well) 36 STU38, ^ several shallow trench isolation areas after (

Then, the gate structure 40 is used as the conducting soil = the polycrystalline silicon gate structure 40 is formed. U and U are two curtains, and the two are ion implantation ... forming a light: hybrid well area 36 for-low concentration heavy ion implantation, The wells are respectively formed into hybrids P: 3 and 6 :; 亍; high concentration ... ^ Sub-doped regions 46 and N-type heavy sputtering

A gate gap wall 44 is formed next to the two side walls. In addition, the gate structure is combined with the gap wall 44 as a cover, and the p ′ M open-pole structure 40 and the gate finger 1220314 are described in (5) Miscellaneous area 48. As the source / drain region; then a rapid thermal recovery and processing are performed, so far the basic components on the semiconductor substrate 30 have been completed

Next, as shown in FIG. 5 (b), a chemical oxide deposition (CVD) method is used to form a thin oxide layer 50 on the semiconductor substrate 30 so as to cover the aforementioned basic components. Using a lithography process, The thin oxide on the semiconductor substrate 30 = 5-0 surface forms a patterned photoresist 52. As shown in FIG. 5 (c), eight are covered on the ESD protection element region 32 to expose the internal circuit region 34. The thin oxide layer 50 is used as a mask, and the thin oxide layer 50 is wet-etched to remove the thin oxide layer 50 on the internal circuit area 34 of the semiconductor substrate 30 without The removed thin oxide layer 50 only covers the ESD protection element region 32 of the semiconductor substrate 30; subsequently, the patterned photoresist 5 2 can be removed by insects.

After the thin oxide layer is completed on the ESD protection element region 32, a self-aligned metal silicide process can be performed. As shown in FIG. 5 (d), a titanium metal layer 54 is first sputtered on the semiconductor substrate 30 to form a titanium metal layer 54. At this time, the titanium metal layer 5 4 on the ESD-protected 70-piece region 32 covers the surface of the thin oxide layer 5 and 0, and the titanium metal layer 54 on the internal circuit region 34 is directly covered. , The surface of the Shixi gate 40, heavy ion doped regions 46, 48 and other components; and then the same rapid heating process, at this time, the titanium metal layer 54 located on the internal circuit region 34 will and polycrystalline stone Xi The gate 40 and the heavily ion-doped areas μ and 48 surface contact portions generate silicidation reaction to form titanium silicide (T i S i2), and then custom alignment to form metal silicide 56; which is located in the ESD protection element area Because of the thin oxide layer 50 within 32 as a barrier, no metal silicide will be formed.

Page 9 1220314 V. Description of the invention (6) Finally, the remaining titanium metal 5 4 and the remaining thin oxide layer 50, which are not involved in the reaction or after the reaction, are selectively removed by wet etching, so that the The internal circuit region on the semiconductor substrate 30 is formed with a self-aligned metal silicide 56 structure as shown in the fifth (e) figure. Thus, a complete deep sub-micron Sa 1 ici de process transistor structure has been completed. Among them, the material of the metal layer may be titanium, nickel, nickel, nickel or other metals. When making self-aligned metal silicide, the present invention utilizes a barrier structure of a thin oxide layer over the ESD protection element area to avoid unnecessary self-contact on the drain contact and polysilicon gate in the ESD protection element area. Alignment of metal silicide is generated, so that a resistance buffer exists between the drain contact and the polysilicon gate, so that the high current generated by electrostatic discharge can be eliminated in a more uniform manner. Therefore, the present invention can effectively guide the current generated by static electricity and voltage to avoid local high current and local heating phenomenon near the drain region. Therefore, the electrostatic discharge protection element can be effectively prevented from being destroyed and the electrostatic discharge can be prevented. Protective elements can ensure their effectiveness in electrostatic discharge protection. The above-mentioned embodiments are only for explaining the technical ideas and special features of the present invention! In order to enable those skilled in the art to understand the present invention: 1 The implementation of the patent scope of the present invention should not be used to limit it That is, the equal changes or repairs made by the spirit not disclosed in the Da-Er '1 Ming should still be included in the patent scope of the present invention. [Illustration of drawing number]

1〇 Electrostatic discharge protection device 12 NM0S

1220314 V. Description of the invention (7) 14 PMOS 16 Drain contact (area) 18 Polysilicon gate 20 NPN transistor 22 White line aligned metal oxide 24 Source area 30 Semiconductor substrate 32 ESD protection element area 34 Internal circuit area 36 P-type doped well region 38 Shallow trench isolation region 40 Polycrystalline broken gate structure 42 Light ion doped region 44 Gate spacer 46 P-type heavy ion doped region 48 N-type heavy ion doped region 50 Thin oxide layer 52 patterned photoresist 54 titanium metal layer 56 metal silicide

Page 11 1220314 Brief description of the diagram The first diagram is a schematic diagram of the circuit structure of the MOS component of the conventional electrostatic discharge protection device used in integrated circuits. The second figure is a graph showing the occurrence of electrostatic discharge. The third figure shows the structure of a conventional MOS device applied to an electrostatic discharge protection device. The fourth figure is a conventional transistor structure with a self-aligned metal discharge protection device. · Figures 5 (a) to 5 (e) are cross-sectional views of the structure of each step in the process of manufacturing the internal circuit and the electrostatic discharge protection device of the present invention.

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Claims (1)

1220314 VI. Application for patent scope 1: The electrostatic discharge protection device of a deep sub-micron process includes the following steps: Each method is provided, and the fv body substrate is formed with an isolation junction #, and the weight of the common electrode is doped. Ion-doped regions and other basic elements; and as a source " and forming a thin layer on the semiconductor substrate so that it covers the aforementioned elements on the surface of the thin layer on the substrate: patterning photoresist, and The patterned photoresist is a mask, a non-static lightning arrester at the bottom: batch 4 layers to remove the base layer: the thin layer on the area of the discharge protection element, and the thin layer except χ covers only Above the semiconductor: without removing the element area, ρ is connected to the ground: electrostatic discharge protection of the substrate-隹-remove the patterned photoresist; 仃 仃 align the metal silicide process to make the s + s The polycrystalline silicon gate formed on the semi-conductive + self-aligned metal silicon 2 region: electrostatic discharge protection removes the remaining thin layer. The original and polar & domain surface; and the manufacturing method as described in item i of the scope of patent application, wherein the electrostatic discharge protection device is manufactured as described in the scope of the patent scope of the project if:: f channel isolation structure.诰 方 味甘 + — μ's method of electrostatic discharge protection device, wherein the doped well is changed in the I well area. The system includes an N-type doped well region and a p-type doped 4 as described in the first patent application, +, ^ ^ manufacturing method, wherein the heavy ion impurity is an ion-doped region made by an electric discharge protection device. ’, The product range includes the weight of N-type and p-type Page 13 1220314 6 · The method according to the scope of patent application No. 1, wherein a part of the thin layer is removed by etching the thin method. 7 · The method made in item 1 of the scope of the patent application, wherein the self-contained method is included in the step of forming the electrostatic discharge protection device described in the step of using a wet etching method to align the metal silicide with the electrostatic discharge protection device described above. More steps Forming a metal layer on the semiconductor substrate; performing high-temperature heating treatment, so that the metal layer and the polycrystalline silicon gate, the heavy ion doped region and the surface of the isolation structure on the non-electrostatic discharge element region are silicified React and self-align to form a metal silicide; and remove the metal layer that has not reacted to the metal silicide. 8. The method for manufacturing an electrostatic & electrical protection device according to item 7 of the scope of patent application, wherein the material of the metal layer is selected from the group consisting of titanium, cobalt, nickel, palladium and platinum, and the commonly used is titanium. • = f Please make the method of electrostatic discharge protection device described in item 7 of the patent scope, wherein the high temperature heat treatment is performed by a rapid heating process completion. The method for manufacturing the electrostatic discharge protection device as described in item 7 of the Shen Jing patent scope, wherein the step of removing the unreacted metal layer is selectively removed by means of wet etching d. Page 14 1220314 Page 15