TWI220271B - Method of forming high-density nonvolatile memory encoding - Google Patents

Abstract

The present invention is related to the method of forming high-density nonvolatile memory encoding and the related mask. The mask of the invention has a line/separation pattern for programming one array region. The array region has plural programmable regions arranged in arrays.

Description

V. Description of the invention (2) The coding mask 30 in Fig. 2 defines the place where the array area go needs to receive the ion cloth value. Fig. 2 is a binary mask 'having a groove / pitch pattern, which means a pattern formed by a light-transmitting groove 32. The two light-transmitting grooves 32 are opaque areas. Figure 3A is a top view of the photoresist layer on the array area using the coding mask of Figure 2 to transfer the pattern. Fig. 3B is a sectional view taken along line aa in Fig. 3A. A trench / pitch pattern similar to that shown in FIG. 2 is also formed on the photoresist layer 28. The photoresist layer 28 corresponding to the opaque area on the encoding mask 30 remains. The photoresist layer 28 corresponding to the light-transmitting grooves 22 on the reticle 30 is exposed and developed and removed to become concave: the groove / pitch pattern on the photoresist layer 28 is as shown in FIG. 3A, because Effect (pr〇ximi ty effect), there will be a corner rounding effect (corner rounding). The programmable region not covered by the photoresist layer 28 will be affected by the subsequent ion layout process and write data. The groove / pitch pattern in Figure 3A has the following disadvantages: 穑 I1 立 ί ί Difficult shrinkage (shrinkage): the cost of the semiconductor wafer surface = = Π ..., all semiconductor manufacturers open H 2 white, Target next-generation products. It is well known that the necessary condition for forming a photoresist layer with a trench / pitch pattern is a well on the photoresist layer, as in the first embodiment. Moreover, the exposure of a well on the barrier layer to the formation of light is getting smaller and smaller, and it will encounter considerable difficulties. lmenslon) The immersion process will be quite sensitive to mis-alignment: in the subsequent process, the layout process will distribute the two sidewalls of the trench 10 / as shown in the figure n. Assume that because of the misalignment of the coding mask, the second 1220271 V. Description of the invention (3) / shift_map ~ The case does not align with the array area 80 below ', for example, the lateral deviation problem t distance. Please refer to Figure 3C. Figure 3C shows the misalignment caused by the blocking of the upper photoresist layer 28, which leads to the subsequent ionic layout system = ". ,,, and method. The main purpose of the present invention is to provide a non-volatile memory coding method that can reduce the number of cases. Yu Yan's other main object of the invention is to reduce non-volatile memory pairs; Sensitivity of the misalignment of the flat code mask. Ji Qing ΐ ΐ ΐ 目 目 #, the present invention provides a high density non-volatile formation. First, an array area (-"Kao heart, X area has a plurality of arrayed arrays Programmable area. Then in the array

: A patterned masking layer is formed on the two's to selectively mask the programmable areas. The masking layer has a line / distance pattern ... J 佶, in the sub-train area, the area not covered by the masking layer is subjected to ionic layout 'to program the array area. The present invention also provides a kind of program-programmable non-volatile memory, which can be arranged in an array; The array area has a program to program the array area. On the reticle, a line / pitch pattern means that the pattern is a pattern of lines. For the dark and dangerous I scented by the raised shadow masking layer, the one-line / pitch pattern is not a pattern composed of raised lines.

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The advantage of the present invention is that the line / space pattern is relatively easy to shrink down in the semiconductor and manufacturing process, so it is easier to manufacture the next generation of non-volatile memory. Another advantage is that the coding of non-volatile memory will be less affected by the > scenarios > to improve the process yield of non-volatile memory. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a specific embodiment is provided in detail, and the detailed description is given in conjunction with the accompanying drawings such as r:

Figure 4 shows the picture of the younger brother. Figure 4 is a two-dimensional morphine of a two-dimensional morphine according to the present invention, which is a coding mask (c0ding50. This% 疋 is used to program the array area 8 in Figure 1A. . As previously attacked, drained drain 2 2_ several trenches 10, or called buried gas fossil evening layer "and a nitrided stone 2: :: trench 10 is composed of 10 ^ pore hole layer 1 on both sides 6 is used as a lithographic barrier, and the etching comes from the U. The pre-coded trenches 18 roughly etch the base exhaustion trenches 18 and the trenches 1G at a straight angle-a pre. 80, arranged in an array. Array area

Pattern of the coding mask 50 of the present invention. For a reticle, a main feature is to have a pattern / distance pattern composed of a line / space opaque line 52, which means that the pattern is a light-transmitting area, as in the case of 帛 4BH. ^ Figure 5A between the two lines 52 is the use of 飨 α of Figure 4, the flat code mask 50 to transfer the pattern to the array area

1220271 V. Description of the invention (5) ^ 's = resistance ^ top view. Figure 5β is a section along line M in Figure M:. The two layers 28 serve as a shielding layer to block subsequent ionic distribution values. The photoresist is formed in a line / space pattern similar to that in FIG. 4. The photoresist layer 28 corresponding to the coded photomask ® ^ μ light area is removed due to exposure and development; the photoresist layer 28 corresponding to the code 'opaque line 52 is retained to form a protruding line i. Therefore, for the photoresist layer 28 In terms of a line / pitch pattern, it means a pattern composed of convex lines, as shown in FIG. 5A. Because of the 'proximity effect', the photoresist layer 28 will have a corner roundlng effect. The programmable lines not covered by the photoresist layer 28 are photoresist lines formed by opaque lines 52 on the code mask 50, which are parallel. The photoresist line can be designed with the groove i. : The article says 'Under the condition of alignment, the photoresist line is located exactly. The invented coding mask is not limited to a two-dimensional (binary) mask.' It can be a phase shift mask or A chromeless mask. The important point is that the present invention forms a line / space pattern in the tomb area. Shoulder shoulders should be in the array early: Compared to Figures 5A and 3A, it can be found. The previous trench / pitch pattern mainly exposed the maskable other areas that need to be programmed and can be programmed; the masking of the photoresist layer of the present invention does not need to be patterned. The area outside the 'programmable area in area 80 is defined as: 1220271 V. Description of the invention (6) In the sensitive area, the prior art is to cover most of the non-sensitive areas, while the present invention is to expose most of the non-sensitive areas. Such a line / space pattern has the following advantages: 1. Easy shrinkage. As is well known, the necessary condition for forming a line / space pattern photoresist layer is to ensure that a dot on the photoresist layer can be formed. The dot-island is shown in the middle left of FIG. 5A. It is easier to expose and develop a dot-shaped island on the photoresist layer than to form a well on the photoresist layer. Therefore, the method of the present invention can be effectively applied to the next generation of integrated circuit products. 2. For misalignment, ^^^ ⑽⑽ will be less sensitive: the subsequent ion layout process will distribute the two sidewalls of the trench 10, as shown in the first redundant figure. Suppose that due to the misalignment of the coding mask, the groove pattern / distance pattern on the photoresist layer is not aligned with the array area 80 below. For example, # 向 的 ^ No: illuminate M, Figure 5C shows the fourth This photo is a cross-sectional view formed by the photomask Yu Wei Shou. Even if there is a misalignment of the ten main bands, the distance of the photoresistive lines is about. 蚩 ..1 Π ^ ^ is subject to the ion distribution value. As for the second job :: groove: both sides of 1 ° will be groove i. It will be because the second 6: the situation that it should be worth the ion cloth does not make the data 2 covered by the 2 resist layer 28. In this way, 々—, pin must be written in the groove 10. Because the code ion 佶 佶 _ a large-angle cloth value ^ ^,, J u 1 away from the teacher value 疋 ratio) too high groove I ί two = two ratio (dePth ~ t〇—height path effect ... In particular, = 2; not = to a large angle to suppress the distribution of the value, accurately data: the "month" method and the mask to reduce the misalignment of the shadow horse into the array area 80. Only the yoke example is disclosed above, but Not to limit

0389-7484TWF (Nl); P900506; EDWARD.ptd page 9 Although the present invention is relatively small mm 1220271

0389-7484TWF (N1); P900506; EDWARD.ptd Page 10 1220271 The diagram briefly illustrates that Figure 1A is a top view of an array area before data has been written to the memory; Figure 1B is the AA line extending in Figure 1A Figure 1C is a cross-sectional view along line BB in Figure 1A; Figure 2 is a conventional encoding mask; Figure 3A is a pattern transfer to the array area using the encoding mask in Figure 2 Above view of photoresist layer. Fig. 3B is a sectional view taken along line AA in Fig. 3A. Figure 3C shows the problems caused by misalignment in the prior art. FIG. 4 is a coding mask according to the present invention. Figure 5A is a top view using the photoresist layer on Figure 4. Figure 5B is a cross-sectional view along line AA in Figure 5A. Figure 5C shows a cross-sectional view of the mask of Figure 4 misaligned during the lithography process. Explanation of symbols: trench 10 substrate 12 stone oxide layer 1 4 silicon nitride layer 1 6 pre-coded trench 1 8 silicon nitride layer 2 2 photoresist layer 2 8 coding mask 3 0

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Claims (1)

1220271 VI. Scope of patent application1. A method for forming a high-density non-volatile memory code, including: a length of 1 for an array region, with a plurality of programmable regions arranged in an array; in the array region Forming a patterned masking layer thereon to selectively mask the programmable areas, the masking layer having a line / space pattern; and in the array area, the area not covered by the masking layer, An ion layout is performed to program the array region. 2 · If the scope of patent application is the first! The method of claim 1, wherein the array region includes a plurality of first trenches and a plurality of pre-coding trenches, and the first trenches are perpendicular to the precoding trenches Each programmable area is formed by an intersection area formed by one of the first grooves and one of the precoded grooves. 3. The method of claim 2 in the scope of patent application, wherein the plurality of lines in the line / space pattern are substantially parallel to the first grooves. 4. The method according to item 2 of Shen Qing's patent scope, wherein the plurality of lines in the line / pitch pattern are located approximately on the first grooves. 5. The method according to item 2 of the scope of patent application, wherein the plurality of lines in the line / space pattern are aligned with the first grooves. ', 6 · The method according to item 2 of the Shenjing patent scope, wherein a silicon oxide layer (si 丨 ic〇n 〇xide) and a nitride layer are stacked on the array region between the first trenches. (Silicon nitride). 7. The method according to item 2 of the patent application scope, wherein the precoding 0389-7484TWF (N1); P900506; EDWARD.p t d p. 13 1220271 On the array region between the trenches, there is a silicon oxide layer. * Λ: a coding mask used for stylized-non-volatile memory, Ξ; = has an array area, and a queue area has a row = row, for programming the array = one line / space (Line / space) Figure 9. The number of first grooves (…) and pre-two-row (per-coding) ^ ^ # ^ vertical 'mother- The programmable area is formed by the intersection area formed by one of the pre-programmed grooves Λ1. • σ declares that the code of the patent No. 9 in the patent encloses the array area before the line / distance map is passed. In the factory, the shielding layer is transferred. ^ The case is transferred to one of the array areas, the shielding + η. For example, the coded photomask of item 10 of the patent application scope, wherein the plurality of lines in the shielding layer are roughly Parallel to the first grooves 12. If the coded photomask of item 10 of the patent application scope, the plurality of lines in the shielding layer are roughly located on the first grooves. 1 3. As of the patent application scope J 〇 The plurality of lines in the masking layer are aligned with the tangent of the first grooves = the coding mask of the tenth item in the range of the ^ Λ Shen Λ special Λ, where the brother-= between A silicon oxide layer (siii_ oxide) and a silicon argon layer (siUcn ni 忖 ide) are stacked on the array area. 15. For example, the coding of item 8 of the patent application is a phase shift (fine eshl⑴ mask). ， —Two-dimensional type Shushun) light 1220271 6. Scope of patent application One of the mask and a chrome less mask. Page 15 0389-7484TWF (N1); P900506; EDWARD.p td