TWI220062B - Passivation layer of integrated circuit and its manufacturing method - Google Patents

Abstract

A kind of passivation layer structure of integrated circuit formed on a substrate having devices contains the followings: UV silicon nitride (UVSiN) layer formed on the substrate; undoped silicon glass layer formed on the silicon nitride layer; and silicon-oxy-nitride layer formed on the undoped silicon glass layer. The undoped silicon glass layer is formed by sub-atmospheric chemical vapor deposition (SAPCVD) method; and the silicon-oxy-nitride layer is formed by plasma enhanced chemical vapor deposition (PECVD) method. In the invention, solidification procedure is eliminated and Q-time problem is solved so as to have the advantages of simplifying manufacturing process and lowering production cost.

Description

1220062 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an integrated circuit protective layer and a manufacturing method thereof, and more particularly, to an application in a flash memory (f 1 ashmem 〇ry) Integrated circuit protective layer and manufacturing method thereof. [Prior art]

In the semiconductor manufacturing process, in order to protect the integrated circuit from the external environment, such as moisture (moi sture), foreign impurities, and mechanical damage, a passivation is usually deposited on the integrated circuit. Common protective layer materials are, for example, silicon dioxide (Si02), silicon nitride (Si3N4), oxynitride (SiON), and phosphosilicate glass (PSG). Due to the increase in the integration degree of current integrated circuits, in order to match the increased internal wiring (i n t e r c ο η n e c t s) requirements after the reduction of mos transistors, the design of two or more metal layers has gradually become a method that many integrated circuits must adopt. In particular, some products with more complicated functions, such as a microprocessor (Microprocessor), even need four or five layers of metal layers to complete the connection between the various components in the microprocessor.

The metal interconnects of the integrated circuit. The upper and lower metal layers are taken as an example. The upper and lower metal wires are interleaved with each other. The plugs are used to connect the upper and lower metal wires to enable each transistor on the chip. Achieve the purpose of connected strings. Please refer to FIG. 1, which is a schematic cross-sectional view of two layers of metal interconnects in a integrated circuit. There is a MOS transistor layer above the substrate silicon 101, and a first metal line 105 is formed on the MOS transistor layer 103 to become the first metal layer.

1220062 V. Description of the invention (2) Inter-Metal Dielectrics 107 formed by dielectric materials are used to isolate the first metal wire 105 and the second metal wire 1 10, Keep the two from shorting without making direct contact. The plug 11 1 connects the first metal wire 105 and the second metal wire 109 to complete the circuit of the entire metal interconnection. The protective layer is formed after the second metal line 109. Please refer to FIGS. 2A to 2E, which illustrate a conventional method for manufacturing a protective layer of an integrated circuit. First, as shown in FIG. 2A, a substrate 20 is provided, and a second metal wire 203 has been formed on the substrate 202. In contrast to the first figure, the substrate 2 02 is the lower part of the second metal wire 1 10 in the first figure. Then, as shown in FIG. 2B, cover the UV silicon layer (si3N4)

^ ^ ^ V V, x3 i is above the substrate 20 2 and covers the second metal wire 2 0 3. Among them, the thickness of the silicon nitride layer 20 4 is about 4 00 A (angstrom). "

Next, as shown in FIG. 2C, a solution type silicon dioxide (Si02) is filled into a hole between the second metal wires 203 by a spin coating method to form a silicon dioxide layer 2 〇6, with the same height as the second: silicon nitride 2 04 above the money 203, this step is also called local planarization ^ (local planarization). Since the solution of the silicon dioxide layer 206 is a mixture of a solvent and a silicon dioxide-related compound, and the wafer is coated by a rotating bow cover, the silicon dioxide layer 206 is also called a formula Glass (Spin-On-Glass, SOG). Next, hot baking is performed in the furnace tube at a temperature of " 40 0 ~ 45 to remove the solvent in the SOG {the liquid ^ a emulsified stone is cured. 'After curing, as shown in Figure 2D, cover on the silicon dioxide layer 206

TW0462F (Wang Hong) .ptd Page 7 1220062 V. Description of the invention (3) Nitrogen oxide layer 208 (Sil icon- 〇xy-Nitride, SiON), Nitrogen oxide layer 208 pairs of moisture and impurities The blocking ability is more ideal than that of the silicon dioxide layer 206. Wherein, the thickness of the silicon oxynitride layer 208 is about 6000 A (angstrom). Then, as shown in FIG. 2E, a silicon oxynitride layer 208 is covered with a phosphate glass layer (PSG) 210. Phosphosilicate glass is a silicon dioxide with a phosphorus content of about 6 ~ 8 weight%. PSG not only has excellent absorption energy for water vapor in the air = ', but also contains phosphorus for alkali metal ions (AlkaHne; [〇ns ) Also has the effect of getter ing. Among them, the thickness of the phosphosilicate glass layer 21 is about 9000 a (angstrom). Then, subsequent processes such as yellow light, etching, etc. (not shown in Figures 2A to 2E) are performed to complete the semiconductor device. Said = 'In the multilayer protective layer of the above-mentioned conventional manufacturing process, the material price of SOG is 叩 shellfish' and requires a curing process of at least 2 hours, which is very time-consuming. In addition, there is the problem of waiting time (Queue t ime). If the qt ime time is too long and the component has absorbed too much moisture in the storage environment, it needs to be baked again (c ur i ng). uneconomic. Therefore, how to simplify the process ’to shorten the process time and reduce the manufacturing cost is the goal of the R & D staff. In addition, in the process of flash memory (f 1 ashmem ry), the element will be irradiated with ultraviolet light (uv) after the protective layer is formed to remove = necessary impurities and ions. Therefore, ultraviolet light The higher the transmittance of the protective layer, the more the transmittance of ultraviolet light is affected by the material of the protective layer. A conventional silicon nitride has a UV transmittance of only about 〇0 ～ 20%. Description of the Invention (4) This is one of the research directions of "how to improve preserving addiction". The layer material's transmittance to ultraviolet light is also important. [Summary of the Invention] In view of this, the purpose of the first layer and its manufacturing method, second, and i is to provide integrated circuit protection. To achieve the purpose of simplifying the process and reducing the production cost According to the purpose of the present invention, the method is proposed, including the following steps: & Dishan # 里 峪 谩 11. The metal layer is required for the manufacture of the metal layer. Πινς · NM ·], then, a UV silicon nitride layer is formed on the substrate to form ^ # Then, a sub-normal pressure chemical vapor deposition method is used on the silicon nitride layer 1 = an undoped silicon glass layer (SAUSG); and forming a silicon nitride oxide layer (Si0N) on undoped hard. According to another object of the present invention, a junction of an integrated circuit protection layer is provided. The junction is formed on a substrate having a component, and includes: a UV silicon nitride layer formed on the substrate; and a silicon nitride layer. An undoped silica glass layer on the substrate; and a silicon oxynitride layer formed on the undoped silica glass layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: [Embodiment] The metal inside the integrated circuit The wiring is multi-layered, and its range can be increased from two to five. A protective layer is deposited over the last metal line. in

TW0462F (Wang Hong) .ptd Page 9 1220062 V. Description of the invention (5) In the following embodiments, 'two layers of metal interconnects are used as the description of the preferred embodiment of the present invention. The first metal line in the lower layer is separated from the second metal line in the upper layer by a dielectric layer, and a protective layer is deposited over the second metal line. Please refer to FIGS. 3A to 3D, the edges of which illustrate a method for manufacturing an integrated circuit protective layer according to a preferred embodiment of the present invention. The integrated circuit protective layer is formed on a substrate having a component. As shown in FIG. 3A, the substrate 302 has a 苐 * -metal wire 303. Then, as shown in FIG. 3B, a siliconized silicon layer (Si3N4) 304 is covered over the substrate 302, and a second metal wire 303 is covered. Among them, the thickness of the silicon nitride layer 304 is about 400 0A (angstrom) °. Then, as shown in FIG. 3C, a sub-atmosphere CVD method is applied to the silicon nitride layer 304. An undoped silicon glass (USG) 306 is formed on the top, so the silicon nitride layer 304 is also called SAUSG. Among them, the sub-normal pressure means slightly lower than the atmospheric pressure ', and its pressure range is about 200 to 400 torr. The thickness of the glass layer 306 without replacement stone is about 7000 A (angstrom). Then, as shown in FIG. 3D, a silicon oxynitride layer 308 (Silicon-〇xy-) is covered on the undoped silica glass layer 306 by Plasma-Enhanced Chemical Vapor Deposition (PECVD). Nitride, SiON). The silicon oxynitride layer 30 8 has a better barrier to moisture and impurities than the conventional silicon dioxide layer 206. The thickness of the 'I oxide oxide layer 308 is about 9000 (angstrom). ’Followed by subsequent processes, such as yellow light, etching, etc. (not shown in

TW0462F (Wang Hong) .ptd Page 10 1220062 V. Description of the invention (6) (3A ~ 3D picture) to complete the semiconductor device. In particular, when using ultraviolet light to remove impurities and ions in the process of flash memory, the conventional silicon nitride layer 204 has a UV light transmittance of only about 10% to 2 0%, making removal difficult to achieve. Therefore, in the nitrided oxide layer 300 of the present invention, 'the hydrogen is added to the nitrided nitride layer to form a nitrogenite compound (Six Nγ Hz)' The existence of hydrogen bonds causes the ultraviolet light (uv) of the nitrided stone layer. The penetrability is greatly improved, so that the ultraviolet (UV) transmittance of the silicon nitride layer 304 of the present invention can be as high as about 70% to 80%. Compared with the traditional integrated circuit protection layer, the process of the present invention uses chemical vapor deposition to deposit an undoped silica glass layer 3 06 to replace the expensive liquid dioxide layer 2 in the conventional process. 0 6, not only the material is cheap, σ, and does not need to go through the curing (Curing) step, which greatly shortens the process time, and there is no known Q-time and re-curing problems. In addition, it has been shown that the conventional phosphosilicate glass layer (p SG) 2 丨 〇 is also omitted, and is replaced by a thickened 卞, siliconized layer 30 8. Therefore, the process of the present invention only requires UVS ^, lice oxygen 3 Eight 1 ^ 6 and 8 丨 (^ have a total of 3 protective layers, compared with the traditional process of 8 and 4,

SiON and PSG have 4 more protective layers, which simplifies the process time greatly, making the process time G, and making the most square wires connected to each other to form a metal shape within the manufacturing genre. The layer of gold threads and the two continuous layers contain multiple layers. Of it. Protective cases include roads, roads, roads, Jin Shifan, electricity, layered body, and body. Or above this layer of lighting is exposed in Siyifa. Although it is limited to the layer office, it is not included in the protective case and is also guaranteed. The example is as follows. The implementation of the example shows the above actual version, and the above line is the road. It belongs to the Ming Dynasty, but the electric hair is in the body, and the structure is clear. The postscript 1220062 V. Description of the invention (7) The method is an undoped silicon formed by chemical vapor deposition at subnormal pressure. The glass layer replaces the traditional liquid silicon dioxide and reduces the protective layer from four layers to three layers, which not only reduces the production cost, but also solves the conventional problems of 0-ΐ: i me and re-solidification, so it has The advantages of simplified process and reduced production cost. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the appended patent application. Participate

TW0462F (Wanghong) .ptd Page 12 1220062 Brief description of the drawing [Simplified description of the drawing] Fig. 1 shows a cross-sectional schematic diagram of two layers of metal interconnections of the integrated circuit; Figs. 2A to 2E show a kind of The conventional and 3A to 3D drawings illustrate a manufacturing method according to the present invention. Description of formula code] 101: Substrate $ 130 103: MOS transistor layer 105: First metal line 107: Inner metal dielectric layer 109, 2 0 3, 30 3: Second gold 11 1: Plug 202, 3 0 2: base material 204, 304: silicon nitride layer 206: silicon dioxide layer 208, 308: silicon oxynitride J 1 210: scale glass layer 306: undoped silicon glass layer

IH

TW0462F (Wanghong) .ptd Page 13

Claims (1)

1220062 6. Scope of patent application 丨 · A method for manufacturing a passivation of integrated circuits, including the following steps: providing a substrate, wherein a metal interconnect has been formed on the substrate; A silicon nitride layer (SiN layer) is formed on the material; an undoped stone glass layer (^ A u SG layer) is formed on the A nitride stone layer; and a layer is formed on the undoped silicon glass layer A silicon oxynitride layer (SiON) is formed thereon. The metal interconnect of the manufacturing method described in item 1 of the scope of patent application is a second metal wire. ^ 3 · Manufacturing as described in item 1 of the scope of patent application Method, wherein the nitrided layer has a characteristic of being transparent to ultraviolet light (UV). 4. The manufacturing method according to item 3 of the scope of patent application, wherein the ultraviolet light (UV) of the nitrided layer is The transmittance is preferably about 70 ° /. ~ 80 ° /. 5. The manufacturing method as described in item 1 of the scope of patent application, wherein the thickness of the rat fossil layer is about 400. A (angstrom) 6 · The manufacturing method described in item 1 of the scope of patent application, which The non-doped silica glass layer is formed by Sub-Atmosphere CVD. 7 · The manufacturing method described in item 6 of the scope of patent application, wherein the undoped silica glass layer It is formed under a pressure range of about 200 to 400 torr. 8 · The manufacturing method described in item 1 of the patent application range, wherein the thickness of the undoped silica glass layer is about 70 0 (angstrom). TW0462F (Wanghong) .pt (1 Page 14 1220062 6. Application for patent scope 9 · The manufacturing method as described in item 1 of the patent scope, wherein the oxynitride layer is made by plasma chemical vapor deposition method (P 1 asma-Enhanced Chemical Vapor Deposition, PECVD). 10. The manufacturing method as described in item 1 of the scope of patent application, wherein the thickness of the nitrogen hafnium fossil layer is about 9000 A (angstrom). The circuit protective layer is formed on a substrate having a component, and includes: a silicon nitride layer (SiN layer) formed on the substrate; an undoped silicon glass layer (SAUSG layer) formed on the nitride On a silicon layer; and a silicon nitride oxide layer (SiON layer) is formed on the undoped silicon glass layer. The integrated circuit protective layer according to item 11 of the patent application scope, wherein the nitride The silicon layer has the property of being transparent to ultraviolet light (UV). 13. The integrated circuit protective layer described in item 11 of the scope of patent application, the thickness of the silicon nitride layer is about 4000a (angstrom ). 1 4 · The product described in item 11 of the scope of patent application Circuit protection layer, the thickness of the undoped stone glass layer is about 7000A (angstrom). 15. According to the integrated circuit protection layer described in item 11 of the patent application scope, the thickness of the silicon oxynitride layer is about 9 0 0 0A (angstrom). TW0462F (Wanghong) .ptd Page 15