594893594893
【發明所屬之技術領域】 本發明係有關於一種半導體之晶圓級封裝，特別係有 關於一種具有應力吸收膜之晶圓級封裝方法。 【先前技術】 習知晶圓級封裝〔wafer level package〕係在晶圓 型態完成複數個晶片之封裝製程，方切割為晶圓級晶片尺 寸封裝結構〔chip scale package, WLCSP〕，本國專利 公告第5 1 1 2 6 7號係揭示有一種晶圓級封裝結構，其係在矽 晶圓之每一電極形成有複數個導體柱，並在該些導體柱上 連接導電凸塊墊片，該些導體柱與該些導電凸塊墊片係埋 設於一絕緣保護層，然而該絕緣保護層係用以缓衝應力， 應當具有適當之厚度，使得細長之導體柱形成困難，實際 上使用電鍵或沉積技術均難以在該絕緣保護層之高深溝比 細孔完成細長導體柱，同時該些剛性金屬材質之導體柱本 身係不具有應力吸收之功效，當導體柱變形斷裂時將導致 電性斷路或阻抗增加，造成電性連接失敗。 本國專利公告第506 0 97號「晶圓級晶片尺寸封裝製 程」係揭示有另一種習知之晶圓級封裝製程，其係在一晶 圓上先配置多個第一銲球，在迴銲後，形成一包覆該些第 一銲球之應力緩衝層，在研磨暴露出第一銲球後，將多個 第二銲球配置在第一銲球上，該些第二銲球係作為該晶圓 之晶片凸塊，此一製程需要將該應力緩衝層塗佈在已形成 有第一銲球之晶圓非平整表面，在印刷或其它塗佈過程因 碰撞易使第一銲球脫落，且不易控制該應力緩衝層之厚[Technical field to which the invention belongs] The present invention relates to a wafer-level package for a semiconductor, and more particularly, to a wafer-level package method having a stress-absorbing film. [Prior technology] The conventional wafer level package [wafer level package] is a packaging process that completes a plurality of wafers in a wafer type, and is cut into a wafer level wafer size package structure (chip scale package, WLCSP). National Patent Bulletin No. 5 No. 1 1 2 6 7 discloses a wafer-level package structure in which a plurality of conductor pillars are formed on each electrode of a silicon wafer, and conductive bump pads are connected to the conductor pillars. The pillars and the conductive bump pads are buried in an insulating protective layer. However, the insulating protective layer is used to buffer the stress. It should have an appropriate thickness to make it difficult to form a slender conductive pillar. In practice, electrical bonding or deposition techniques are used. It is difficult to complete the slender conductor pillars at the high deep groove ratio of the insulating protective layer. At the same time, the conductor pillars of these rigid metal materials do not have the effect of stress absorption. When the conductor pillars are deformed and broken, it will cause electrical disconnection or increase the impedance. , Resulting in electrical connection failure. National Patent Bulletin No. 506 0 97 "Wafer-Level Wafer Size Packaging Process" discloses another conventional wafer-level packaging process, which is to first arrange a plurality of first solder balls on a wafer, and after re-soldering To form a stress buffer layer covering the first solder balls, and after the first solder balls are exposed by grinding, a plurality of second solder balls are arranged on the first solder balls, and the second solder balls are used as the The wafer bumps of the wafer. This process requires the stress buffer layer to be coated on the non-flat surface of the wafer on which the first solder ball has been formed. The first solder ball can easily fall off due to collision during printing or other coating processes. And it is not easy to control the thickness of the stress buffer layer
第7頁 594893 五、發明說明（2) 度，此外，作為外部電性連接的第二銲球係接合在 銲 球上，ΪΙ要考f互炼問題，且第一銲球本身不具有應力 吸收之·，使彳于该應力緩衝層的應力吸收作用有限。 【發明内容】 π名丨艮 本f明之主要目的係在於提供一種具有應力吸收膜之 晶圓級封裝方法，利用先準備具有感光型B階介電層之銅 猪，其開孔内形成有B階導電膠，以貼附在一晶丄，埶 ==一晶圓之全面應力吸收膜，_作晶圓與 凸塊間全面應力吸收膜之功效。 曰月之次一目的係在於提供一種具有應力吸收膜之 晶圓級封裝方法，利用一柄％釜番制 、 後:、將兮桐電膠構成之全面應力吸收膜，在貼附於晶圓 膜之暫凸塊接塾，達到製程中全面應力吸收 包含=本發明之具有應力吸收膜之晶圓級封裝方法，其係 提供一銅箔； 声俜^ ί右^ f型6階介電層於該銅荡，該感光型8階介電 禮係疋義有複數個凸塊導接區； 形成複數個開孔於該感光型β階介電層之凸塊導接 區’以貫通至該銅箔； ^成一Β階導電膠於該感光型Β階介電層之該些開孔； 曰，供一半導體晶圓，該晶圓包含有複數個晶片，每一 糸/、有主動表面及一非主動表面，該些主動表面係 第8頁 594893Page 7 594893 V. Description of the invention (2) degrees. In addition, the second solder ball, which is an external electrical connection, is bonded to the solder ball. The problem of mutual refining must be considered, and the first solder ball itself does not have stress absorption. In other words, the stress absorption effect of the stress buffer layer is limited. [Summary of the Invention] The main purpose of the π name 丨 gen f is to provide a wafer-level packaging method with a stress absorbing film. A copper pig with a photosensitive B-stage dielectric layer is first prepared, and a B is formed in the opening. High-grade conductive adhesive, which is attached to a crystal wafer, 埶 == a wafer's comprehensive stress absorbing film, which is used as a comprehensive stress absorbing film between the wafer and the bump. The purpose of the second month is to provide a wafer-level packaging method with a stress-absorbing film, which is made by using a handle, and then: a comprehensive stress-absorbing film composed of Xitong electric glue is attached to the wafer The temporary bumps of the film are connected to achieve full stress absorption in the manufacturing process. Including the wafer-level packaging method with a stress absorption film of the present invention, which provides a copper foil; 俜 ^ right ^ f-type 6-level dielectric layer In the copper ring, the photosensitive type 8-level dielectric system has a plurality of bump conductive regions; a plurality of openings are formed in the conductive bump regions of the photosensitive β-level dielectric layer to penetrate to the Copper foil; forming a B-stage conductive adhesive in the openings of the photosensitive B-stage dielectric layer; that is, for a semiconductor wafer, the wafer includes a plurality of wafers, each of which has an active surface and a Inactive surfaces, these active surfaces are on page 8 594893
形、 I蔓層以及露出於該護層之複數個銲墊； # ^ = ^附/亥感光型B階介電層至該晶圓之主動表面，使得 =^彻I電膠對應於該些鲜塾，並熱固化該感光型β階介 ^階導電膠，以構成一熱固性結合於該晶圓之應 力吸收膜； 接塾=該銅箱’以形成在該些已熱固化導電膠上之凸塊 形成複數個凸塊於該些凸塊接墊。 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之具有應力吸收膜之晶圓級封裝方法，請參 閱第1圖’首先準備一銅箔1 〇，然後，在該銅箔i 〇上以印 刷或黏貼形成一感光型B階介電層2 〇，該感光型b階介電層 20係以一預定光罩定義有複數個凸塊導接區，其對應於晶 圓之銲墊分佈〔圖未繪出〕，該感光型B階介電層2 〇係包 含有〔負〕光阻劑、低介電高分子材料〔如聚亞烯胺〕 〔低於3· 0K〕及低膨脹係數填充粒子〔f丨ner〕〔如矽氧 物〕等等，該感光型B階介電層20之形成厚度約在100# m，較佳地，該感光型B階介電層20係具有一小於30 °C之玻 璃態轉換溫度〔glass transition temperature，Tg〕， 以提供用以貼附晶圓之低溫熱黏合性。 請參閱第2圖，利用曝光顯影技術對該感光型B階介電 層20形成複數個開孔2 1於該些凸塊導接區，而不需要額外 光阻劑，該些形成後之開孔21係貫通至該銅箔1 〇，較佳Shape, I layer, and a plurality of pads exposed on the protective layer; # ^ = ^ Attached / Hai photosensitive B-stage dielectric layer to the active surface of the wafer, so that = ^ I electrical adhesive corresponds to these Fresh, and heat-curing the photo-sensitive β-order medium-level conductive adhesive to form a stress-absorbing film that is thermosettingly bonded to the wafer; then connected = the copper box 'to form the heat-cured conductive adhesive The bumps form a plurality of bumps on the bump pads. [Embodiment] With reference to the drawings, the present invention will be described by the following embodiments. According to the wafer-level packaging method with a stress-absorbing film according to the present invention, please refer to FIG. 1 'a copper foil 10 is prepared first, and then a photosensitive B-stage dielectric is formed on the copper foil i 0 by printing or pasting. Layer 2 0. The photosensitive b-stage dielectric layer 20 is defined by a predetermined mask with a plurality of bump-conducting regions, which corresponds to the pad distribution of the wafer [not shown]. The photosensitive B-stage dielectric layer 20 The dielectric layer 20 is composed of a [negative] photoresist, a low-dielectric polymer material [such as polyalkyleneamine] [less than 3.0K], and a low expansion coefficient filled particle [f 丨 ner] [such as silicon oxide The thickness of the photosensitive B-stage dielectric layer 20 is about 100 # m. Preferably, the photosensitive B-stage dielectric layer 20 has a glass transition temperature of less than 30 ° C [glass transition temperature (Tg) to provide low temperature thermal adhesion for attaching wafers. Referring to FIG. 2, a plurality of openings 21 are formed in the photosensitive B-level dielectric layer 20 using the exposure and development technology in the bump conductive regions without additional photoresist. The hole 21 is penetrated to the copper foil 10, preferably
第9頁 594893 地，该些開孔21係為等距格狀陣列〔same pi tch array·〕，請再參閱第3圖，以印刷及乾燥方式形成一匕階 導電膠30於該感光型B階介電層2〇之該些開孔21，該b階導 電膠30係包含有如環氧物、$亞烯胺等熱固性樹脂以及如 銀粉等導電粒子，#導電粒子係粒徑約在數微米，亦可為 奈米級導電粒子〔小於i微米〕，較佳地，該B階導電膠3〇 係具有一小於30°C之玻璃態轉換溫度〔glass transiti〇n temperature，Tg〕，以提供用以貼附晶圓之低溫熱黏合 生因此以該銅Ά 1 〇作為該感光型B階介電層2 0與該B階導 電膠3 0之暫時性製程承載件。 请參閱第4圖，貼附該具有β階導電膠3〇之感光型B階 2電層20至一晶圓4〇，該晶圓4〇包含有複數個晶片，每一 晶片係具有一主動表面41及一非主動表面42，該些主動表 面41係形成有一如習知氮化矽〔siHc〇n以七“心〕、氮 氧化矽〔silicon-oxy — nitride〕或碳化矽〔siHc〇n carbon〕之”蔓層 43〔passivation layer〕以及露出於該 濩層43之複數個銲墊44，較佳地，該些銲墊44係為重分佈 銲，，而該感光型B階介電層20與該B階導電膠3〇係貼附於 該^圓40之主動表面42，使得該些b階導電膠3〇對應於該 些銲墊45，由於該感光型B階介電層2〇係具有低溫熱黏結 眭〔不大於8 0 C〕，以黏貼於該晶圓4 0，並熱固化該感光 型B階介電層20與該B階導電膠30，分別形成二已熱固化介 電層22及已熱固化導電膠31，使得該已熱固化介電層22與 已熱固化導電膠31係具有低模數以及低於3〇之玻璃轉移On page 9, 594893, these openings 21 are equidistant grid arrays [same pi tch array ·], please refer to FIG. 3 again to form a dagger-shaped conductive adhesive 30 in the photosensitive type B by printing and drying. The openings 21 of the step dielectric layer 20, and the b-stage conductive adhesive 30 series include thermosetting resins such as epoxy, aryleneamine, and conductive particles such as silver powder, and the #conductive particle system has a particle size of about several microns. It can also be nano-scale conductive particles (less than i microns). Preferably, the B-stage conductive adhesive 30 has a glass transit temperature (Tg) of less than 30 ° C to provide The low-temperature thermal adhesive used to attach the wafers therefore uses the copper alloy 10 as a temporary process carrier for the photosensitive B-stage dielectric layer 20 and the B-stage conductive adhesive 30. Please refer to FIG. 4. Attach the photosensitive B-stage 2 electrical layer 20 with β-stage conductive adhesive 30 to a wafer 40. The wafer 40 includes a plurality of wafers, and each wafer has an active chip. Surface 41 and a non-active surface 42. These active surfaces 41 are formed with a conventional silicon nitride (siHcon with seven "hearts", silicon-oxy-nitride or silicon carbide [siHc〇n carbon ”, a“ passivation layer ”, and a plurality of bonding pads 44 exposed on the ply layer 43, preferably, the bonding pads 44 are redistribution bonding, and the photosensitive B-stage dielectric layer 20 The B-stage conductive adhesive 30 is attached to the active surface 42 of the circle 40, so that the b-stage conductive adhesive 30 corresponds to the pads 45. Because the photosensitive B-stage dielectric layer 20 is It has a low-temperature thermal bonding 眭 (not more than 80 C) to adhere to the wafer 40 and thermally cure the photosensitive B-stage dielectric layer 20 and the B-stage conductive adhesive 30 to form two heat-cured dielectrics, respectively. The electric layer 22 and the heat-cured conductive adhesive 31 make the heat-cured dielectric layer 22 and the heat-cured conductive adhesive 31 have a low modulus and a glass transition of less than 30. shift
594893 五、發明說明（5) 溫度〔glass transition temperature, Tg〕，以構成一 熱固性高分子材料應力吸收膜，該應力吸收膜係因Tg小於 30 °C而能在熱循環測試溫度範圍内處於橡膠態〔rubbery state〕足以吸收應力，且該已熱固化導電膠31係具有小 於3.0GPa揚氏係數，故該已熱固化介電層22與該些已熱固 化導電膠3 1均為具有良好應力吸收性以構成一熱固性結合 於該晶圓4 0之全面應力吸收膜。 請參閱第5圖，之後，蝕刻該銅箔丨0，以形成在該些 已熱固化導電膠3 1上之凸塊接墊丨丨，該些凸塊接墊丨丨係形 成於該已熱固化介電層22且與對應之已熱固化導電膠31電 性導通，並請參閱第6圖，以無電極電鍍技術在該些凸塊 接塾11形成-錄—金〔Ni/Au〕電鍍層12，以利凸塊5〇之接 2參閱第8圖，以印刷或是植球方式將複數個 該些凸塊接塾11，較佳地，更包含有一迴銲 個免用底膠〔〇W〕Η，並經晶圓單離切割步驟，以製得複數 底膠〔underfllling〕之覆晶型晶圓級晶片尺寸封 因此，I*、+、 中’除了已熱固二膜之晶圓級封裝方法 凸塊接墊11之庳六r 『22應力吸收性，凸塊50作用於 收，故本發明係二u化導電膠31有效呢 速封裝方法。 種具有全面應力吸收膜之晶圓級快 為準’任何熟1: ί J :::後：之申請專利範圍所界定者 、技*者，在不脫離本發明之精神和範 1 第11頁 594893 五、發明說明（6) 圍内所作之任何變化與修改，均屬於本發明之保護範圍。594893 V. Description of the invention (5) Temperature [glass transition temperature, Tg] to form a thermosetting polymer material stress absorption film, which can be in the rubber in the temperature range of thermal cycle test because Tg is less than 30 ° C The rubbery state is sufficient to absorb stress, and the heat-cured conductive adhesive 31 has a Young's coefficient of less than 3.0 GPa. Therefore, the heat-cured dielectric layer 22 and the heat-cured conductive adhesives 31 have good stress. The absorptivity forms a comprehensive stress-absorbing film that is thermoset bonded to the wafer 40. Please refer to FIG. 5. After that, the copper foil 丨 0 is etched to form the bump pads on the heat-cured conductive adhesive 31, the bump pads are formed on the heat The dielectric layer 22 is cured and electrically connected to the corresponding thermally-cured conductive adhesive 31, and referring to FIG. 6, electrodeless plating technology is used to form the bumps 11 on the bumps 11-plating-gold [Ni / Au] plating The layer 12 is to connect the bumps 50 to 2 as shown in FIG. 8. The plurality of bumps are connected to the bump 11 by printing or ball-planting. Preferably, a solder-free primer is also included. 〇W] Η, and through the wafer single singulation step, to obtain a flip-flop type wafer-level wafer-level wafer size seal. Therefore, I *, +, and 'except for the crystals that have been thermoset two films Round-level packaging method 26 of the bump pad 11 "22 stress absorption, the bump 50 acts on the receiver, so the present invention is an effective fast-speed packaging method for the binary conductive adhesive 31. A wafer-level device with a comprehensive stress-absorbing film will prevail. Anyone who is skilled in the 1: 1, J ::, and post-application scope, without departing from the spirit and scope of the present invention, page 1 594893 V. Description of the Invention Any changes and modifications made within the scope of (6) shall fall within the protection scope of the present invention.
第12頁 594893 圖式簡單說明 【圖式簡單說明】 第1至7圖：依本發明之具有應力吸收膜之晶圓級封裝方 法，一晶圓在各步驟中之部份截面圖。 元件符號簡單說明：Page 12 594893 Brief description of the drawings [Simplified description of the drawings] Figures 1 to 7: According to the wafer-level packaging method of the present invention with a stress absorption film, a partial cross-sectional view of a wafer in each step. Simple explanation of component symbols:
10 銅f白 11 凸塊接墊 12 電鍍層 20 感光型B階介電層 21 開孔 22 已熱固化介電層 30 B階導電膠 31 已熱固化 導電膠 40 晶圓 41 主動表面 42 非主動表面 43 護層 44 銲墊 50 凸塊10 Copper f white 11 Bump pad 12 Plating layer 20 Photosensitive B-stage dielectric layer 21 Opening hole 22 Thermally cured dielectric layer 30 B-stage conductive adhesive 31 Heat-cured conductive adhesive 40 Wafer 41 Active surface 42 Non-active Surface 43 Cover 44 Pad 50 Bump
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