594784 五、發明說明（1) % 9月領域： 種I本發明係有關於一種非揮發性記憶體電路，特別是一 大=有較佳讀取時間效果之參考記憶胞電路以提供感測放 器比較的參考電流，用以決定非揮發性記憶體儲存邏輯 發明背景：594784 V. Description of the invention (1)% Field of September: The present invention relates to a non-volatile memory circuit, especially a large = a reference memory cell circuit with a better reading time effect to provide a sensing amplifier. A reference current for the comparison of the controller to determine the non-volatile memory storage logic. BACKGROUND OF THE INVENTION:
近年來，行動電話和膝上型電腦的發展帶動半導體積 體電路没叶與技術的快速發展。低功率，高密度與可以重 複讀寫之記憶體無疑的是快速發展的市場最亮麗的明星。 而其中由許多位元組所構築之一個位元組一個位元組可電 抹除之唯讀記憶體（EEPROM)雖是明星產品之一，不過由於 其記憶胞太大而不實用，這使得快閃記憶體挾其僅需較小 的尺寸並且具有高度的可信賴性的優勢而成為另一候選 者。對於習知技術如何對快閃記憶體資料讀取之過程，我 們將佐以圖示來加以說明。In recent years, the development of mobile phones and laptop computers has driven the rapid development of semiconductor integrated circuits and technology. Low-power, high-density and repeatable memory are undoubtedly the brightest stars in the fast-growing market. Among them, a byte-by-byte electrically read-only memory (EEPROM) constructed by many bytes is one of the star products, but because its memory cells are too large and impractical, this makes Flash memory is another candidate because it requires the smaller size and has the advantage of high reliability. How the conventional technology reads the flash memory data will be illustrated with illustrations.
圖一示一讀取傳統快閃記憶體胞資料儲存狀態的功能 方塊示意圖。它包含了一參考記憶胞陣列（r e f e r e n c e cel 1 array ) 1 0，中的兩個參考記憶胞i 5a、i 5b，分別在 偶數列與奇數列，用以提供一參考電壓，以比較正規記憶 胞陣列（normal cel 1 array) 40中的兩個記憶胞45a或45b J^/04 五、發明說明（4) 憶 新的設計 有鑑於此，本發明將對I 以改善上述讀取時間長的問題 發明目的及概述： 鑒於上述之發明背景中 係提供一種改善分閘快閃參^本發明之一目的 time)之參考記憶胞電路。° ‘忌匕-貝時間（access 本發明揭露一種改善分問体 參考記憶胞電路，用以提供正、—、二％胞讀取時間之 比較，由於係以奇數列參考f愔^ =胞項取時參考電流之 比較電流，偶數列參考記恃月d奇數列正規記憶胞 電流，因此，在相同製程條侔 見圯隐肊比較 高。 ％件下，比較電流之可靠度提 本發明之參考記憶胞電路$小 胞及偶數列參考記憶胞，偶數二=3"數列參考記憶 考記憶胞共用一源極線：：：憶胞與該奇數列參 考記憶胞之各別浮置間㈣^數列參考記憶胞與偶數列參 之汲極則連接於比較』之-相同電壓源vcc’各別 胞讀取時邏輯狀能;輸入鸲，以提供參考電流供記憶 考記憶胞之控刹；;^斷，—控制信號直接連接奇數列參 數列參考記憶⑯：以杵：：二：信號經-反相器連接於偶 &制八開啟。因此，控制信號電壓位 594784 五、發明說明（5) --- — 準為1>或^0時，將可令上述其中之一種參考記憶胞輸出電流 至比較器之輸入端。 *本I明之另一貫施例中，除了偶數列參考記憶胞與該 可數列參考記憶胞共用一源極線，奇數列參考記憶胞與偶 數列參考記憶胞之各別浮置問極連接於—相同電壓源 VCC ’同時各別之控制閘極也連接至電壓源vcc，以使得參 考圮憶胞在準備就緒狀態。此外奇數列參考記憶胞與偶數 列參考記憶胞汲極各連接一電晶體做為開關，由一控制信 號直接連接或經反相器再連接於上述電晶體閘極，以決定 由偶數列參考記憶胞或奇數列參考記憶胞輸出電流。 發明詳細說明： 一如在發明背景所述，傳統方法之參考記憶胞浮置閘 極與控制閘極雖然相連接，但由奇數列參考記憶胞切換至 偶數列參考記憶胞或偶數列參考記憶胞切換至奇數列參考 吕己憶胞時’將有讀取時間（a c c e s s t i m e )長的問題，主要 係浮置閘極具有高阻抗的特性。本發明可改善上述的問 題。 本發明提供的改善方法，請參考圖三所示的示意圖。 如同圖二所示之的參考記憶胞。偶數列參考記憶胞 (reference cell) 34 0提供偶數列正規記憶胞（normal 594784 五、發明說明（6) ce 1 1 )比較電流。奇數列參考記憶胞33〇提供奇數列正規記 憶胞比較電流。一控制信號XARD [ 〇 ]經反相器3 2 0後連接至 偶數列參考記憶胞3 4 0之控制閘極3 4 0 A，同時控制信號 XARD[ 0 ]也連接至奇數列參考記憶胞33〇之控制閘極33〇a。 並由控制信號XARD [ 0 ]輸入的電壓位準決定是奇數列參考 記憶胞3 3 0作用（act i vated)或者偶數列參考記憶胞340產 生作用。 請注意，與傳統參考記憶胞（圖二所示）極大差異點為 奇數列參考記憶胞3 3 0及偶數列參考記憶胞340之浮置閘極 3 3 0B、34 0B同時連接至一電壓源VCC。因此，不管是奇數 列參考記憶胞3 3 0之控制閘極3 3 0A在作用狀態或偶數列參 考記憶胞340之控制閘極34 0A在作用狀態。浮置問極 / 3 3 0B、340B始終在VCC電壓的準備就緒位置。如此，發明 背景所述的問題（浮置閘極慢速拉升電壓至vcc電壓）將不 存在。 、 本發明之第二實施例請參考圖四所示的示意圖。圖四 之設計與圖三設計有相類似的概念，即浮置閘極43 0B、 440B電壓始終維持在VCC電壓的準備就緒位置。不只如 此，控制閘極43 0A及控制閘極440A電壓也同時維持在vcc 的電壓位準。奇數列參考記憶胞43〇與偶數列參考記愤胞 ‘“是否輸出電流係由輸入信號乂…”㈧所控制之電曰^體已 435及電晶體445所決定。當XARD[0]端以位準為電壓Figure 1 shows a block diagram of a function for reading the storage state of traditional flash memory cell data. It contains a reference memory cell array (reference cel 1 array) 1 0, two reference memory cells i 5a, i 5b, in even and odd columns, respectively, to provide a reference voltage to compare regular memory cells Two memory cells 45a or 45b in an array (normal cel 1 array) 40 J ^ / 04 V. Description of the invention (4) In view of this, the present invention will improve the problem of long reading time by using I in the present invention. Object and Summary of the Invention: In view of the above background of the invention, a reference memory cell circuit is provided to improve the opening and closing flash parameters (time, one of the objectives of the present invention). ° 'Dagger-shell time (access) The present invention discloses an improved reference memory cell circuit for providing a comparison between positive, negative, and two-percent cell read times, since the reference is f 奇 ^ = cell term The comparison current of the reference current at the time of taking, the reference current of the even-numbered column, and the regular-memory cell current of the odd-numbered column. Therefore, it is relatively high in the same process bar. The reliability of the comparison current is referred to the reference of the present invention Memory cell circuit $ small cell and even-numbered reference memory cell, even number two = 3 " number-reference memory test memory cell shares one source line ::: memory cell and the respective floating reference cell of the odd-numbered reference memory cell ^^ The reference electrode of the series reference memory cell and the drain of the even number reference are connected for comparison "-the same voltage source vcc 'each cell reads the logical state energy; input 鸲 to provide a reference current for the memory test memory cell control brake; ^ Break, the control signal is directly connected to the odd-numbered parameter parameter reference memory. ⑯: with a pestle :: two: the signal is connected to the even & system through the -inverter. Therefore, the voltage of the control signal is 594784. V. Description of the invention (5 ) --- — quasi 1 & When gt; or ^ 0, one of the above reference memory cells can output current to the input terminal of the comparator. * In another consistent embodiment of the present invention, except that the even-numbered reference memory cell is shared with the countable reference memory cell One source line, the floating floating poles of the odd-numbered reference memory cell and the even-numbered reference memory cell are connected to the same voltage source VCC 'and the respective control gates are also connected to the voltage source vcc, so that the reference voltage is recalled. The cell is in the ready state. In addition, the odd-numbered reference memory cell and the even-numbered reference memory cell are each connected with a transistor as a switch, which is directly connected by a control signal or connected to the transistor gate through an inverter to It is decided to output the current from the reference memory cell of the even-numbered column or the reference memory cell of the odd-numbered column. Detailed description of the invention: As described in the background of the invention, although the floating gate of the reference memory cell of the traditional method is connected to the control gate, When the reference memory cell is switched to the even-numbered reference memory cell or the even-numbered reference memory cell is switched to the odd-numbered reference Lü Jiyi cell, there will be a long access time (accesstime). The problem is mainly due to the high impedance of the floating gate. The present invention can improve the above problems. For the improvement method provided by the present invention, please refer to the schematic diagram shown in Figure 3. The reference memory cell as shown in Figure 2. Even number Column reference memory cell (reference cell) 34 0 provides an even number of regular memory cells (normal 594784 V. Description of the invention (6) ce 1 1) comparison current. Odd number reference memory cell 33 provides an odd number of regular memory cell comparison currents. The control signal XARD [〇] is connected to the control gate 3 4 0 A of the even-numbered reference memory cell 3 4 0 through the inverter 3 2 0, and the control signal XARD [0] is also connected to the odd-numbered reference memory cell 33 〇 Control gate 33a. And it is determined by the voltage level input by the control signal XARD [0] whether the effect is caused by an odd-numbered reference memory cell 3 3 0 or an even-numbered reference memory cell 340. Please note that the significant difference from the traditional reference memory cell (shown in Figure 2) is the odd-numbered reference memory cell 3 3 0 and the even-numbered reference memory cell 340 floating gates 3 3 0B, 34 0B are connected to a voltage source at the same time. VCC. Therefore, whether the control gate 3 3 0A of the reference memory cell 3 3 0 is in the active state or the control gate 340 0A of the reference memory cell 340 is in the active state. Floating interrogator / 3 3 0B, 340B is always in the VCC voltage ready position. In this way, the problem described in the background of the invention (floating gate slowly pulls up to vcc voltage) will not exist. For a second embodiment of the present invention, please refer to the schematic diagram shown in FIG. The design in Figure 4 is similar to the design in Figure 3, that is, the voltages of the floating gates 43 0B and 440B are always maintained at the VCC voltage ready position. Not only this, the voltages of the control gate 430A and the control gate 440A are also maintained at the voltage level of vcc. The odd-numbered reference memory cell 43 and the even-numbered reference memory cell ‘“ whether or not the output current is controlled by the input signal… ”is determined by the body 435 and the transistor 445. When XARD [0] terminal uses level as voltage
594784 圖式簡單說明 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形倣更詳細的闡述： 圖一顯示依據習知技術以讀取一快閃記憶體時，和參 考記憶胞陣列關係的功能方塊圖。 圖二顯示依據習知技術記憶胞讀取時係分別以奇數列 參考記憶胞和偶數列參考記憶胞提供參考電流。 圖三顯示本發明之方法所設計之第一實施例，參考記 憶胞電路的示意圖。 圖四顯示本發明之方法所設計之第二實施例，參考記 憶胞電路的示意圖。 圖號對照表： 參考記憶胞陣列 1〇 正規記憶胞陣列 40 偶數列正規記憶胞4 5 a 奇數列正規記憶胞 45b 感測放大器 50 比較器 5 0、2 0 0、3 0 0、4 0 0 反相器 2 2 0、3 2 0、4 2 0 奇數列參考記憶胞15b、2 3 0、3 3 0、430 偶數列參考記憶胞1 5 a、2 4 0、3 4 0、4 4 0 〉孚置閘極 230B、 240B、 330B、 340B、 430B、 440B、594784 Schematic illustration of the preferred embodiment of the present invention will be supplemented by the following graphics in the following explanatory text to illustrate in more detail: Figure 1 shows the conventional memory technology to read a flash memory, and reference memory Functional block diagram of cell array relationships. Figure 2 shows that according to the conventional technology, the reference current is provided in the odd-numbered reference memory cell and the even-numbered reference memory cell when the memory cell is read. FIG. 3 shows a first embodiment designed by the method of the present invention, referring to a schematic diagram of a memory cell circuit. FIG. 4 shows a second embodiment designed by the method of the present invention, referring to a schematic diagram of a memory cell circuit. Drawing number comparison table: Reference memory cell array 10 Normal memory cell array 40 Even-numbered regular memory cell 4 5 a Odd-numbered regular memory cell 45b Sense amplifier 50 Comparator 5 0, 2 0 0, 3 0 0, 4 0 0 Inverter 2 2 0, 3 2 0, 4 2 0 Odd column reference memory cell 15b, 2 3 0, 3 3 0, 430 Even column reference memory cell 1 5 a, 2 4 0, 3 4 0, 4 4 0 〉 Fuji gates 230B, 240B, 330B, 340B, 430B, 440B,
控制閘極 230A、 240A、 330A、 340A、 430A、 440A 電晶體435、 445Control gate 230A, 240A, 330A, 340A, 430A, 440A transistor 435, 445