TW594167B - Method for fabricating a thin film transistor liquid crystal display panel - Google Patents

Abstract

First, a scan line, a data line that does not contact with the scan line, and a gate electrode are formed on a substrate using one mask. Thereafter a dielectric layer, a semiconductor layer, and a heavily doped semiconductor layer are formed thereon. A contact hole is etched for connect the data line. A transparent conducting layer is deposited. Then, the transparent conducting layer is defined to form a pixel electrode, a source and a drain. Finally, a passivation layer is formed.

Description

594167 杂 92107814__ 年月 a a correction_ 5. Description of the invention (1) The technical field to which the invention belongs The present invention provides a thin film transistor liquid crystal display (TFT-LCD) panel manufacturing method In particular, it is a method for manufacturing a Tft-LCD panel in which scanning lines and data lines are located on the same plane, so as to avoid the short circuit between the trace / data line staggered area. With the booming development of the electronic information industry in the prior art, the scope of application and market demand for liquid crystal displays (LCDs) has also continued to expand from 'small products' such as electronic sphygmomanometers to portable information products such as personal Digital assistants (PDAs), notebook computers (notebooks), as well as large daytime displays that are likely to be commercialized in the future, can be seen that liquid crystal displays are widely used on them. Because the structure of the liquid crystal display is very thin, short, and has the advantages of low power consumption and no radiation pollution, it is widely used in the above-mentioned people's livelihood and information products. The conventional thin film transistor liquid crystal display basically includes a transparent substrate having a plurality of thin film transistors arranged in an array, pixel electrodes, scan lines on different planes, and scan lines. The data line (data 1 ine), a color filter (color fi Iter), and the liquid crystal material filled between the transparent substrate and the filter, and matched with appropriate capacitors, connection pads, etc.

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t No. 92107SU V. Description of the invention (2) Electronic components to drive liquid crystal pixels to produce rich direct images. However, when manufacturing a thin film transistor liquid crystal display, g = pattern line staggered area or thin film transistor is prone to occur without: ,, 1 and the capital process or human factors that make LCD products the most, 'expected or line defects. Please refer to Figure 1. Figure 1 is a part of the conventional TFT-LCD. The conventional technique uses five yellow light and etching processes (pE ^ j to form a TFT-LCD 10 on a glass substrate. As shown in Figure 1, the scanning lines 18 and data lines 36 of the conventional and transparent TFT-LCf are It is defined in different techniques, and the vertical parent is staggered to a cross over area 14. The thin-film electrical electrodes 32 series are electrically connected to the data line 36, and the thin-film transistor drain electrode 34g is connected through a via hole (via hole) 41 (formed in the conventional fourth pep process) is electrically connected to the pixel electrode 42. "

Please refer to Figs. 2A to E. Figs. 2A to E are schematic cross-sectional views of conventionally making τ F T-L C D. As shown in FIG. 2A, a conventional method for manufacturing a TFT-LCD panel is to first deposit a first metal layer on the surface of a glass substrate 11 and then perform a first yellow light and etching process on the glass substrate 1 1 A gate electrode 16 and a scanning line 18 passing through the staggered region 14 are formed on the surface of the transistor region 12 respectively. As shown in FIG. 2B, a gate insulator 22, a semiconductor layer 24, and a highly doped semiconductor layer are sequentially deposited on the glass substrate 11 in order.

Page 7 594167 _Case No. 92107814_ Year Month Amendment _ V. Description of the invention (3) doped semiconductor layer) 26. Then, a second yellow light and etching process is performed to etch away the doped semiconductor layer and semiconductor layer outside the transistor region 12 to form an active region of the thin film transistor. As shown in FIG. 2C, a second metal layer is then deposited over the doped semiconductor layer and the gate insulating layer, and a third yellow light engraving process is performed to define the pattern of the second metal layer for the transistor. A source 32 and a drain 34 of a thin film transistor are formed in the region 12, and a data line 36 (data line) passing through the interleaved region 14 is defined at the same time. As shown in FIG. 2D, a protective layer 38 made of silicon oxide or silicon nitride is then deposited on the glass substrate 11 and a fourth yellow light and etching process is performed to remove a portion of the thin film transistor 4 4 A protective layer 38 above the drain electrode 34 is formed in the protective layer 38 to form a via hole 41 which reaches the surface of the drain electrode 34, and a part of the drain electrode 34 is exposed. As shown in FIG. 2E, a transparent conductive layer 40 composed of indium tin oxide (IT0) or indium zinc oxide (IZ0) is formed on the glass substrate 11 and is carried out. A fifth yellow light and etching process to form a pixel electrode (pi X e 1 e 1 ectr) 42 which is electrically connected to the drain 34 of the thin film transistor 4 4. From the above, it is known that the manufacturing method of the conventional TFT-LCD panel is a structure in which data lines 36 and scanning lines 18 are alternately arranged on different planes. In addition, in the manufacturing method of the conventional TFT-LCD panel, it is necessary to perform yellow light five times.

594167

The problem is that the thin film transistor liquid crystal display is very easy because of:: affecting production yield ’, and this problem will become more serious when the liquid crystal panel ruler 36 is produced. In particular, the staggered area through which the two Putian lines 18 and 8 pass simultaneously 丨 4 and the transistor area 丨 2 The attached book will be inadequate because of the platform ta P e Γ at the lower scanning line 18 or gate electrode j 6) Good, scan line 18 or under cut phenomenon of gate line, metal rupture phenomenon, and unpredictable existence of semiconductor layer 24 and gate insulation layer u. After the second metal layer is deposited, factors such as various dye particles cause gate-signal shorts between the scan lines 18 and the data lines 36. From the above, it can be known that the traditional panel manufacturing technology cannot be performed in the following steps. Neither the process yield nor the product structure is ideal, and further improvement is needed. In the design of TFT-LCD panels, how to reduce the number of depositions or one pass to avoid the above scan lines Questions such as short-circuiting with the data line, etc., to maintain a certain production yield, have become an important issue in the production of tft_lc. Summary of the Invention The main purpose of the present invention is to provide a thin film transistor liquid crystal liquid crystal (Thin Film Transistor Liquid Crystal Displ). av TFT-LCD) manufacturing method ’The scanning lines and data of the TFT-LCD panel ^ are defined on the same plane’ can prevent the scanning line / data line staggered area from being transmitted ^

594167 ---- Case No. 92107SU_Year Month and Day___ V. Description of Invention (5) Road phenomenon. In addition, the manufacturing method of the TFT-LCD panel of the present invention does not need to deposit a second metal layer, so the process steps can be simplified, and the process efficiency and yield can be significantly improved. In a preferred embodiment of the present invention, a substrate is first provided, the substrate includes at least one pixel region, a transistor region for forming a thin film transistor (TFT), and a scan line / data line staggered region. A metal layer is deposited on the surface of the substrate, and a first photo-etching-process (PEP) is performed. Scanning lines and data lines that are not in contact with the scanning lines are defined on the substrate surface at the same time. A gate of the thin film transistor is formed in the transistor region, and then a gate insulator, a semiconductor layer, and a heavily doped semi conductor are sequentially deposited. layer), and then a second yellow light and etching process is performed to remove the semiconductor layer and the highly doped semiconductor layer outside the transistor region to form an active region (active regi ο η) of the thin film transistor. Then a third yellow light engraving process is performed to form a contact hole in the gate insulation layer, exposing part of the data lines on both sides of the scan line, and then depositing a transparent conducting layer, And fill the contact hole to bridge the data lines on both sides of the scan line. A fourth yellow light and last name engraving process is performed to form a pixel electrode, a source electrode, and a drain electrode, and the data line is connected to the source electrode. Finally, a protective layer is deposited on the substrate. And perform the fifth yellow light and etching process to expose the pixel electrode.

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Because the liquid crystal of the present invention _ + crying, making fen times to give birth to the door on the wrong day production method, the scan line to the face of the yellow light ㈣ ㈣ production process :, and then 明明明 c The traces are not in contact with each other and the metal deposition process material line is less, which can not only reduce the problem, but also further improve the avoidance of short circuits in the wrong area. The embodiment is shown on the clear glass substrate, and the contacts are connected to the source. Conductive Figure 2 'Figure 3 shows the layout of the TFT-LCD system 100 of the present invention = 2. The method is to form a TFT-LCD system 100 on the transparent lens 01 (not shown in Figure 3) by using the yellow light and etching process 15 times. , And iOl may be a quartz substrate or a plastic substrate. As shown in Figure 3, the feature of ^ j is that the scanning lines 102 and data lines 104 of the TFT-LCD are on a plane, and the two are vertically arranged but not connected in the interlaced area 1 1 1 1 = using a L-shaped transparent conductive as shown in the figure The layer u0 passes through the contact hole 138 η transparent conductive layer 130 and is electrically connected to one of the thin film transistors. The pixel electrode 114 is directly electrically connected to the drain electrode 108 of the thin film transistor without passing through any contact holes. Here, the pixel electrode 1 Η and the L-type transparent layer 1 3 2 are defined by the same transparent conductive material. # Α 至 Ε, Figure 4A to Ε are a preferred embodiment according to the present invention—a schematic cross-sectional view of the D panel process along the tangent line AA ′ direction (as shown in FIG. 4A, first, the surface of the glass substrate 100 is comprehensive Deposition No. 594167 Case No. 92107814 V. Description of the invention (7) Metal layer, followed by a first yellow light and etching process, to define the metal layer on the surface of the glass substrate to form a plurality of scanning lines 102 (In area 118), a plurality of discontinuous f-line segments (data line sections or data line strips) that are not in contact with the scanning line, i〇4 (located in area 1 12), and a gate electrode i 〇 6 (Located in the area 丨 i 6 The inner gate electrode 106 is connected to a corresponding scanning line. Each of the material line segments 104 is located between two adjacent scanning lines and is in line with the scanning cat line on the same plane. (See Figure 3). For the convenience of description below, the region 116 is called the transistor region, the region 1 12 is called the contact hole region, and the region i 18 is called the staggered region. In the subsequent process, it is located in a sweep The data line segments 1 0 4 on both sides of the sight line will pass through a staggered area 11 8 The transparent conductive layer and the contact hole are electrically connected to each other to form a scan line and a data line array. The metal layer may be a single metal layer or a multi-layer composite metal layer. If it is ^, it constitutes the The material of the metal layer is composed of chromium, molybdenum or Yankey alloy. The material of the latter is the material of the double-layer composite metal. The first layer is aluminum or aluminum alloy, and the second layer includes an alloy layer of titanium, chromium and molybdenum. Or iron alloy layer.

As shown in FIG. 4B, a gate insulator 124, a semiconductor layer 12 6 and a heavily doped semiconductor layer are sequentially deposited on the glass substrate 101 in this order. 128 ^, and a second yellow light and etching process is performed to etch away the semiconductor layer 1 2 6 and the highly doped semiconductor layer 1 2 8 other than the thin film transistor region 1 1 6 to form an active region. The gate insulating layer 1 2 4 is a single (s i n g 1 e) dielectric layer or a composite

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V. Description of the invention (8) (composite) The dielectric layer is made of silicon oxide (Si OX) and SiNy is still silicon oxynitride (Si OxNy). The semiconductor layer 126 is also called It is an active layer, which is an amorphous silicon layer containing hydrogen, and is used as a channel (cha η ne 1) when the thin film transistor is turned on. The highly doped semiconductor layer 1 The 28 series is used to provide an ohmic contact between the transparent conductive layer 130 and the semiconductor layer 126 to reduce the resistance. As shown in FIG. 4C, the third yellow light and etching process is then performed. A contact hole 1 38 is formed in the gate insulating layer 1 2 4 to expose part of the data lines 1 0 4 on both sides of the scanning line 1 0 2. As shown in FIG. 4D, a transparent conductive layer 1 3 3 is then deposited. The contact hole 1 3 8 is filled, and the transparent conductive layer 130 is used to bridge the data line segments 104 on both sides of the scan line 1 102. Then a fourth yellow light and etching process is performed to define a direct electrical connection The pixel electrode 1 1 4 of the drain 108, the source 1 10, the drain 108, and an L-type transmission through the interleaving area 11 8 and connecting the data line 104 to the source. It is a conductive layer 130. The transparent conductive layer 130 is composed of indium tin oxide (IT0) or indium zinc oxide (IZO). As shown in FIG. 4E, an oxide layer is finally deposited. A passivation layer 132 composed of silicon, silicon nitride, or oxynitride is subjected to a fifth yellow light and etching process to expose the pixel electrodes 1 1 4. In order to further understand the present invention and the conventional technology TFT-LCD manufacturing method

Page 13 594167 _ Case No. 92107814_ Year Month Amendment _ V. For the differences of the description of invention (9), please refer to Figure 5. FIG. 5 is a comparison diagram of the TFT-LCD process of the present invention and the conventional TFT-LCD process. The manufacturing process of the conventional TFT-LCD is described as follows: Step 501: depositing the first metal layer; step 502: defining the scan line and the gate electrode by the first yellow light and etching process; y step 503: continuously depositing the gate electrode Insulating layer / semiconductor layer / highly doped semiconductor layer; Step 5 0 4: Define the active area by the second yellow light and etching process; Step 5 5 ·· Deposit a second metal layer; Step 5 0 6: Take the third The yellow light and etching process defines the data line, the source, the drain, and the channel area; Step 507: deposit a protective layer; Step 5 8 ·· Define the contact hole with the fourth yellow light and etching process; Step 509: Deposit a transparent conductive layer; Step 5 1 0: Define the pixel electrode by the fifth yellow light and etching process; and the manufacturing process of the TFT-LCD of the present invention is described as follows: Step 521: deposit a first metal layer; Step 5 2 2: The first yellow light and etching process defines scan lines, gates, and discontinuous data line segments that are not in contact with the scan lines; Step 5 2 3: Continuously deposit gate insulation layer / semiconductor layer / highly doped semiconductor layer; Step 5 24: Define the active area with the second yellow light and etching process;

594167 _Case No. 92107814_ Revised Year of the Month _ V. Description of the Invention (10) Step 5 2 5: Define the contact hole with the third yellow light and etching process; Step 5 2 6: Deposit a transparent conductive layer; Step 5 2 7 : Define the source, drain, channel area, and day electrode with the fourth yellow light and etching process, and connect discontinuous data line segments through the contact holes; Step 5 2 8: Deposit a protective layer; Step 5 2 9: Define the daylight electrode with the fifth yellow light and etching process;

Compared with the conventional technology, the present invention is to form a scanning line and a plurality of discontinuous data line segments at the same time during the first Huangguangji # engraving process, that is, the scanning line and the data line are on the same plane, and then contact The gate insulating layer 1 2 4 in the cave region 11 2 is engraved with a contact hole 1 3 8 and an L-shaped transparent conductive layer 1 3 0 is used to bridge the data line segments 104 and the thin film on both sides of the scanning line 1 0 2 The source of the transistor is 110, so that not only can reduce a metal deposition process, but more importantly, it can avoid short circuits in the staggered area, thereby improving process efficiency and yield. The above are only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent for the present invention.

Page 15 594167-Case No. 92107814_Year Month Amendment _ Simple Description of Drawings Simple Description of Drawings Figure 1 is a top view of the layout of a conventional TFT-LCD. Figs. 2A to E are schematic cross-sectional views of a conventional TFT-LCD. FIG. 3 is a partial top view of the layout of the TFT-LCD of the present invention. 4A to 4E are schematic cross-sectional views of a TFT-LCD manufactured by the present invention. Figure 5 is a comparison of the TFTLCD manufacturing process of the present invention and the conventional technology. Figure 0 Symbol description 10 TFT-LCD system 11 glass substrate 12 transistor region 14 staggered region 16 gate electrode 18 scan line 22 gate insulation layer 24 Semiconductor layer 26 Two-doped semiconductor layer 32 Source 34 Drain 36 Data line 38 Protective layer 40 Transparent conductive layer 41 Via hole 42 Pixel electrode 100 TFT-LCD system 101 Glass substrate 102 Scan line 104 Data line 106 Gate electrode 108 Drain 110 Source 112 Contact hole area 114 Pixel electrode 116 Transistor area 594167 _Case No. 92107814_ Year and month revision 128 highly doped semiconductor layer 130 transparent conductive layer 1 3 2 protective layer 1 3 8 contact hole 5 0 1 deposit first metal layer 5 0 2 first yellow light and etching process 5 0 3 sequentially deposit gate insulation layer / Semiconductor layer / highly doped semiconductor layer 5 0 4 Second yellow light and etching process 5 0 5 Second metal layer 5 0 6 Third yellow light and etching process 5 0 7 Product of the fourth protective layer 508 etching process channel yellow cum

5 0 9 Deposition of transparent conductive layer 5 1 0 Fifth yellow light and etching process 5 2 1 First metal layer 5 2 2 First yellow light and etching process 5 2 3 Sequential deposition of gate insulating layer / semiconductor layer / Highly doped semiconductor layer 5 2 4 Second yellow light and etching process 5 2 5 Third yellow light and etching process 5 2 6 Deposition of transparent conductive layer 5 2 7 Fourth yellow light and etching process 5 2 8 Deposition Protective layer 5 2 9 5th yellow light and etching process

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Claims (1)

594167 _ Case No. 92107814_ Month and year 1 · A method for manufacturing a thin-film transistor liquid crystal display panel, wherein "person,%" includes the following steps: providing a substrate on which a metal substrate is deposited; and the substrate includes a transistor region, a staggered region, and —Contact 9 holes', where the transistor area forms a thin film transistor; ^ perform a first yellow light and money engraving process, define the metal layer, and define a scan line and two A data line segment located at two f of the scan line and not in contact with the scan line, and the thin film @ sequentially deposits a first dielectric layer, a semiconductor layer and a high doping Semiconductor layer (heavily doped semiconductor layer); performing a second yellow light and etching process to form an active region of the thin film transistor; performing a third yellow light and etching process to form a contact hole in the dielectric layer , Exposing part of the data line segments on both sides of the scanning line; depositing a transparent conducting layer (transparent conducting layer) and filling the contact hole; performing a fourth The photo-lithography process defines a pixel electrode, a source, and a drain, and connects the data line and the source; deposits a second dielectric layer on the substrate; and performs a first Five yellow light and etching processes expose pixel electrodes. Page 18 594167 _Case No. 92107814_ Year Month Amendment_ VI. Patent Application Scope 2. The manufacturing method described in item 1 of the patent application scope, wherein the substrate comprises a glass substrate, a quartz substrate or a plastic substrate. 3. The manufacturing method according to item 1 of the scope of patent application, wherein the first metal layer is a single-layer metal structure, and the material constituting the first metal layer includes chromium (Cr), iron (Mo) or Tungsten indium alloy (MoW alloy). 4. The manufacturing method as described in item 1 of the scope of patent application, wherein the metal layer is a multilayer composite metal structure, and the material constituting the multilayer metal structure contains aluminum (A1) or an alloy containing aluminum as a main component, Copper (Cu) or an alloy containing copper as the main component. 5. The manufacturing method as described in item 1 of the scope of the patent application, wherein the first dielectric layer is used as a gate insulation (GI) layer, and includes oxide silicon oxide (S i 0 x) and nitride Xi (S i N y) or oxynitride (SiON). 6. The manufacturing method as described in item 1 of the scope of patent application, wherein the second dielectric layer is used as a passivation layer and includes silicon oxide, silicon nitride or silicon oxynitride. 7. The manufacturing method according to item 1 of the scope of patent application, wherein the semiconductor layer is an amorphous silicon layer (a-Si layer), a polycrystal silicon layer (polycrystalline silicon layer) or a single crystal layer crystal 594167 _ Case No. 92107814_ Year Month Amendment _ 6. Scope of patent application Single crystal silicon layer. 8. The manufacturing method according to item 1 of the scope of patent application, wherein the highly doped semiconductor layer is used to provide an ohmic contact between the semiconductor layer and the transparent conductive layer. 0. According to item 1 of the scope of patent application In the manufacturing method, the transparent conductive layer is composed of indium tin oxide (IT0) or indium zinc oxide (IZ0). 10. The manufacturing method according to item 1 of the scope of patent application, wherein the data line segment is in the same plane as the scanning line. 11. The manufacturing method as described in item 1 of the scope of patent application, wherein the data line segment and the scanning line are bridged in the staggered area by a transparent conductive layer. 12. The manufacturing method according to item 1 of the scope of patent application, wherein in the second yellow light and etching process, the highly doped semiconductor layer and the semiconductor layer of the staggered region can be retained or removed.