TW591531B - Conditional execution control head in a VLIW processor - Google Patents

Abstract

A VLIW processor for executing a sequence of very long instruction words having a plurality of operations to be executed in parallel. The VLIW processor has a plurality of functional units for parallel execution of the operations specified by the VLIW, an instruction register for holding the VLIW, and a condition flag for indicating the results of a comparison operation. The VLIW includes a conditional head and a plurality of slots, each slot including an operational code and any related operands. The conditional head has a plurality of conditional indicators, each conditional indicator uniquely corresponding to one operation and specifying a condition in which the operation is to be executed if the indicated condition exists. A control circuit is connected to the instruction register and the functional units to deliver the operation from the instruction register to the corresponding functional unit for execution when the condition exists.

Description

591531

FIELD OF THE INVENTION The present invention provides a conditional execution header with a super long pointer. "'= = Character processing." BACKGROUND OF THE INVENTION More and more computer operations require instruction level parallel processing (instruction level). Parallelism (ILp) capable computer means that the computer can execute multiple instructions at the same time, and a very long instruction word (VLIW) processor is a type of processing that can handle such very long instruction characters Super long command character processor is used in super computer (main computer), mainframe (mainframe), or other computers that require high-speed computing. Each super long command character contains multiple fields (fie 1 d), or instruction slot (s 1 ot), each instruction slot is designed to contain only a single instruction, and the instruction contains an action code (opcode) and other related operands (operand ). In general, the number of instruction slots in the extra-long instruction character is related to the machine's architecture and inside the machine, such as arithmetic and logic units (ALU), floating-point arithmetic units (floati ng point unit (FPU) is related to the number of functional units. Each instruction slot corresponds to a specific arithmetic and logic unit or a floating-point arithmetic unit, the arithmetic and logic unit

Page 6 591531

V. Description of the Invention (2) It is used to perform arithmetic operations such as addition, subtraction, and multiplication of integers and Bollinger logic operations, and the floating-point arithmetic unit is used to perform floating-point operations. Due to cost considerations, most of the centers only include a foreign point operation unit. When the Chaoxian # A. Μ1 Waseda A You Changyi 7th day is executed, the foreign point 2 early execution of the corresponding The execution action indicated by the action code in the action slot is 0. The learning cycle order places all the instruction tubes that should refer to a specific value. After finishing the machine, one finger is everywhere. Guan Yuan's managed command line can be executed in a super-long instruction word 7L processor. The super-long instruction character is converted from memory into an instruction pipeline in a ^ machine cycle time. ), The usefulness of the instruction pipeline is known, and the instruction pipeline has been shown to greatly improve the operation speed of the processor's code that contains a series of sequentially executed instructions. There are functional steps related to the execution of the instruction, such as fetching execution operations in a memory. During sequential execution, the next # will be known, and can be converted immediately in the next machine cycle immediately after being converted to the instruction bank. Therefore, although every instruction is possible It takes several stages ^, but once the instruction pipeline is filled, the execution of the finger cycle is completed. 7 '1 However, most of the code also contains, for example, "丨, conditional instructi0n". Such du, and 々 will wait until the execution is complete before they know that the next one will be executed. / Refers to

591531 V. What is (3)? Because a conditional instruction does not know what the next instruction is to be executed, it is almost impossible to fill the instruction pipeline with a series of instructions arranged in a serial manner. Therefore, a conditional instruction will reduce the processor's processing speed. Please refer to Fig. 1. Fig. 1 is a program containing a conditional instruction nif π (line 12) in C language. Fig. 2 shows how a compiler interprets the program in Fig. 1 Converted into a combined language code, please note that the instruction slots between lines 3, 6, and 44 use double straight lines to represent the boundaries between instruction slots. In Figure 2, it is not until the expression (CMPGT R0, 0) on line 32 has been executed that it is' not known to follow 32-> 34- &36; > 38- > 40- > 48 The order back is processed according to the order of 32-> 34-> 42-> 44-> 46-48. The processor determines the instructions to be processed based on the logic of (CMPGT R0, 0). The above-mentioned uncertain situation is called branch delay, and this delay may be caused by the need to clear all instructions in the channel instruction and after the execution of the instructions in line 12 In order to convert the next correct instruction into the instruction pipeline, such an inefficient action is unpleasant for a high-speed processor. There have been many solutions to the above-mentioned branch delay problem. One of them is to predict the most likely instruction to be executed after a one-component instruction according to the execution record of a specific program. For example, if n R 0 π in Figure 2 has always been greater than zero in the past execution records, then when the program reaches line 34, π R 0 π is expected to be greater than zero. Based on such predictions,

591531 V. Description of the invention (4) At the same time as the instructions in line 34 are executed, the instructions in lines 36, 38, 40, and 48 are immediately loaded into the instruction pipeline. If the previous prediction i is correct, the aforementioned branch delay problem can be effectively avoided. However, if the previous prediction is wrong, all existing instructions in the instruction pipeline need to be cleared in order to convert the correct instructions in lines 4 2 '4 4, 4, 6 and 48 to the cleared instruction pipeline. Time, and time is wasted in the process of transferring the correct instruction to the cleared instruction pipeline. The second method to solve the branch delay problem is to load all possible instruction sequences into the instruction pipeline. Each instruction sequence corresponds to a conditional instruction indicated by line 34. result. At this point, all instructions in lines 3 6-48 are converted to the instruction pipeline. Each execution action in the super-long instruction character not only contains an action code and related operands, but each execution action also contains a single-bit or multi-bit flag (f 1 ag). To indicate that the execution action belongs to a particular program branch. Please refer to FIG. 2 again. The flag “value” of each instruction in lines 36 to 40 is set to “1”, which represents the branch “l'f”, and lines 42-46 The flag "value π" of each instruction in the instruction is set to "01", which represents the branch π 〇π. If the conditional instruction (CMPGT R0, 0) in line 32 is "true π, then Only those instructions in the instruction slot containing the flag value `` 1π will be executed. Conversely, if the conditional instruction (CM PG Τ R0, 0) in line 32 is "false", then only Only those instructions in the instruction slot containing the flag value π 0 '' will be executed. Although this method can help the instruction pipeline to remain full, this method requires that each instruction slot in the super-long instruction character is air

591531 Five-out record, description of the invention (5) _ of the predetermined space, the size of the memory is slightly smaller; ^ U stores some flags, and of the predetermined space. ^ Depending on the possible number of program branches during the execution of the 4 program, this method cannot be accompanied by ί. It is not enough to solve the branch delay problem described above. The first execution result, and 篦: silk-times can correctly predict conditional instructions. Each of them is vacated with a predetermined instruction length per-instruction slot. ， T blocking space ’will increase the length of the program. The purpose and outline of the invention / · The main purpose of Ben Maoming is to reduce the jump bar

Qump) to reduce the number of jumps at eight o'clock-stone w ... at eight o'clock to reduce the branch delay in the ultra-long instruction word processor. The second object of the present invention is in the middle batch—the purpose is to avoid increasing the extra memory space required to store the flag of the ultra-long recruiting action. 7 The third purpose of the invention is to enable the super-long instruction characters to be individually controlled. γ mother-instruction ^ The present invention discloses a word processor for executing a very long instruction character, wherein the very long instruction character includes a conditional expression, a conditional execution head (CEX), and a plurality of instructions. Thermal / Ding display

V. Description of the invention (6) When executing multiple executions, the second principle is: = :: two: functional units, which are used for inter-off, and a control circuit, two or two temporary storage states, and a plurality of control opening switches. The control circuit can ^ = ^ The register and the plurality of control conditions control the instruction register indicated by the condition index corresponding to the plurality of open Zs. The register is closed. The condition indicator, each-condition indicator Ϊ =; = The header contains each-control switch line among a plurality of control switches. The plurality of controlled functional units will receive the execution action transmitted from the control opening slot of the control state in the ON state, and the functional unit of the switch of the control switch in the open state will not be ready to receive: = ^ = in The execution action received when the control in the closed state is "performed: execute action # 'and the detailed description of the functional unit invention please refer to Figure-to Figure 3, Figure 1 is a p51 conditional instruction nif" + The content written by j Ch Lu contains a description of how to replace the program in Figure 1, 22 a super-long instruction character compiler-super-long instruction characters. -Combined language ^ How to transfer the program in Figure- to the power unit according to the present invention. _L 列 的 J 理 $: 疋: The functional unit that can be transmitted from the instruction slot to the function will receive "two 2", which is opened when the control is in the open state.

Page 11

Note (7) Lines 6, 2, and 4 of the plural f1 correspond to a super-long instruction character, respectively: column, or "command slot". In Figure 3, each-command slot is :: Action: Separately, each instruction slot contains-execute an action, execute an action code and any related operands. Please ^ Execution: The jumps in lines 34 and 40 in Chinese are no longer shown in Figure 3. Branches will be delayed on the line, however, the "instructions will not skip lines, so I can increase the processing of I condition i :: 口 ： CEU.C『 C 』C” The four 丨 I characters in the super long instruction characters f j2 under one bar include four instructions, 鈇 ^, line. Although the number of super long fingers in line 62 is usually two = one super long command character can be two. The amount of command i in the command character is different. The present invention is not limited to the super: The CEX instruction is usually after the action is performed, as the result of the 60th comparison is performed by comparison. Just like the conventional super "1 ,, (True) or ,, 0" (bird = after the work in the target register is executed, than). The condition flag is set to page 12. V. Description of the invention (8) When the ancients in line 6 and 2 are loaded, each such as, for example, Γ · C ”is loaded into an instruction register. Flags) will directly correspond to an instruction bar ^ indicator (also known as a bit 'component flag is set to "i". Perform this order if and only if the corresponding action is performed i 4 a /, Indicator π · Nc ”means to execute " ο”. Therefore, if the condition flag is set as the standard is set as " 丨 == the comparison result is ', true' and the condition flag ^ Λ ΛνΓ / Λ ^ χ * c · c; NC · NC € ^ ^ ^ line, and the first instruction in the extra-long instruction character will be executed. Therefore, the corner of the invention: jf: instruction Will not be executed twice, and make the "^" execution standard μ reduce the conditional execution of the invention in the program ;:-the case is full load. In addition, the length of this order, so ϋ will not be as The prior art generally increases each finger and does not take up extra space in the memory. Basic: Yisi is a piece of execution of the ultra-long instruction character processor 73 of the present invention. 8〇Ϊ Command word *, the extra-long instruction character contains-an instruction slot than a plurality of instruction slots 82, 84, 86, and 88, each ^ 5 t contains an instruction that can be executed simultaneously. Ultra-long instruction Character processing ° 85, 87 dagger 3, multiple functional units (functinal units, FU) 83, r action, and 8 9 are used to execute the multiple executions specified by the super long instruction character P 2, ^, and plural Control switches 92, 94, 96, and 98. The control switches 4, 9, 6, and 98 are respectively set in the super-long instruction characters.

Page 13 591531 V. Description of the invention (9) '~'-$ 82, 84, 86, and 88 and corresponding functional units between, 85, 7, and 7 are used to control whether an execution action can be performed From the instruction slots 82, ^ 86, and ⑽ to the function units 83, 85, 87, and 89. The super long finger is processed as 73. It also includes a control circuit 75 for controlling the opening / closing of the switch * /, ^ 6, and 98, and a flag register 77, and the flag "register 7 7 contains a The condition flag # γ β is used to temporarily compare the results of the left and right. The flat flag '76 temporarily stores a comparison and performs an action control switch 9 2, 9 4, 9 6, and 9 8 can be a multiplexer and a lambda crystal. 'Or other devices designed to control in a controlled way—the electronic signal passed through and all belonging to the present invention: In addition, the instruction slots 82, 84, 86, and 88 are shown in ..., but Any two = may | can ... can ... install the actual circuit settings I control the electric power i ^ can load Λyuanyi. To the instruction-order register 79 for execution, it will be temporarily stored in the flag ^ work 1. 稷 several comparators or transistors, etc.) 丨 8. Inner bar: 7 == piece flag 76 and conditional execution header BU, = Ϊ super; instruction slot of instruction characters ... 84, 86 in The condition flag 76 located in the | fruit condition flag is the same as the condition index 80a, 80b, 80c, and 仃 on page 14 of 591531. V. The invention description (ίο) has one or more condition indicators, so as long as it is : =: OK,, and 8_ condition flag 76 is the same ^^ Please also refer to the super index of c in line 62 in Figure 3 ^ The condition indicator for old is ".c. (· Nc. NC " / y sub, here τ. Lei Erding action has set the condition flag to-^, compared to your temple. Because the values of the condition 7fi and the shihanji are the same as the value of the condition indicator 80a, 2: The flag 76 is turned on, and the corresponding control switch 92 is opened, so that the operation channel 75 will instruct the slot 82 to transmit. To the functional unit 83 in preparation for == action, the condition flag 76 can be compared with the rest from 75, and the control circuit is controlled based on the comparison result; =, 80. , 80d Phase 98 on or off. Therefore, at this; 96, and greater than zero, then the instruction slots 82, 844? F If the 60th line of the R0 instruction slot 86, 88 moves 2 = the execution action will be executed, and the other Two CEX long fingers ^^ will not be executed: and ".C. NC" in line 64, because j: dagger, in line 64, the person said: = will be executed, and the instruction slot The order within 84 is said to hold T inside. Actions will be made 4 ;: 之]; Π: "The operation procedure and operation of the above-mentioned embodiment, and round: = · Thousands of flags 76 to indicate a specific execution 591531 V. Description of the invention (11) | Whether the action It will be executed instead, using another flag, register, or value, or even a combination of the three, which is different from the bar 76 to compare the condition indicators 80a, 80b, 80c ', and 80d. The above-mentioned borrowing [adjusts the specific flag, register, or value highly: can: take a specific part of the code to be executed, use for debugging, use = xuyi A single program can be executed in different modes in different situations, = any other purpose. Obviously, the control circuit in this embodiment is the flag, the register, and the input value of the value and conditions Compared with the indicator 80a, I 8 0 b, 80 c, and 8 0 d. Compared with the conventional technology, the present invention can reduce the number of times of f-line skipping during program execution, thereby reducing ultra-long instruction words. Branching delay in the meta processor. In this paper, it is not necessary to occupy very long instruction word lines while reducing the branching delay. The extra bit space of the action can avoid increasing the type & i.t. The present invention can also perform the execution of each execution action. The branch delay caused is often an important factor in the execution speed of the processing processor, and the present invention does provide an effective improvement method. 丨 For example, ΐ i :: i: 运 斤 if flags are just a number of indicators One of them, the register, etc. cited in the subject can also be used as a reference, and the features are also lacking in the known technology. The above is only a preferred embodiment of the present invention. 16 pages 591531

Page 17 591531 Brief description of the diagrams Brief description of the diagrams Figure 1 shows a program written in the C language with a conditional instruction n i f π. Figure 2 shows that the conventional compiler converts the program in Figure 1 into a combined language code. Fig. 3 shows that the ultra-long instruction character compiler of the present invention converts the program in Fig. 1 into a combined language code. FIG. 4 is a hardware architecture diagram of an ultra-long instruction character processor according to the present invention. Explanation of Symbols for Drawings 73 Very Long Instruction Word Processor 75 Control Circuit 76 Condition Flag 77 Flag Register 79 Instruction Register 82 ^ 8 [86 ^ 88 Instruction Slot 80 Conditional Execution Header 83> 85 ~ 87 ^ 89 function unit 92 ^ 94 ^ 96 > 98 control switch

Page 18

Claims (1)

591531 VI. Patent application scope __ ι〇 ^ Long instruction characters, including a conditional execution header (c order to ", this, super ⑽. Two ...) and multiple execution actions: two instruction words multiple functions Unit for executing one-by-one instruction registers simultaneously, including a plurality of instruction slots for temporarily storing the 2 actions; ftf, a plurality of instruction slots for executing actions, the condition g-type execution standard control switches, each control switch is sent To the functional unit; and the second control circuit passed from the berth slot, connected to the instruction register and: made to: according to this, the corresponding two conditions refer to the opening of the 2 switch in JL, 4 Or close (cl〇Se) · condition = = = will not receive to receive 1 = is in the function menu to turn off the switch; at the same time the meeting will execute ㈣ '... the execution received by the early Yuan; ΐ 2 · such as Apply for the extra long instruction character processing described in item 1 of the conditional benefit range. The execution condition of the plural condition indicators in the header is one pair. On page 19, the method of applying for a patent scope corresponds to the super-long instruction character ^ 3. If the patent is applied for-several execution actions, where the execution action is performed by the above action: the super-long instruction character processor, all The execution of the execution. .. ,,, used to indicate that this functional unit will be used !. Also: Please! The scope of the 1st item of the range of interest is confusing # fruit—conditional flag, which is used to indicate that than Λ 令 行 字 动 = 理 ^^ i. 二 = :; [: 项 _ 所 λ… 令 字… 器, as applied凊 The execution action in item $ of the patent scope is executed by the ultra-long instruction character processor of the condition indicator fan. 'When the value of the condition flag is equal to 7. A super-long instruction character is used to execute-an ultra-long instruction character, the super ^ t: a plurality of functional units, which execute a header and a plurality of execution actions, ^ The character ΐ contains a conditional expression J which can only be equal to the number of the plurality of functional units. The number of execution actions The processor includes: Number of summers, the extra-long instruction ^ The instruction register contains multiple gimmicks and The plurality of instruction slots for performing actions, including the execution of the standard ^^, and the scope of patent application " " t, number, condition indicators, the number of condition indicators is equal to the number included in the over 7,7 yuan Number of execution actions, and each condition indicator only corresponds to the moving action, each condition indicator is used to indicate under what conditions the corresponding action t will be executed; enter 2 control switches, use To control whether an execution action can be transferred from the finger to the functional unit, each control switch is connected to a command slot and a functional unit in a one-to-one manner; and off, # ί 路, connect In the instruction Register and said plurality of control when opening the opening 1 = Γ way to perform the operation corresponding to the closed subject to the conditions of execution. 2. When the corresponding execution action does not meet the conditions to be executed, such as 3 persons in the execution scope of the patent application scope item 7 ^. The righteousness is long and the order is executed. The execution action = T code, It is used to indicate the superconducting # 人 玄-占 果 which will be described in item 7 of the patent scope of this functional unit. Lai Mingming compares the execution actions and compares the results. For example, the scope of patent application is item 9 where the execution action recognizes the super long ‘order sub-processor’ of 4 ± 4 and is executed. Condition indicator and the value of the condition flag are equal to the date 591531 VI. Patent application scope 丨 Long instruction characters include a program execution method of 3, the super device, the instruction register includes a plurality of instructions temporary storage and the plurality of execution instructions Slot, once t Μ conditional execution header contains a number of functional units, used for the same as the "execution g" 1 purpose = character processor to include control switches, each control switch is based on-two works, and multiple commands Between a slot and a functional unit, used to control +2 way to connect to a one-finger instruction register is transmitted to the function list ^ = whether the action can be performed from the I to the corresponding execution action is included by the i method : The circuit is turned on, and the control circuit is turned off when the corresponding actuator is executed. Pay 5 conditions for execution 1 2. The super-long instruction character processor described in item 丨 丨 of the patent application scope also includes a condition flag J enforcement, where the comparison result of the execution action. 、 Not used to indicate a comparison 1 3 · As described in item 丨 2 of the scope of patent application, the execution action is based on the condition indicator and the condition flag_2 =, where the line. ‘Silver’ is executed when the values are equal