TW589822B - Ethernet switching architecture and dynamic memory allocation method for the same - Google Patents

Abstract

A dynamic memory allocation method of an Ethernet switching architecture includes providing a plurality of input ports and output ports, a shared memory, a first link RAM (random access memory), and a second link RAM. The second link RAM is employed as a FIFO (first in first out) device in sharing of both get-link and release-link operations. And six packet segments of a packet are linked with the first link RAM by a single linked-list. Accordingly, the transportation port counts and bandwidth can be increased.

Description

589822 V. Description of the invention (1) [Background of the invention The present invention relates to a closing method, and particularly to receiving and transmitting the data through a dynamic configuration to obtain a total of 俾 up to increase the network threshold. The memory dynamics of the Ethernet switching structure is a kind of Ethernet switching structure, which provides an optimized single shared memory for the packet segment switching of the packet during a packet sale process. Purpose of transmission bandwidth. _According to the test, a shared memory packet will be stored in the input port and the received data packet will be stored in this output port. Because of its low cost, usually the main structure of SWITCHING uses a single · common output A 'path of data rece' shared memory, and a path of data, simplified design requirements, and used as the main structure of the regional network.

Same memory organization. iving) allocation and transm implementation (the LAN body is used as the network to reach the appropriate fi 11 in ng via a round-trip packet) 〇 The car is Gu Yi ’s simple configuration method in the Ethernet exchange. Divide a shared delta memory into a plurality of continuous > contiguous data buffers with fixed length (fi xecj — 1 ength) of 2K bytes, and treat the stand as a first-in-first-out (FIFO) device 'To store the packets received from the plural input ports and transmit the packets to the appropriate output port. Although this is convenient in terms of hardware implementation, when the length of the received packet is considerably smaller than the fixed length, the efficiency of using shared memory will be greatly reduced. In the conventional technology ’, in order to solve this problem,

Page 5 589822 V. Description of the invention (2) --- The memory is configured into a plurality of discontiguous data buffers with a fixed length of 256 bytes to store the data received from the complex input port. Packet segments. After the plural packet segments arrive from different input ports, the blank data buffer in the shared memory is assigned to the plural packet segments. At the same time, a link RAM that has a mapping relationship with the shared memory will store the link address (1 inked address) and the link corresponding to the block address where the plurality of packet segments are located. Knot string. By judging the block address, the corresponding link address, and the desired output port of the multiple packet segment, the multiple packet segment will be added to the appropriate output port of the appropriate The output queue (〇utput queue). The output queue represents these packet streams (Streain 0f packets) in the transmission data path waiting to be transmitted to a corresponding output port. Figure 1 shows a conventional Ethernet switching structure. As shown in the figure, a shared memory 10 is configured as a plurality of data buffer blocks 1 and 1 having the same size, which includes: free buffer storage slot (free buffer p〇〇1) 12 and a plurality of designated buffers Area (assign ed buffers) 13, in which the free buffer storage tank 12 stores blank blocks to be assigned to the packet segment 21 to be received, and packets in the plurality of designated buffers 3 that have been read The blank block returned by the segment, and the plural designated buffer area 3, store the packet segments that have been received from the plural input port 20. In addition, the number of link address spaces 31 of a link RAM 30 is configured to be the same as the number of blocks of the shared sigma memory 10, and the link address 33 and the block bits of the shared memory 10 Address 14 is a mapping relationship 15.

589822

wί t! ΓD, the link sequence of the six packet segments of the received packet 3 = the node addresses are # 4, 6, 8, 9, 13 and "in Figure 1, respectively, due to the mapping on memory i. At this point, the six link addresses are the last link positions of the packet segments at 100, 11 and 14 respectively, and 7 & 50, 70, and 90 respectively. See the chain of the first packet segment that is linked to the next received packet = J. Therefore, the link address θ will be marked to the first of the next received packet with a flag 35. The link address of a packet segment # 1 0 | SJ indicates that the block corresponding to the link address # i 4 is the block where the last 2 packets are located. On the other hand, in the chain The link address # of the link on the RAM30 is represented by a dotted line. The link address # 0, 7, n, 12, 15, 3, and 5 are links that are released after a received packet is read. Address space, which corresponds to the white blocks & 5, 15, 25, 35, 45, 55, and 65 in the free buffer storage tank 12 on the shared memory 10, respectively, such link addresses Space for the next packet to be received Used by the link, and its corresponding blank block can be used for packet storage of the next packet to be received. Under the condition of unicast, a packet is transmitted to an output port to which it wants to go. Therefore, each packet segment of a packet with reference to the link sequence 3 4 formed by its link address 3 3 will be inserted into an appropriate corresponding round / out according to the output port 40 to which it is going. On queue 37, the purpose of transmitting the packet from the output port 40 is achieved ^ In the process of receiving and transmitting several packets of a packet in segments, the link RAM will perform the following four steps in order: _Get predicate (get link), that is, in a shared memory to buffer its unused data

589822 V. Description of the invention (4) When the punch block is assigned to the packet segments, the corresponding link address space is found on the link RAM; the second step is to make the link (make link), also That is, the link addresses of the packet segments are concatenated to form a link series; the third step is to read the link (read Hnk), which is the read of the link series; and the fourth step This is called release 1 ink, and the link address space of the read chain sequence is about to be released. The following description will be explained from two aspects of reception and transmission. In terms of reception, the packet segmentation of a packet is obtained through an input port 20 first, and then the available link address space 31 is obtained, and then the packet segmentation 21 is written, and the packet segmentation 21 constitutes a key link. Concatenate ^ and add an output queue 3J '俾 to complete the reception of these packet segments. Fig. 2 is an example of a control flow chart of the Ethernet switching structure of a graphics worker in the process of receiving a packet. Under the auxiliary reference of FIG. 1, it is explained that it includes the following steps: Step 201: Obtain six link address spaces; that is, one input port 20 determines whether the blank link address space on the link ram30 is available for use. i less two 9 six; if yes, continue to obtain the link address empty 1 otherwise skip to step ^ 02 ° step 202 · The input port judges whether it exists-go to step 203 if not, otherwise end. After receiving the packet on the 2nd and 3rd of the evening, the gate Λα was received; that is, the six link addresses obtained from the acquisition (such as # 4 and β 〇 in the mapping area Γ such as ϋ 13 and 14) are shared. The first block of blocks & 50, 70, 90, 100, 140, and 150) on the memory 10 begins to be written.

589822 V. Description of the invention (5) Step m: write the packet information; according to the current link address 33 of the packet segment 21 of the packet on the link RAM 30 (see # 4, 6, 8, 9 in Figure i) , 13 and 14) and their links, and the mapped block address 14 on the shared memory 10 is written into the data of the packet. Step 205: Determine whether the writing of the packet has been completed; if yes, skip to step 208; otherwise, skip to step 206. Step 206: Determine whether the writing of one block has been completed; if yes, skip to step 207, otherwise proceed to the shared memory 1 () ±, and return to step 204. Step 207: Perform a link, and return to step 204, and proceed to the next-block. The link includes: when the completed block is the first-time chain: the next link address is assigned to the current link Address instead of m. When the completed writing block is not the first time, the link address is linked to the previous key address, and the current chain step 208: determine whether the packet is The good address is vacated to the next-to receive the packet and then use 2. If yes, go to step _, no: sufficient buffering the link address space packet on R = receive, and return this key to step 202. Time 31 is given to the next time-to-be-received packet and reused 'Second step 21 0 · Determine whether the packet is the first packet that reaches its output Tan 40; if yes, go to step 212, otherwise skip to step Chuan.

589822 V. Description of the invention (6) Step 2 1 1 · Form a link; that is, put the packet into the output port 40 after the terminal address (taii address) = :. Add the packet in series. Flag of the last link address on the link RAM30 to write this / step 212. · Write the packet to the link ram II r The packet to the link _ ° ^ Tell its output port 4 〇. Which ,,, and port address, and transmission, it is to read the address space of the packet segment where these packets are segmented; == then control the process of transmission of the read chain packet on the output port 4 Figure 1 Second too: The road switching structure is under the seal, and an example of its packet diagram is explained. In the auxiliary reference of FIG. 1 = Step 22G:-Wheel exit port 4 () to determine whether it exists · If yes, go to step 221, otherwise end. The M packet reads its front-end address from the output array 37 of the port 40 (from the money out step 2 ^). 38 to pick up the address of the first block, and proceed to steps 222 and

W222 Read link; that is, sequentially read the link addresses of the link sequence 34 of the packet, and proceed to step 224. A Jia J: Get the packet data; that is, read the packet data according to the current link address 33 of the packet on the chain and the mapping block address 14 on the shared memory 10, and skip Go to step 227. Step 224: Determine whether the key reading of the last block has been completed;

Page 10 V. Description of the invention (7) If yes, skip to step 225, otherwise, step m: judgement = go to step 222. Step 226, otherwise skip to Step 2 ^ is. The next packet to be transmitted; if yes, skip to step 226: Load the address of the benefit area ^ dragon of the last block of the most fragmented packet segment; load the front end address of the round packet, and proceed to step = 7 address' is taken as the next round to be transferred. Step 2 2 7: Judging the pending transfer fails; if yes, proceed to step 22t to transfer the packet. Whether the packet has been read or transmitted. _: Explain :: Judgment. The chain of the segment on the output port is in phase, that is, sequentially release the read packet in half step 90n · ,, key, ,, ° address space 31, and then proceed to step 229. A release has been performed. It is judged whether the link address space 31 on the link RAM 30 has been released by the king, and then returns to step 220, otherwise returns to step 228. As shown in Figure 2 and Figure 3, _ during the process of receiving and transmitting a packet, the packet chain has undergone four steps: obtaining the link, forming the link, reading the link, and releasing the link. It is managed by a link RAM30. In this regard, the time it takes for each packet to be received and transmitted is the time it takes to perform the four bonding steps (4 x clock period (cloc period)) and the number of blocks used (bi 〇ck counts) and the number of port counts. Although, in the 10/100 MB / s Ethernet exchange, 'this kind of link serialization method does not yet limit the required bandwidth', however, in high-speed Ethernet exchange, due to the The transmission time must be less than 672ns (that is, the bandwidth is more than iGb / s), and the number of transmission ports is proportional to the transmission time of the packet, so the number of transmission ports is also limited.

589822 V. Description of the invention (8) " ---- In the method of solving this bandwidth problem, although the system clock frequency has been improved to shorten the transmission time of the packet to increase the bandwidth, However, this will cause problems of poor power consumption and reliability. Therefore, it is necessary to find a method that can achieve multi-port and high-bandwidth Ethernet switching without increasing the clock to a non-permissible range. [Comprehensive description of the invention] One of the objectives of the present invention is to solve the above-mentioned problem that the transmission bandwidth and the number of transmission ports of the Ethernet exchange are limited. Another object of the present invention is to provide a memory dynamic configuration method for an Ethernet switching structure, which can improve the implementation of the transmission bandwidth and allowable increase in the number of transmission ports of an Ethernet parent switch. An Ethernet switching structure of the present invention mainly includes a shared memory, a first link RAM and a second link ram. The two

The Ram system is used as a standard, first-in-first-out, and first-out-first-out table to jointly manage the packet address of a packet into two. When writing to the shared memory, the link address space of its chain is in series. At = the acquisition on the input port, and after the packet segments are read, its chain = the release of the link address space of the chain on the corresponding output port, so that the intraoperative link steps can be used. Time halved. In addition, the link sequence formed by the packet and ^ Γ a link address "writes all the block addresses of the 纴" i segment to the shared memory at a time, so it is read in the constituent chain 2. The time spent linking the Risi Temple has nothing to do with the number of blocks on the shared memory. In this way, the total packet transmission time will be reduced to the product of the clock time and the number of transmission ports. Therefore, in the idle state without improving, we can not only obtain high-frequency performance, but also increase

Page 12 589822

Add its transmission port number. [Detailed description of the preferred embodiment] FIG. 4 is a simple schematic diagram of an Ethernet network in accordance with a preferred embodiment of the present invention, in which the same numerals refer to the structural elements of the reference ^ and there are two main differences: the first Provides-first ", free link RAM50 of mouth structure, and second, provides a better" military first out & knot series "34a. Among them, the number of free bond locations of the free link RAM50—the number of bond links 51 and the link address space 3 of the bond rAM30 are both the same as the number of blocks in the shared memory, And the free link address width 52 of the free bond ram50 is smaller than the link address width 32 of the link RAM30, and its role is to jointly manage a number of packets in a packet and divide it into Q segments. Acquisition and release of its link address space. ° For example, 'the six packet segments of a received packet are stored in the buffer area on the co-dry memory 10, with the buffer addresses & 60, 80, 100, 110, 120, and 140, respectively. The blocks and their corresponding link addresses are, 6, 8, 9, 13 and 14 respectively. In the present embodiment, since the composition and reading of the six packet segment address are “one-time completed”, the link address # 4 of the first packet of the received packet will “link once” ”To the next ^, the link address # 丨 〇 of the first packet segment of the received packet forms one:“ link series 34a. On the other hand, since the free link RAM50 is one ... The memory is first out, so after the packet of the current received packet is read in segments, the released link address # 0, 7, 11, 1, 2, 1, 5, 3, and 5 will be released by the free link. RAM50 is managed sequentially in a first-in, first-out manner.

Page 13 589822 V. Description of the invention (10) Use of the next packet to be received. The buffer block corresponding to the released link address will be released back to the free buffer 12 on the shared memory 10 for storage for the next packet to be received. Fig. 5 is an example of a control flow chart for describing a link formation during a packet receiving process according to the Ethernet switching architecture 'according to a preferred embodiment of the present invention. FIG. 7 is an example of a control flowchart for acquiring a link in FIG. 5 according to the Ethernet switching architecture 'according to a preferred embodiment of the present invention. Here, I control the acquisition link in the conventional technology to be independent, and the free link R A 50 is responsible for management. Therefore, with the auxiliary reference in FIG. 4, the simultaneous acquisition link and packet write are described to illustrate the steps involved: (acquisition link, see FIG. 7) Step 300: determine an input port 20 If the obtained free link address space 51 is less than six; if yes, go to step 3 001; otherwise, go to 302. Step JU1 · The input 珲 20 requests the free link RAM 5 () to 丨, _ free link address spaces 51, and returns to step 3 00. ^ Step 302: Determine whether there is a packet to be received; Yes, step 3 0 0, otherwise end. W step (packet write, see Figure 5) Step 302: Determine whether there is a pending step 303, otherwise end. Seal the dagger, and then proceed to step Step 303: determine whether there is a to, a blank area for the input 20 in the shared memory 10, exempt; if yes, skip to step 304 22

Page 14 589822 V. Description of the invention (11) Abandon the reception of the packet and skip to step 3 02. Step 3 0 4 Receive the packet; receive the packet immediately, and start writing from the blank block, proceed to step 305. Step 305: Write the packet data; write the packet address of the packet on the link RAM 30 on the link RAM 30, and the mapped block address 14 of the packet on the shared memory 10 to write Step 306 of the packet's data line • If yes, skip to; if yes, skip to-address write step 306: Determine whether the packet has been written to step 309, otherwise skip to step 3 〇7 . Step 307: Determine whether the writing of a block has been completed. Step 3 08, otherwise, it will be entered on the shared memory and return to step 305. Step 308: Perform linking; that is, the address of the front link, and the addresses $ 愔 _ 彳 and m are assigned to the target in this share, and the process returns to step 305. Bu & block write step 309: judge the write packet to step 310, otherwise refuse to accept the good packet; if yes, skip back to step link address space 31 to make room for the next frame / dagger, and This link is 302 on RAM30. Wait for the packet to be received and reuse it. Step 310: If the port is judged to be out of port 40, skip to step 311. Otherwise, there will be enough buffers for the talk; End 30 step 302. ,,, ° Reuse the next packet to be received, and go back to step 311 Once $ Block of all packet segments of the packet

589822 V. Description of the invention (12) — ~ ---- =; = 2 notes. The buffer in buffer 13 on memory 10 has been designated. First, I: Λ judges whether the packet is the first packet to reach its output 40, and then proceeds to step 314, otherwise skips to step 313. _〇 step 2 on step 3: = knot; segment the packet on the bond = early-link Chuan Cong 3 on M30 and add it to the end address 4 〇 ° ^ step 314: Write the flag of the packet, and the initial link address (such as # 4) of the packet ^ segment on the link RAM30 to inform the output port. Figure 6 is an Ethernet exchange according to an embodiment of the present invention. Structure, describing the flow of reading the link during the packet transmission process. According to the example of Otome_ 政 $ au in the embodiment of the present invention, and FIG. 8 is a flowchart of releasing the link. “3”: cross = ;, describing FIG. 6 The release chain control is independent from the principle of the conventional technology. Refer to the auxiliary reference in Figure 4; ^ The H key is responsible for reading the packet. Both instructions indicate that it contains a step knife. ^ Release the link at the time and (Release link, see Figure 8) Step 320 · Judge a round of ψ ^: Link address space containing ytnie put 31; it is the second port after reading the packet. Interpretation step 321: release the link 纴 .f order ', 1, otherwise end. The free address _〇 二 == the link address space address 53 after the end address for pipe / sequential hanging Link (read packet, see FIG. 6) back to the processing step (iv).

589822

Description of the invention (13) Step 3 2 2: determine early π + step 323, otherwise it will end ^ if there is a packet to be transmitted 丨 if yes, then skip to step 323: bismuth jing, output 40 of the roach 40 'out , List the front end address; that is, read the front end address 38 from the material H of the input block to obtain the first area * cattle. Perform steps 3 2 4 and 3 2 6 simultaneously. 1 4. Read the block address 14 of the packet on the shared memory 10 and the knife 4 again, and go to step 3 2 5. Step 325: Read the packet data; read the packet data according to the current link address 33 of the packet on the link \ AM30 and the mapping block address 14 on the shared memory. And skip to step 328. Step 3 2 6 • Determine whether there is the next packet to be transmitted; if yes, skip to step 3 2 7 ′; otherwise, skip to step 3 2 8. Step 327: Read the link; read the single link string 34a of the packet on the link RAM30, and the link string address table of the packet on the link RAM30 (such as # 4 — —, As the next to-be-passed round packet, add the front end address reference of the corresponding output queue 37 of the packet, and go to step 3 2 8.

Step 3 2 8 on page 17 · Determine whether the packet has been completely read or the transmission has failed; if yes, go back to step 322, otherwise continue with this judgment. Η 589822 The diagram briefly illustrates that Figure 1 is a conventional Ethernet network exchange Simple phonogram of the structure. ., An example of the control flow chart of double ,, and the same father changing, and the ancient structure received a curse in a packet. Figure 3 is a private flowchart in Figure 1. Figure 4 shows the control flow of a conventional EtherVariety.> 4-way parent switch configuration in the packet transmission process. Figure 4 The Ethernet switching structures of the embodiments do not think about it. FIG. 5 is an example of a control flow chart of the Ethernet switching structure forming a link in a packet received privately according to a preferred embodiment of the present invention. Fig. 6 is an example of a control flow chart for reading a link during a packet transmission process of an Ethernet switching structure according to a preferred embodiment of the present invention. FIG. 7 is an example of a control flow chart for obtaining a link in FIG. 5 according to an Ethernet switching structure according to a preferred embodiment of the present invention. Fig. 8 is an example of a control flow chart for releasing a link in Fig. 6 according to a preferred embodiment of the Ethernet switching structure of the present invention. ° [Symbol description] 1 0 ～ shared memory 11 ～ buffer block 12 ～ free buffer storage slot 1 3 ～ designated buffer 14 ～ block address 1 5 ～ map 20 ～ input port

Page 18 589822 Brief description of the diagram 21 ~ packet segment 30 ~ link RAM 31 ~ link address space 32 ~ link address width 3 3 ~ link address 3 4 ~ link string 3 4 a ~ Single link series 3 5 to flag 3 6 to link series 3 7 to output queue 3 8 to front end address 4 0 to output port 42 to front end address 4 3 to back end address 50 to free chain Junction RAM 51 ~ Free link address space 5 2 ~ Free bond address width 5 3 ~ Free link address

Claims (1)

589822 6. The scope of patent application includes: 1.—A kind of dynamic memory configuration method for Ethernet switch structure, including plural = multiple input port and plural rounds, which are used to receive and transmit inverse plural packet segments. ; Jiudeshi enjoys the memory, which is dynamic random access memory, used to store the packets before transmission, after receiving, from the plural rounds out, the first link RAM, and its The shared memory is-mapping off_. When the plural packets are written on the hidden body, one of the packet segments that add the plural packets for a long time is controlled. When each of the next four packets is taken, the single ones are controlled. Read the Bei Ping chain and the Xiangkou series; and η 戽 ^ 仏 I ΐ a link RAM, as a first-in-first-out device, for the input on the port and the dagger 3 knots? Release of address space on corresponding output port. ,,chain,,,. The method of dynamic memory allocation for the first item of the scope of patent application by the above application, its _ address width. The width is configured to be no larger than the first link of the 2nd patent application scope of the dynamic memory allocation method. The shared memory system in the basin is configured to be complex and related, and ^ β ^ takes a number of data buffers of the same size. The number of blocks in the area and the first-link RAM and the second-link number link address space are all the same, and the number of complex numbers is the same. '... Hai-Xiang 5 complex memory block 4. If the memory allocation method of item 3 of the patent application is dynamically allocated, it is 589822. 6. The block size of the complex buffer area in the patent application is 256. Bytes. • Affirmed that the third aspect of the patent scope is that the emotional body moves away from ancient times and the ancient times, and that the plural packets of the plural-sentences are different. The latest version of the shared memory can be filled with six daggers; £ r 6 is as follows: Γ f " Dynamic range memory allocation method of item 3, which = IΞThese single-link series ', The acquisition of the link address space on the corresponding input car is when the link address space is less, requesting a second link to request a free link address space The fixed number is determined by dividing the maximum length of a packet by the size of the data buffer block; and the free bond address space corresponds to one of the available link address spaces of the first key negotiation. 7 · If the memory allocation method of item 6 of the patent scope is declared, the fixed number is 6 immediately. … 8. According to the method of dynamic memory allocation of item 3 in the scope of patent application, when writing the plural packets on the Yu body, control the composition of one of the packets / knife segments of the plural L in the early link sequence including writing A packet of data contains: π / ^ Requests at least one blank block from the shared memory. • Requests to write from P to J from the remote shared delta memory; 3 The first block of the R & block starts to follow At present the size of the packet, the link position on the first bond RAM of the packet, and the packet dagger \ write the packets in the block address on the memory. A /, hand knife Fengyou's data; and 589822 VI. Patent application memory writes the block addresses of all such packet segments into the shared packet. When the first packet is written, 1 is written into the packet, and When the packet of the " Hai packet is segmented at the first g D Λ M, the link address is notified to the first-packet of the second port, which constitutes a link. For the purpose of outputting the memory dynamic allocation method of the patent application No. 8 in the patent application # 9, the end address of the output port is established. . The parallel rank is added to the 10. If the management of the single link series reads in the memory dynamics of item 3 of the patent application scope, the bond bit = on; the release on the output port should be released by the first The second link RAM is to first add the link address of the first link RAM that has completed reading the link; the back end address of the second link RAM is added in order. In the workshop, if you read the plurality of packets in the memory dynamic alignment of item 3 of the patent application, control the read packets of the single-key string sequence. The following steps: Read the output of the output port The front-end address on the queue is the link address of the first packet segment of a packet; at once, read all the packet block addresses of the packet on the shared memory, and determine whether there is the next one at the same time Packets to be transmitted; read the scoop according to the current segmented addresses of the packets on the first link RAM and its block address on the shared memory; μ, i, six, patent application Ranges such as ί :: iT packets exist from ~: ;; Γ: Μ chain link address table / these packets are segmented at the front-end addresses of the two output queues 俾 the next wait When the packet is transmitted, the packet to be transmitted is read. Or, if the transmission fails, the following 12 types of Ethernet exchange driver shake multiple input ports are used to receive a wide range of complex output signals, which are used to transmit these packet fragments; a shared memory, A kinetic energy is sent to the knife. Also, when the packet is segmented into the plurality of rounds, the memory is used to store the plurality of network packet segments before the transmission, and then transmit a first chain from the plurality of output ports. In the RAM, 1 is used for V and V in the shared memory: the upper body is a mapping relationship. The control of packet segmentation of several packets is controlled by the early key, the structure of the ⑺ series, and the reading. When fetching the plurality of packets, control the reading of the single-link series; and-the second link RAM 'It is a first-in-first-out device, which is used to jointly manage the single-link series before they are formed. After the link address space is acquired on the corresponding input port and the single link string of the link net is read, the link address space is released on the corresponding output port. 1 3 If the Ethernet switching structure of item 12 of the patent application scope, wherein the address width of the second link RAM is not greater than the address width of the first link ram. 1 4 · If the Ethernet switching structure of item 12 of the patent application scope, its page 23 589822 The shared shared memory contains a plurality of data of the same size and each of the first-link RAM and the second-link RAM is configured with:, the number of address spaces is the same as that of the buffer area of the plural data: head: end 15. If the size of the plurality of data buffer blocks in the Ethernet of the scope of application for patent No. 14 is 256 bits = change ,,,. Structure, the second 6 .: The Ethernet switching structure of item 14 of the patent scope is requested, and a packet of a plurality of packets in the basin is divided into a maximum of six blocks. Xi j is full of the shared drought memory 17. If the Ethernet exchange structure of the 14th patent application scope, the block of the plural data buffer of the shared drought memory includes: Bayi free buffer storage slot A plurality of blank blocks; and a plurality of write blocks of a plurality of designated buffers. 18. If the Ethernet switching structure of item 17 of the patent application scope, wherein the plurality of blank blocks of the free buffer storage tank includes: blank blocks to be sent to the recipients who are about to receive the packet segments. , And a blank block released by a person who has read the plural write block of the plural designated buffer. 19 · If the Ethernet switching structure of item 7 of the patent application scope, wherein the plurality of blank blocks in the free buffer storage slot corresponds to the specific plural number of the second key RA M Address space. 20 · If the Ethernet switching structure of item 2 in the scope of patent application is applied, before the management of the single link series, the link address space is in operation. Page 24 589822 6. The scope of patent application should be obtained on the input port. When the link address space is less than a fixed number, 'request at least one free link address space from the second link RAM. The free link address space corresponds to the first-link Ram, an available link address space. 2 ° of °, such as the Ethernet switching structure of patent application No. 20, and the fixed number is 6. 〇 22.2 · If the Ethernet switching structure of item 12 of the scope of patent application, the management of the release of these single links in series, the release address of the link address ° space on the corresponding output port The second link RAM uses the first-in-first-out formula "quotation 0" to free the link address space released by the completed read link on the first link RAM from the back end of the second link RAM. Addresses are added sequentially. 2 3 · If the Ethernet switching structure of item 12 of the patent application scope, the maximum length of one packet of the plurality of packets is 1 536 bytes. 24. If the Ethernet switching structure of item 12 of the patent application scope, wherein the shared memory system is SRAM or DRAM. 25. If the Ethernet switching structure of item 12 of the patent application scope, wherein the first link RAM is a SRAM or a DRAM. 2 6 · If the Ethernet switching structure of item 12 of the patent application scope, wherein the second link RAM is a SRAM or a DRAM. Page 25