TW589570B - Low-complexity bit-parallel systolic multiplier over GF(2m) - Google Patents

Abstract

The present invention relates to a low-complexity bit-parallel systolic multiplier over GF(2m). The multiplier includes a multiplication unit and a base transformation unit. The circuit architecture of the multiplication unit is composed of m<2> identical cells. Each cell is composed of 2-input AND gate, 2-input XOR gate, and 1-bit register. The base transformation unit is composed of tree-type 2-input XOR gates. When the generation polynomial of the finite field is non-factorable all one polynomial (AOP) or power-three polynomial x<m>+x<n>+1 where 1 <= n <= upper bound of (m/2). The multiplier generates very low system complexity and very low propagation delay. The computing delay of this circuit requires only m+1 or m+2 pulse cycles, thereby achieving the effects of low computing delay and high output speed.

Description

589570 A7 B7 V. Description of the invention (I) Technical field (please read the notes on the back before filling this page) The present invention is a low-complexity systolic array type double base multiplier with limited field GF (2m), especially Refers to an innovative technology that can increase the multiplier speed of a finite field GF (2m). BACKGROUND OF THE INVENTION At present, China's patent technology related to the "multiplier" disclosed in the Republic of China Patent Gazette can be listed as follows: 1. Announcement No. 3 8 2 0 8 8 "Finite Field GF (2m) Cell array power and circuit "invention patent case. 2. Announcement No. 4 0 7 8 9 "Multiplier" invention patent case. 3. Announcement Patent No. 2 5 5 9 5 7 "Design method of t-bit semi-parallel processing Growayan multiplier". 4. Announcement No. 3 6 0 8 4 5 "Panel array multiplier architecture and method" invention patent case. 5. Announced patent case No. 4 0 5 0 8 6 "Fast Regular Multiplier Architecture". Printed in this limited field GF (2m) by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, effective algebra operations (including operations such as addition, multiplication, division, and exponent) are widely used in error correction codes and cryptographic techniques. Decoding of binary BCH code, encoding and decoding of RS code (Reed-Solomon Code), and encryption and decryption of digital information on secure communication (Encryption and Decryption). Nevertheless, the operations of multiplication and negation of GF (2m) are still quite complicated. For multiplication in GF (2m), some scholars have proposed fast algorithms and fast circuits, such as Itoh-Tsujii, Sunar-Koc, Hasan. These 3 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 589570 A7 __B7_ V. Description of the invention (2) These multiplier architectures are based on special polynomials, which include all-one-polynomial (AOP), isometric Polynomial and trinomial polynomial. Gu◦ and Wang developed the second stage (please read the notes on the back before filling out this page), a multiplier, which is composed of a general multiplication unit and a power reduction processing unit. Although the low complexity multiplier described above is very suitable for cryptographic technology, its circuit structure is not a systolic array circuit. If m is large, it will cause a long propagation delay. For the low complexity multiplier, please refer to the following literatures: [1] E. R. Berlekamp, Algebraic Coding Theory, New York: McGraw-Hill, 1968 [2] D. E. R. Denning, Cryptography and Data Security, Reading, MA: Addison-Wesley, 1983.

[3] M. Y. Rhee, Cryptography and Secure Communications, McGraw-Hill, Singapore, 1994.

[4] T. Itoh and S. Tsujii, "Structure of Parallel Multipliers for a Class of Finite Fields GF (2m)," Information and Computation, Vol. 83, pp. 21-40, 1989. Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives [5] MA Hasan, M. Wang, and VK Bhargava, r, A Modified Massey-Omura Multiplier for a Class of Finite Fields, &quot; IEEE Trans. Computers, Vol. C-41, No. 8, PP. 962-972, Aug. 1992.

[61] CK Koc and B. Sunar, &quot; Low Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields, 丨 'IEEE Trans. Computers, Vol. 47, No. 3, PP. 353 ~ 356, Mar. 1998.

[7] B. Sunar and CK Koc, MMastrovito Multiplier for All Trinomials, &quot; IEEE Trans · Computers, Vol. 48, No · 5, PP. 522- ____I____4_ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 (Mm) 589570 A7 _________ V. Description of Invention) 527, May 1999.

[8] JH Guo and CL Wang, &quot; Low-Complexity Power-Sum Circuit for GF (2m) and Its Applications &quot;, IEEE Trans. Circuits and Systems-II, Vol. 47, No. 10, PP. L〇91_l 〇97, 〇ct. 2000 · In the ultra-large-scale integrated circuit technology, the array processor has a simple and regular circuit system, including three types of circuit architecture: cardiac contraction (systollc), cells (cellular), and ducts ( pipeline). The advantage of the array processor is that it can be defined as a basic cell or some cells. Existing shrinking multipliers for finite field GF (2m) are mostly based on two algorithms-a first significant bit first array and a last significant bit first array. Calculates the product of two elements of a finite field. These multipliers are suitable for applications with error correction codes, but these shrink multipliers have very complicated circuits and long calculation delays for cryptographic applications. For example, the wait time of Wei's multiplier requires a 3m pulse delay; the wait time of Guo-Wang's multiplier requires a 2.5m pulse delay. Related systolic multipliers can refer to the following documents: [1] SW Wei, MA Systolic Power-Sum Circuit for GF (2m), M IEEE Trans. Computers, Vol. 43, No. 2, PP. 226-229, Feb . 1994.

[2] C. Yeh, S. Reed, and D. K. Truong, &quot; Systolic Multipliers for Finite Fields GF (2m), M IEEE Trans. Computers, Vol. C-33, PP. 357-360, Apr. 1984 · [3] C. Y. Lee, E. H. Lu, and J. Y. Lee ,,, Bit-Parallel Systolic Multipliers for GF (2m) Fields Defined by All-One and Equally-Spaced Polynomials, , f IEEE Trans. Computers, No. 5, PP. 385- _ _5__ This paper size applies to China National Standard (CNS) A4 specification (21 OX297 mm) (Please read the precautions on the back before filling this page) L · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7C 5 9 8 5 A7 B7 V. Invention Description (j) 393, May 2001. (Please read the notes on the back before filling this page) [4] CY Lee, EH Lu, and LF Sun, &quot; Low-Complexity Bit-Parallel Systolic Architectures for Computing AB2 + C in a Class of Finite Field GF (2m) n, IEEE Trans. CS-II, No. 5, PP. 519-523 , May 2001 · For the finite field GF (2m), the expression of the element mainly includes a polynomial basis (standard basis or polynomial basis), double Bottom base (dual basis) and the substrate normal (normal basis). In the double base, the linear-feedback Belekamp multiplier is effectively implemented according to linear feedback. Wang has developed another type of dual-base multiplier that uses its own dual-normal basis. Not long ago, Wu-Hasan-Blake used a dual base to design a low-complexity bit multiplier.

Fenii proposed a conversion relationship between double and standard bases. He also proposed bit-parallel and serial double-base multipliers. For the multiplier with double bases, please refer to the following documents: Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs [1] J. Menezes, IF Blake, X. Gao, RC Mullin, SA Vanstone, and T. Yaghoobian, Applications of finite fields Kluwer Academic, 1993.

[2] ER Belekamp, &quot; Bit-Serial Reed-Solomon Encoders, &quot; IEEE Information Theory, Vol. 28, PP · 869-974, 1982 · [3] M. Morii, K. Kasahara, and D 丄 · Whiting , &quot; Efficient Bit-Serial Multiplication and Discrete-Time Wiener-Hoph Equation over Finite Fields, &quot; IEEE Trans · Information Theory, Vol. 35, PP.1177-1184, 1989. __ ^ _ 6_ This paper standard applies to Chinese national standards (CNS) A4 specification (21 OX297 mm) 589570 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7___ V. Invention Description (f) [4] M. Wang and IF Blake, &quot; Bit Serial Multiplication in Finite Fields /, SIAM Discrete Math. Vol. 3, No. 1, PP. 140-148, Feb. 1990. [5] CC Wang, nAn Algorithm to Design Finite Field Multipliers Using a Self-Dual Normal Basis, &quot; IEEE Trans. Computers, Vol · 38, No. 10, PP. 1457-1459, Oct. 1989. [6] H. Wu, MA Hasan, and LF Blake, M New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases, &quot; IEEE Trans · Computers, Vol · 47, No. 11, PP. 1223 ~ 1234, Nov. 1998. [7] StJ Fenn, M. Benaissa, and D. Taylor, nGF (2m) Multiplication and Division over the Dual Basisf, IEEE Trans. Computers, Vol. 45, No. 3, PP. 319-327, Mar · 1996 · [8] StJ Fenn, M. Benaissa, and D. Taylor, MA Dual Basis Systolic Multipliers for GF (2m) &quot; IEE Proc-Comp. Digit · Tech ·, vol · 144, no. 1, PP.43-46, 1997 Introduction to the finite field GF (2m) Assume that the finite field GF (2m) is a nondecomposable polynomial F (x) = xm + fm -... + flX + f. Produced, where all coefficients are fi or 0. Assuming α is a root of F〇〇, the element of GF (2m) can be expressed as follows: A = a〇 + aia + ... + am-iam · 1 where all coefficients are 0 or 1 and the base is called the standard base Or polynomial basis. In addition, the standard base corresponds to the form of the double base {β. , Βν ··, βπ ^} have the following characteristics: ________7_ This paper size is applicable to the Chinese National Standard (CNS) Α4 specification (21 〇 × 297 mm) (Please read the precautions on the back before filling this page) Ordering storms __ ·· · Π4 589570 A7 B7 V. Description of the invention (6) ΊΗγα%) if i = j ⑴ [〇if i ^ j where Tr (·) is the trace function, and YeGF (2m), Y # 0. For AEGF (2m), ^ = 5 where ⑴ and are the corresponding coefficients of the polynomial basis and the double basis of the element A. From, we get m-lΤΓ (γαίΑ) = ΤΓ (γαίνα] β]) ml a] Tr (Ya ^ j) 7 (2) (Please read the precautions on the back before filling this page) a, from F (a ) = 0, we can get the following relation mY m-Γ

m-Y

Ja order a / n + l 5 (c + /: /, (v ϊ-Γ

/ (V (3) s &gt;. a mV 2m-2 _ / * (^-2) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, where all coefficients are equal to 1 or 0. Assume the element Β = ώ0β〇 + 1) ΐβΐ + is based on the double-basis table 7] ~ ς. Applying the tracking function to both sides of equation (3) gives Tr {yalB) ^ bi? i = 0,1, ..., m-1 and (4a) paper The scale is applicable to the Chinese National Standard (CNS) A4 specification (210X29? 589570 A7 B7 V. Description of the invention (m_l 7 &gt; W5) = J // — ~ ·, i = m, m + 1, ..., 2m-2 ( 4b) / «0 Suppose ί, i = 0, Bu ..., 2m-2. If element C is the product of two elements A and B, then there is the following relationship ^ 0 ^ 1 ~~ h b.

bm a'K ax ym-l J2m-2 a ml C0 C1 ml c Extremity = rr (yaj) (i = 〇, 1, 2,. ^ 2111-2), c ^ TKy ^ C) (i-0 , 1, 2, • ••, ml), and ^:

(5) (Please read the notes on the back before filling in this page) To sum up, calculating C = AB has the following two steps:

^ SJ 1. Use equation (4) to calculate β, 0 ^ U2m-2 2. Use equation (5) to calculate Ci, OsUm_l The calculation rule of a double bottom multiplication method right A = a〇 + aicx + a2Cx +. &Quot; + am-i〇c and B = b〇P〇 + biPi + b2P2 +. &quot; + bm- are two non-zero elements of GF (2m), which respectively reveal the element expressions of the standard base and the double base. First, suppose the calculation of ί = 7 &gt; (yaW), i = m, m + 1,…, 2m-2, has been determined by equation ⑷. Therefore, according to equation (5), 'if the element C ^ CoPo + ClPl + CzP〗 + ··· + 〇ηι · ΐβπι_1 is the product of the two elements A and B, then ml ml ϋΑ + Λ ⑹ In order to design a systolic double-base multiplier, the new algorithm needs the following derivation process. PX A = 3.0 + fllCX + & 2CX + ... + 3.m * l (X and B = 1) 〇β. + bl β 1 + This paper size applies to China National Standard (CNS) Α4 size (210X297 mm)

1T S. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 &amp; 589570

Both elements are GF (r). From the equation ⑹, which has a double earth bottom, it is divided into two parts: the even number i + j and the odd number ⑷, that is, 7—Hdd. Now we will explain the double base multiplication according to equation (7). 1) The even numbers i + j assume that j and k are the same Is an even number or an odd number, where and 'and 1 are selected so that i = &lt; Gk) / 2 &gt; to satisfy i + j as an even number, where &lt; θ &gt; is expressed as ein〇dm. Then, substituting i = &lt; (jk) / 2 &gt; into the first term on the right side of equation (7), we can get (please read the notes on the back before filling this page) i + j is even m— 丄 1 i + k is even ⑻

IT 2) Odd number i + j Suppose j is even (or odd), and k is odd (or even), where O ^ k ^ n-I and, and i is selected as izz &lt;-( j + k + l ) / 2 &gt; so that i + j is equal to an odd number. Therefore, substituting i = &lt;-( j + k + l) / 2 &gt; into the right side of equation (7) The second term, we can get άφ. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 71-1

i + j is odd αΑ + / ^ / = y y.a &lt;

A: 1 / = 0 λ = 0 i + k is odd Therefore, multiplication can be derived as follows:

AB i + j is odd b + a &lt;-( i + y + l) / 2 &gt; ^ &lt;-(/ + y + l) / 2 &gt;+; i + j is even (9) (10) paper The standard applies to the Chinese National Standard (CNS) A4 specification (210XM7 mm) 589570 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_ V. Invention Description (7) Example 1: Assume A = a〇 + aia + a2a2 + a3〇 c3 + a4a4 and B = b〇p〇 + b ^ + b ^ + b ^ + b # 4 are two elements of the finite field GF (25); and it is assumed that C = c〇P〇 + c ^ + c ^ + c3p3 + c4p4 is the result of multiplying two elements A and B. If S; = 7 &gt; (yaj), i = 0, Bu 2, ..., 2m-2, the calculation has been completed by equation ⑷. Therefore, using equation (10) to calculate the double base multiplication, if the element OC ^ + C ^ l + C ^ +. H + Cn ^ nM is expressed as the product of two elements, the product of A and B is obtained as follows: β〇βχ β2 / ^ 4 β〇5〇aA a3b6 a3b7 ~~~~~~~~~~ + «2b2 fl2Z? 3 a ^ 3 a ^ 4 a〇Z? 4 ^ This is the reason for the invention The purpose is to propose a GF (2m) multiplier with low calculation delay and high output speed. In order to achieve the above-mentioned object, the present invention proposes a low-complexity systolic array-type double base multiplier with a low field of finite field GF (2m). The circuit characteristic includes a device for error-control encoding of data decoding and encryption technology. In decryption, the multiplier performs a product operation on a first element A and a second element B in the finite field GF (2m) to obtain a third element C, where the element A is based on a polynomial basis (I, α, α2, ··· # 1 ™), the elements B · and C are expressions with double bases, and the finite field OF (2m) is an indecomposable polynomial ______ η_ ___ This paper standard applies Chinese national standard ( CNS) A4 specification (21〇297297) (Please read the precautions on the back before filling this page)

589570 A7 B7__ ___ V. Description of the invention (/ 0) (Please read the notes on the back before filling this page), and α is the root of the indecomposable polynomial; the first element A is represented as a m-bit A = a〇 + aia + a2〇c2 + ... + am] am] '§ Table I element B is expressed as an m-bit B = Νβο + Ι ^ β ^ + b2p2 + ... + ΐ3〇Μβπ ^, The second element C is represented as-^ Π1 position C = Cop. + 〇ΐβ 1 + C2 02 + ·· + ". Such as · 1 'where the coefficients of all elements are equal to 0 or 1, the multiplier includes two units. · Double-base multiplication and double-base conversion; The double-base multiplication The circuit structure of the unit is composed of small cells with the same m2 to form an mxm array. Each small cell contains three (or four) input signal lines and three (or four) output signal lines. Each small cell contains an AND. Gate, one X0R gate and three (or four) one-bit registers; the circuit structure of the dual-base conversion unit is composed of a tree-type 2-input X0R gate. The multiplication unit of this multiplier contains two array cells of small cells (V and U cells), where each V cell performs ~ = \ _ ({. +;. + 1) / 21 (1. +; + 1) / 2 &gt;+; + q calculations; each U cell performs the calculation of [广 α &lt; (ί · _;) / 2Λ (Η) / 2 &gt;+; · + c; •. Where The output signal A of the array cell Uu is connected to the input signal a of the array cell Ui + u + i, and the output handle of the array cell Uu; B is connected to the array. Input signal B of Ui.m; output signal a of the array cell Vu is connected to the array cell Vuu. Input signal A, output signal B of the array cell Vu is connected to the array cell Vm, and +1 input signal B . Among them, if all the elements of the finite field GF (2m) are composed of three items that cannot be decomposed ^ The paper scale is applicable to the national standard of China ^: (grabbing) 8 4 specifications (210/297 mm) &quot; '~' 7 589570 A7 ___B7 V. Description of the invention (I 丨) The polynomial xm + xn + l is generated, where gcd (m, n) = 1, and the coefficient of the second element B is entered in an arrangement of ⑼ \ (1) ... Basis conversion array processor. Among them, the output signal of the base conversion array processor is output in the form of (heart_ & —..., -_). Where all elements of the finite field GF (2m) are determined by Generated by the indecomposable trinomial polynomial xm + x ”+ l, where gcd (m, n) = 1 and r &gt; 2, the coefficients of the second element B are divided into i groups, and each group of coefficients is arranged in the same order The method enters the subbase conversion array processor. Among them, the coefficient of the second element B, the coefficient of the i-th group, O ^ Ur-2, is input to the modified subbase. Conversion array processor, the output of the sub-base conversion array processor is the i = r-1 set of coefficients input to the sub-base conversion array processor, and the output of the sub-base conversion array processor is 1) + / + mr ( 2) + i + mr ^ K (ml) + i + mr) where the array cell Uu, if i + j = even, the output signal A of the array cell Uu is connected to the input signal A of the array cell Umw, the The output signal B of the array cell Uu is connected to the input signal B of the array cell; if 1+: j = odd, the output signal A of the array cell Uu is connected to the input signal A of the array cell, and the output signal of the array cell Uu B is connected to the input signal B of the array cell U1 + u + 1. Among them, when i + j = odd, each U cell performs the calculation of ς · = 次 -㈣'s daughter-in-law; when 1 ♦ even number, each u cell executes ς · = 4 (W) / 2 &gt; 5 &lt; (WV2 &gt; + Calculation of ς ·. _ ^ _ 13 __ This paper size applies to the Chinese National Standard (CNS) Α4 size (210 X 297 mm) / '(Please read the precautions on the back before filling this page) Άά0. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 589570 A7 _____B7 V. Description of the invention ((2) Where all elements of the finite field GF (2m) are indecomposable The structure of the multiplier includes only a double-base multiplier, and the calculation delay of the multiplier only needs m + 1 pulse periods. Among them, the multiplier consists of (m + 1) x (m + 1) array cells, where each cell contains an AND gate, an XOR gate, and three one-bit registers, where the three one-bit registers, where the first element A is represented Is a m + 1 bit (Α = Αο + Αια + A2a2 +. &Quot; + Amam), the second element B is represented as a m + 1 bit B = Βοβο + Βφ i + B $ 2 + ... + Bmpm, the third element C is represented as an m + 1 bit C = C〇p〇 + Οβ C2p2 + · _. + Cmpm Among them, the propagation delay of each pulse period requires the calculation time of an AND logic gate and an X0R logic gate. Among them, if all elements of the finite field GF (2m) are composed of an indecomposable trinomial polynomial xm + x + l, the calculation delay of this multiplier only needs m + l pulse period; if all elements of the finite field GF (2m) are generated by the indecomposable trinomial polynomial xm + xn + l, 2 ^ n ^ "m / 2l, the calculation delay of the multiplier only needs m + 2 pulse wave periods. In order to make the above-mentioned objects, features, and advantages of the present invention obvious and understandable, a preferred embodiment is given below, and In conjunction with the attached drawings, the detailed description is as follows: 'With a view to B, people who are familiar with the related technology of the present invention can implement it according to the statements in this specification. Formula Description 1 Figure: The systolic double-basis multiplication of the present invention Structure diagram of the device. The second figure ... is a schematic diagram of the circuit of the base conversion unit of the present invention. (Please read the Precautions to fill out this page)

/ 0%. 5 9 A7 ______B7 V. Description of the invention (丨)) Figure 3: This is the sequential calculation process of the double base multiplication unit of the preferred embodiment of the present invention. Figure 4: GF (25) systolic architecture diagram of the dual base multiplication unit of the preferred embodiment of the present invention. Fifth figure: Detailed U-cell circuit. Figure 6: Detailed V-cell circuit. Fig. 7 is a detailed base converter circuit of the trinomial polynomial χ7 + χ4 + 1 of the preferred embodiment of the present invention. Eighth diagram: (a) is a detailed subbase conversion circuit of the trinomial polynomial χΐ2 + χ3 + 1 of the preferred embodiment of the present invention; (b) is a trinomial polynomial xl2 + x3 + l of the preferred embodiment of the present invention The modified sub-base conversion circuit. The ninth figure: the circuit structure of the base converter of the trinomial polynomial xl2 + x3 + 1 in the preferred embodiment of the present invention. Figure 10: Correspondence table between the polynomial cyclic basis and the expression of the polynomial basis of the finite field GF (24) element. FIG. I ^ 1 is a GF (24) systolic architecture diagram of an AOP-based dual base multiplier according to a preferred embodiment of the present invention. Detailed description This section describes the new bit-parallel systolic double-basis contraction multiplier, which includes two-unit double-basis conversion and double-basis multiplication. Figure 1 shows the functional block diagram of the entire double-basis multiplier. In Figure 1, Dk represents the m-bit register and the delay of the register is the calculation time of the double base conversion unit. The double base conversion unit calculates m ^ i ^ 2m-2 according to equation (4), where the element B = b〇p〇 + biPi + b2p2 +… is double _____15_______ This paper scale applies Chinese national standard (cys) A4 Specifications (210 X 297 mm) &quot; — (Please read the notes on the back before filling this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 589570 5 A7 B7, Invention Description (#) The element expression of the base and Y £ GF (2m). The double base multiplication unit performs the product of two elements according to equation (10). First, according to equation (4) ', the conversion unit contains m-1 modules, and each module is built into a tree structure of XOR logic gates, as shown in Figure 2. Therefore, this circuit is composed of (ml) 22-inputX〇R logic gate, 2m (ml) 2-input AND logic gate, and (m-1) 2 l-bit register, the calculation of the conversion unit circuit The delay only requires a pulse period of f0g2ml. Second, for simplicity, the multiplication unit is based on the finite field GF (25) as an example. Holiday Man A = a〇 + aicx + a2〇c + a3a + a4 (x4 and B = b〇p〇 + + b2p2 + b3p3 + b $ 4EGF (2m), and calculated that it has been converted to g by ten Calculate. Right Ci = CiOp〇 + 〇ηβΐ + Ci2P2 + Ci3P3 + Ci4p4 is expressed as the product of the i-th two elements. If the initial 値 C〇 = 0 is set, the sequential calculation process of multiplication is shown in Figure 3. Based on Figure 2 The ten-calculation process shown in Figure §. Figure 4 reveals a bit-wise parallel systolic multiplier. This circuit contains 25 basic cells (14 U cells and 11 V cells). Each U cell is defined as a 2-input XOR gate, a 2-input AND gate 'and three i-bit registers, as shown in Figure 5; each V cell is defined as a 2-input XOR gate, a 2-input AND gate , And four 1-bit registers, as shown in Figure 6. In Figure 4, all coefficients in Uu cells exist in diagonally adjacent cells. We can see from example 1. For example, Uu cells define two coefficients a3 And the product of | 35 'and the coefficient a3 exists in U (u and u2,3 cells. Similarly, the coefficient b5 also exists in U2 "and U (u cells. Similarly, all coefficients in Vu cells Exist in a diagonal neighboring cells from within a paradigm known. Special attention, two-line (please read the Notes on the back to fill out this page) Order Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed

589570 A7 V. Description of the invention () number, ζ and when entering V cell, one of the two coefficients-provides the multiplication operation of the cell. The output signal A of the array cell Uu is connected to the input signal a of the array cell U1 + u + 1, and the output signal B of the array cell Uu is connected to the input signal β of the array cell Um, w; the output of the array cell Vu The signal A is connected to the input signal a of the array cell Vi ui, and the output signal B of the array cell is connected to the input signal B of the array cell Vi + i j + i. Each v cell is performing the calculation of c; · = ㈣ + 1), 2 five + ㈣ ~; each U cell is performing ^ Cj ^ a &lt; (ij) / 2 &gt; ^ &gt; &lt; (ij) / 2 &gt; + j + C; • calculation. As mentioned above, the calculation delay of this multiplication requires only m pulse periods. Based on the above conclusions, according to this algorithm, the calculation delay of the proposed double-basis systolic multiplier only needs m + "log2ml pulse wave period, and each cell requires a 2-input AND logic gate and a 2-_utX〇R logic gate The calculation is delayed. Therefore, the GF (2m) multiplier proposed in this patent has very low calculation delay and high output speed. In order to further reduce the complexity of the circuit, the following uses two polynomials, trinomial polynomials, and all-in-one polynomials to analyze and discuss the complexity of the multiplier. (1) Unresolvable trinomial polynomial The form of the polynomial is xm + xn + l, which is called a trinomial polynomial. Assume that an indecomposable trinomial polynomial is used to generate all elements of the finite field GF (2m). From the multiplication algorithm according to equation (10), for the finite field GF (2m) generated by a trinomial with a different power of m, the double The structure of the base multiplication unit having the same multiplication unit is known from equation (5), however, the double base conversion unit circuit does have different calculation delays and circuit complexity from equation (4). Therefore, we will analyze the circuit complex of the conversion unit by using a non-decomposable trinomial polynomial. 17 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) | _. ^-(Please read first Note on the back, please fill out this page again)-Ordering and Miscellaneous · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 589570 Α7 Β7 V. Invention Description (μ) Miscellaneous. First, we define π⑴ as the smallest non-negative integer of module m, that is, Jt (i) = m−l + i (m-n) mod m (11) where lsnsm-1 and OsUm-1. Suppose that η is set to any integer in the Unsm-1 interval and gcd (n, m) = 1. For si &lt; p ^ ml, ml + I (mn) mod m # m-l + p (mn) mod m. As a result, {m-l + i (mn) mod Π1} i = 〇, 1, 2, ..., m-1 — {0, 1, · · ·, ΓΠ-1} 0 From equation (11), An integer i of the set of {0, 1, 2, ..., m-1} can be corresponding to Jt (i). Using this conversion, the higher-order terms a〃m, j = 0, 1, ..., m-2, can be converted into απ (1) + 1Ώ, ^ 1, _..., ιη-1. Assuming that a is the root of the indecomposable trinomial polynomial P (x) = xm + xn + l, we can get P (o〇 = am + an + l = 〇 and am = an + l. In order to reduce the higher-order term απω + ίη, first, we define the following equation to perform the power reduction operation of the higher-order term: α &quot; + π (0 = αη + π (0 + απ (05 Ui ^ m-1 ⑴) According to equation (11), element B Can also be expressed as B = ΐ3π (〇φπω) + 1) π (ι) β π (υ + ··· + 1) π (ηι-ι) β π (πι · υ. Using equation (2), the equation (12) can become

Tr (am + 7T (i) rB) = ΤΓ (αη + π (ί) γΒ) + Τν (απ (ί) γΒ) = 7 &gt; (W) impulse) + \ (〇 (13) αη + π (1 ) There are two types in equation (13): (a) n + JC⑴ &lt; m and (b) n + Jt (i) ^: m. According to equation (12) 'ΐΓ (αη + πωγΒ) has the following characteristics: (a) n + ji (i) &lt; m From equation (11), we can directly obtain

Jt (i) = m -η + π (ί-1) (⑷ I-- · ---------- 'I— Order ------ Μ9! (Please read the note on the back first Please fill in this page for further information) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 18

589570 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Both sides of equation (14) of the invention description (^) add an integer η, so Jt (i) + n = m + Jt (i-1). Suppose, we can get ΓΓ (αη + π (ι) γΒ) = Tr (am + π (1 '° γΒ). Using the characteristics of equation (12), αη + π (1) can be converted into τν {αη + π {ί) γΒ) = Τφ ^^ γΒ) + Ττ (απ {ί-ι) γΒ) = 7 &gt; (α_ ㈣ 淖) 4Λ (μ) (b) n + Jt (i) &gt; m from the equation ( 11), we know that 0 ^ :( Hua 111-1 &gt; 0, 1, 1, 111-1 'if n + Jt (i) &lt; m, shell [J π (ί-1) = m-l + (il ) (mn) mod m = n-l + i (mn) mod m = n + m-l + i (mn) mod m = η + π (ί) Therefore ΤΓ (αη + π {ί \ Β) ^ ΤΓ (απ {ί-χ) γΒ) q6) From the above characteristics, if the higher-order term cxm + Jt ， can be reduced to the k-th power according to equation (12), it can become the following τν {απ ^ ΜγΒ) = bK (i) + Tr (a ^ nyB) (15) (17) (Please read the precautions on the back before filling out this page) ~) + νι) + ·· + ν_ + 7 &gt; (α jt (i 一k +1) + η γΒ) When performing k-th power reduction through equation (12), jt (i-k + l) + n 値 in equation (17) becomes smaller In m, therefore, the paper size of 19 in Equation (16) applies the Chinese National Standard (CNS) A4 specification (210X297 mm) / '589570 i___ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives / 2) + 7 = / 0) + / 1) + ^ (2) α- (3) + 7 = α, (2) + α, (3) ^ α ^ 4 ^ 7 = απ (2) + απ (3) + απ (4 ) α- (5) + 7 = α, (4) + α, (5) α · 7 = α ～) + α_ + α46) Α7 Β7 Description of the invention (| g) Characteristics, 7 &gt; (c ^ &gt; wy5 ) Can be obtained as follows: ΊΥ (απ (0 + ηιγβ) = ㈣ + ·. · + 1? Π (ί, (18) Note that the lower-order operation of the higher-order term απα) + Ι + is based on equation (12) The operation is performed successively, and the power of the power is greater than or equal to one. Assuming k is defined as the power of the power, k will have the following relationship (19) mn As mentioned above, let's focus on three types of three-term polynomials The situation respectively illustrates the complexity of the multiplier: (i) xm + xn + l and gcd (m, n) = l; (ii) xmi + xni: + l and gcd (m, n) = l and r &gt; 2 〇 (i) xm + xn + l and gcd (m, n) = l In order to explain the structure of the multiplier conveniently, we will take the trinomial polynomial x7 + x4 + l as an example to illustrate the circuit structure of the conversion unit. m = 7 and n = 4. From equation (11) we know that Jt (i) = m-l + i (mn) mod, π (〇) = 6, π (1) = 2, π (2) = 5, and jc (3) = 1 , Π (4) = 4, π (5) = 0, and π (6) = 3 can be directly calculated. Suppose α is the root of χ7 + χ4 + 1; απω + 7, i = l, 2,3,4,5,6, and the modular polynomial has the following result απ (1) + 7 = α9 = α6 + α2 α ^ + 7 = α12 = α6 + α2 + α5 απ (3) +7 = α8 = α5 + α απ (4) + Ί ^ α11 = α5 + α + α4 α &quot; (5 &gt; + 7 = α7 = α4 + 1 α, ( 6) + 7 = α10 = α4 + 1 + α3 With the characteristics of equation (11), the element B = b〇P〇 + biPi + ... + b6P6 can also be expressed as 6 = 13 a team (.) + 1 ^ 〇 々 洲 + ~ + 1 ^ 61 (6). Therefore, according to equation (2), the above equation can be calculated as follows: 20 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read first (Notes on the back then fill out this page)

589570 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _______B7 V. Description of Invention (丨 f) 1 ζτ ⑴ + 7 = ~ (〇) + ~ ⑴ = Office 6 + Office 2 \ (2) +7 2 \ ⑼ + \ (1) + \ (2) = do 6 + do 2 + do 5 = \ (1) +7 + do 5 t ⑶ + 7 ⑺ + \ (3) = do 5 + Α ^ :( 4) +7 = ^ 1: (2) + ^ (3) + ^ (4) = 05 + 6 + 64 = ^ (3) + 7 + 64 \ (5) +7 = \ (4) + \ (5) -do 4 + Office 〇1 (6) +7 Two dagger (4) + &amp; π (5) + b,) = b4 + b0 + b3 = &amp; π (5) +7 + b3 Figure 6 reveals the calculation &amp; &gt; 7, 1: = 1, 2, ..., 6 are obtained from the above equation. From the above-mentioned process of power reduction, for the form of the trinomial polynomial xm + x + l, the process of processing power reduction needs only one time; for the form of the trinomial polynomial Xm + Xn + 1, 2sn4m / 2l, processing power reduction The square process only needs to be performed twice. Therefore, for a finite field GF (2m), the polynomial is a trinomial polynomial. If the higher-order terms require k-order power reduction processes, the delay of the entire multiplier is always calculated as follows: m + k pulse period total 2- input XOR number of logic gates: m2 + m total 2-input AND number of logic gates: m2 (ii) xmr + xnr + l and gcd (m, n) = l and the form of rd polynomial g〇〇 = p (x &gt; i + xn ^ r is called an r-equally space trinomial (r_EST), where gcd (m, n) = l and P (x) is a trinomial polynomial of m power. If g (x) Is an indecomposable trinomial polynomial and gcd (m, n) = l, then p (x) is also an indecomposable polynomial. Pay special attention to the form of r-EST g〇〇 = xm + xm / 2 + l is not Decomposed trinomial polynomial if m = 2.3j, &gt; 1. For m-th power unresolvable r-EST, possible (mr, nr) pairings include the following: (6,3), (12,3), ( 12,9), (18,3), ... Assuming that the finite field GF (2m ^) is generated according to r-EST of the power of mr, the element can also be expressed as a 21-sheet paper scale applicable to the Chinese National Standard (CNS ) A4 size (210'〆297mm) (Please read the note on the back first Please fill in this page again for the items) • Equipment · -Order 589570 A7 B7 V. Description of the invention (2〇) B ~ B〇 + B1 + ... + Br-i (20) Among them, 〇 心 r_l (21) from 4j) was Defined in equation (11), π〇) can also be rewritten as n (j) = r (ml) + jr (mn) mod mr. Therefore, Bi, OsUr-1 can also be expressed as / π-1-the name of the office π (/) +! · Ar (y) + '° calculated from ζ = 7> 〇αζ'β), 〇sU2mr- 2. We divide ξ into r groups, and the good P 'is organized / contained by Chang, Min + i, ..., 5 (2 / „令 + 丨}' where 〇si &lt; rl. When i = rl 'do ( Lecture 2 -1> + Bu 1 = 〇 'In other words, the r-1 group ί contains only i 4+ 丨… ((2m-2) r +: · I' = Γ-1 according to a (j) = r (ml) + jr (mn), each group of good L ·, ..., 1 such as 丨 can be converted into | ~~~~ |

^ π (0) + ι &gt; (1) ++ /?, ^ 7r (ml) + /? ^ r (0) + / + mr ^ ^ n (ml) + i + mr J According to the equation (20 -21), the 値 of each group of ζ can be obtained by the following equation: KU) + i = Tr (Ya7t (j) + lBi) ^ bK {j) + i ^ 〇 ^ j ^ ml? 0 ^ i ^ rl ( 22) bjr (j) + i + mr = 7 &gt; (yc ^) + i + / Mr4), 〇sUr-2 (23) Exhausted), Ujsm], i = rl (24) Since equation (22) is No calculation is required. Therefore, according to equation (23-24), the structure of the base conversion unit can be divided into r sub-base conversion units. For the convenience of explanation, we will take the trinomial polynomial x12 + xVl, m = 4, n = l, r = 3 as examples to illustrate the structure of the base conversion unit. From Jt (j) = r (m-l) + jr (m-n) mod mr, the calculation of equation (24) can be obtained as 22 (Please read the precautions on the back before filling this page)-, v &quot;

T Printed by the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives. The paper size applies to Chinese National Standards (CNS) A4 specifications (21 OX 297 mm) 589570 A7 B7 i. Invention description (α |) Under: (1) +14 = Office 20 = do 11 + do 8 ~~ (2) +14 = \ l = + ~~ ^ (3) +14 = &amp; 14 + fo2 As the above equation, the subbase conversion unit is revealed as shown in Figure 8 (b) As shown. We find that the structure of the subbase conversion unit is the same as the base conversion unit designed by the trinomial polynomial x4 + x + l. When i = 〇, the calculation of equation (23) can be obtained as follows: ^ π (0) +12 ~ Office 21 = Office 9 + Office 12 k ⑴ + 12 = Office 18 = Office 9 + Office 6 (2) +12 = ^ 15 = ^ 6 + ^ 3 ~~ (3) +12 b12 = b3 + As the above equation, the subbase conversion unit constructed according to equation (24) can be modified as shown in Figure 8 ( a) shown. Figure 9 reveals the relationship between the output and input coefficients of the entire base conversion unit. As described above, for the form of a trinomial polynomial; τ + π + ι and gcd (m, n) = 1 and the basis conversion unit can be implemented using a smaller basis converter. Therefore, for a finite field GF (2m), the polynomial generated is a trinomial polynomial χ ^ + χ〃 + 1. If a higher-order term requires k-order power reduction, the complexity of the entire multiplier is always delayed as follows: m + k pulse period total 2-input XOR logic gates: m2 + m total 2-input AND logic gates: m2 ⑵AOP-based systolic double base multiplier polynomial form P (x) = xm + xm_1 + ... + x + l Called the all-in-one polynomial (also 23 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm). —-* (Please read the precautions on the back before filling out this page) • Call the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employees 'cooperatives 4-5Θ. 589570 Printed by employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_______ V. Description of the invention (22) one polynomial (AOP). Let the finite field GF (2m) be generated by the indecomposable polynomial P (x). The element A of GF (2m) can be expressed as: A = a〇 + aicx + &quot;-+ am-iam · 1, ai = {l or 0}, where a is the root of P (x). Unfortunately, it is not indecomposable for any m-degree congruent polynomials. 'Integers from 0 to 100 are indecomposable congruent polynomials, such as: 2, 4, 10' 12, 18, 28 , 52, 58, 60, 66, 82, 100. Because a is the root of P (x), ρ (α) = 0. When P (a) = 0, we can get an + 1 = 0 or 0 ^ = 1. Therefore, through the characteristic of 乂 = 1, we can easily simplify higher-order terms such as ap and pa m. In order to reduce the complexity of the circuit, the elements of the finite field A = a〇 + aicx + ... + am-ioT1 are all represented as A ^ Ao + AiCx + ·· ++ Amam, where AiEGF⑵ and H + 1, and the basis {1, 〇 ^ 2, ..., 〇 ^ are called the polynomial base {1, ", ..., 〇 ^} extended base, also known as the polynomial cycle base. The corresponding relationship for all elements is shown in Figure 10. Usually without losing this feature, this element can also be expressed as an extended double base. When cxm + 1 = l will produce am + 1 = aM, Uism-l, assuming B ^ Bopo + B ^ +. U + Bmpm is an element of 0? (201). Therefore, calculating 0 &lt; U2m, we can get ζ = Sm + i + 1 = Bt? 〇 &lt; i &lt; m-1 and K = Bm are expressed by the above elements. According to equation (10), the circuit of the AOP-based systolic multiplier requires only a double base multiplication unit, and Its structure can be extended from mxm to an array of (m + 1) x (m + 1), and each cell is defined as a U cell. We take m = 4 as an example, if A = A〇 + Ai〇c + A2〇c2 + A3〇c3 + A4〇x4 and B = ________24__ This paper standard applies to China National Standard (CNS) A4 specification (21 OX 297 male thin 1 tmMmmmmf tmmmmmmmmm n-MBBl In imte —i ^ i 11 am— flu m 11 1_ϋ · ϋ · — V Guang * (Please read the notes on the back before filling this page) 589570 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs System five, description of the invention (: 3) Β〇β〇 + Βφβ Β2β2 + Β3β3 + Β4β4 are the two elements of GF (24), assuming c = C〇P〇 + Clpl + C202 + C303 + C404 is the two elements A and B Product, according to the multiplication calculation rule of equation (10), we can get the following results β〇βΐ β2 / ¾

AqBq A4Bq A4Bi A3B2 a4b4 a0b, a3b0 a4b2 A2Bx 乂 界 ^ B4 AqB2 AJo A4B3 Λ3B3 A1B2 A2B4 A0B3 ΑλΒ0 + A2B2 A2B3 Αβ3 AtB4 A0B4 ~ CQ ~ QC ~ QC-based QC graph; Dual base multiplier. In Figure 11, the array cell Uu, if i + j ^ g number, the output signal A of the array cell Uu is connected to the array cell input signal A, and the output signal B of the array cell Uu is connected to the array. The input signal B of Um + i; if i + j = odd, the output signal A of the array cell U㈩ is connected to the input signal A of the array cell Uhh, and the output signal B of the array U 糸 is connected to the array cell Ui +1, j + 1 input signal B. When i + j = odd, each U cell executes the calculation of 9 hearts +; + 1) / 2 children ("㈣ / 2 &gt; + c; when i + j = even, each U cell executes ς . = Λ ^ /) / 2; calculation of Λ (^ 2; + (:.); In addition, it is worth mentioning that for different m 値, the circuit of a single unit is the same. The difference is only the unit The size of the combination is very low, so the circuit design cost is also very low. In summary, although the present invention has been disclosed as above with a preferred embodiment, its 25 paper standards are applicable to the Chinese National Standard (CNS) A4 Specifications (210X297mm) (Please read the precautions on the back before filling out this page}-、 可 589570 A7 B7 V. Description of the invention (〇4) It is not intended to limit the present invention. Anyone skilled in this art will not leave The spirit and scope of the present invention can be modified and retouched. Therefore, the scope of protection of the present invention is defined by the scope of the patent application. (Please read the precautions on the back before filling this page) Bureau of Intellectual Property, Ministry of Economic Affairs The paper size printed by the employee consumer cooperative is applicable to China National Standard (CNS) A4 (210X297) %)

Claims (1)

589570 A8 B8 C8 D8 6. Scope of patent application (please read the precautions on the back before filling this page) 1. A low-complexity systolic array-type double-basis multiplier with limited field GF (2m), its circuit characteristics include There are: a device 'data decoding for error control encoding and encryption / decryption of cryptography' The multiplier performs a multiplication operation on a first element A and a second element B in a finite field GF (2m) to obtain A third element C, where element A is an expression with a polynomial basis (I, α, α2, ..., ^ 1), elements B and C are an expression with a double basis, and the finite field GFCr) is impossible The 'and α produced by the decomposed polynomial are the roots of the indecomposable polynomial; the first element A is represented as an m-bit A = a〇 + aia + a2〇c2 + ·., And the second element B is Expressed as a m-bit BzzboPo + b ^ !, the third element C is expressed as a m-bit C = C〇pG + (: ΐβ 1 + C2p2 + ·· ++ Cm.lpm.l, where The coefficients of all elements are equal to 0 or 1. The multiplier includes two units: double base multiplication and double base conversion; The circuit structure of the double base multiplication unit is composed of small cells of the same m2 to form an m X m array; each small cell contains three (or four) input signal lines and three (or four) output signal lines; Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperative, each small cell contains an AND, an XOR gate and three (or four) one-bit registers; the circuit structure of the dual-base conversion unit consists of a tree-like 2- Input X0R gate. 2. Low-complexity systolic array type double base multiplier with limited field GF (2m) as described in the first patent application scope. The multiplication unit of this multiplier contains two small cells (V And U cells), each V cell is 27___i______ This paper size applies to Chinese National Standards (CNS) A4 specifications (210X 297 mm) 589570 A8 B8 C8 D8 6. The scope of application for patents is enforcement = w 又 ㈣_ &gt; +, · + Calculations; each u cell performs the calculation of S ·-β &lt; Η) / 2Α (Η) / 2 &gt;+; · + scoop. 3. The low-complexity systolic array-type double base multiplier of the finite field GF (2m) as described in the second item of the patent application, the output signal A of the array cell Uu is connected to the array cell Ui + u + i. Input signal A, the output signal B of the array cell Uu is connected to the input signal b of the array cell Ukw; the output signal a of the array cell Vu is connected to the input signal A of the array cell Vhh 'the output signal b of the array cell v 细胞Input signal B connected to the array cells Vi + 1, j + 1. '' 4. As described in the first item of the scope of the patent application, the finite field GF (n is a low-complexity systolic array type double base multiplier. If all the elements of the finite field GF (2m) are composed of the indecomposable trinomial polynomial χ% χη + 1 is generated, where gcd (m, n) = 1, and the coefficient of the second element B enters the base conversion array processor in an arrangement of ⑼ ⑴. 5. As the fourth item in the scope of patent application The low-complexity systolic array-type double base multiplier of the finite field GF (2m), wherein the output ig number of the base conversion array processor is output in the manner of (2) + m ... 6. The low-complexity systolic array-type double base multiplier of the finite field GF (2m) as described in the first item of the scope of the patent application, if all the elements of the finite field GFG111) are composed of the indecomposable trinomial polynomial χ ^ + χΜ +1, where gcd (m, n) = 1 and r ^ 2, the coefficient of the second element B is divided into i groups, O ^ Ur-1, each group of coefficients is also ca \ (1) + ί The arrangement of k (/ n_1) + i ·) enters the sub-base conversion array processor. 7. The low complexity of the limited field GF (2m) as described in item 6 of the scope of the patent application • 28 __: __________________ This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back first (Fill in this page again) Γ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 589570 A8 B8 C8 D8 VI. Patent-Patented Systolic Array Double Base Multiplier, where the coefficient of the second element B is the 'i-th group coefficient, OsUr -2, input to the modified subbase conversion array processor, the output of this subbase conversion array processor is (π (〇) · Η · + / Π, π ⑴U »); the i = rl group coefficient input To the subbase conversion array processor, the output of the subbase conversion array processor is. ^ Π (1) + ζ + / ηΓ ^ π (2) + ΐ + ηΐΓ ^ r (ml) + / +; 7ir) 〇 8. The low-complexity systolic array type double base multiplier with a finite field GF (2m) as described in item 7 of the scope of the patent application, wherein the array cell Uu, if i + j = even number, the output signal of the array cell Uu A is connected to the input signal A of the array cell Ui + 1, w. The output signal B of Uu is connected to the input signal B of the array cell; if an odd number, the output signal A of the array cell team is connected to the input signal A of the array cell Uaw, and the output signal B of the barrier cell Uu is connected to The input signal B of the array cell 仏 + ^. 9. As the low-complexity systolic array double-basis multiplier with a finite field GF (2m) as described in item 8 of the scope of the patent application, when i + j = odd, each U cell executes c + 7 ++ ) / 2: Λ »1) / 2 &gt; + ς · 's calculation; when i + j = even number, every ~ U cells are executed by C &lt; (w) / 2A (w) / 2 &gt; + C / Calculation. 10. The low-complexity systolic array-type double base multiplier of the finite field GF (2m) as described in item 1 of the scope of the patent application, if all elements of the finite field GF (2m) are indecomposable all-one polynomials ( AOP), the structure of the multiplier only includes a double base multiplier, and the calculation delay of the multiplier only needs m + 1 pulse wave periods. 1 1. As the paper size of the limited field GF (2m) as described in Item 10 of the scope of patent application, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applicable (please read the precautions on the back before filling this page) ) T Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 '589570 A8 B8 C8 D8 VI. Patent application with complex systolic array type double base multiplier, the multiplier consists of (m + l) x (m + l) Array cells, each of which contains an AND gate, an XOR gate, and three bit registers. 1 2. The low-complexity systolic array type double base multiplier with a finite field GF (2m) as described in item 11 of the scope of the patent application, the three one-bit register, in which the first element A is represented Is an m + 1 bit (Α = Α〇 + Αια + A2CX2 + &quot;. + Amam) 'The first element B is represented as an m + 1 bit B = Βοβο + Βφ ι + Β2β2 + ·· · + ΒΓηβ, the third element c is expressed as a m + 1 bit C = C〇P〇 + ClP 1 ++ ... CmPm 0 1 3. The finite field as described in the first item of the scope of patent application GF (2m) low-complexity systolic array type double base multiplier. The propagation delay of each pulse period requires a calculation time of an AND logic gate and an X0R logic gate. 14. As in the low-complexity systolic array type double base multiplier of the finite field GF (2m) described in the first item of the scope of the patent application, if all the elements of the finite field GF (2m) are composed of the unresolvable trinomial polynomial xm + x + l, the calculation delay of this multiplier only needs m + 1 pulse period; if all elements of the finite field GF (2m) are generated by the indecomposable trinomial polynomial xm + xn + l, Among them 2 ^ i &lt; m / 2l, the calculation delay of the multiplier only needs m + 2 pulse wave periods. ________ 30 — This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) i——Order Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs