TW589536B - Memory operating method and device - Google Patents

Abstract

The present invention provides a memory operating method and device, which uses an address latch comparison module to determine if the data to be read is stored in the buffer; if so, making a control module to read data from the buffer, then transmitting the data to a receiving unit by a bus controller; if not, making the controller to send out a reading signal to a memory control signal generation module for generating a data reading signal to a memory, then storing the read data into the buffer, and transmitting the data to the receiving unit through the bus controller. The memory operating device further can be provided for the user to conduct the memory operations, such as data writing, data erasing and reading identification code.

Description

589536 V. Description of the invention (1) [Field of the invention] A method and device for operating a memory, which is more easily evaluated through a hard penetrating device, and a, which is related to the background of the invention [body background] operation control Method and device of reminiscence. With the development of I1's information technology, LeiGongtai has shown a trend of doubling year by year. 'UK :::::; The body capacity has been equal to more than half of the cost of the product itself ::: = = = _ Production cost of flash memory (κ copy of the memory product came into being, such as fast body (EE: PRQm mory), compared to the electronic erasing type read-only memory, 1 # 不 i 'EDIT memory De-write ... block "Ϊ Bit: special programming equipment, the market share of physical memory ί = fi; now: Λ flash memory includes anti- or flash memory (_ memory data read Shaanxi write Flash erase 1 to remove hidden memory (NAND Flash), etc. For fast flash ΐ: (2) said that M contains a loss Λ Γ C * low solid state memory: f can reach 3 to 35 blocks' ,: The number of ε f depends on the memory density. You only need to change the invalid area to / block, which will not affect the & block of the valid block in the address map.

1 ； if ^: ^ A (η 5 ^ 4§ With block i ds as 2 5 6 or 512 bits and groups (advanced level. I right & t operation, then a block is 4k, 8k Or 161 ^ has the division of quick editing and erasure ^ qi 6k bit 589536 V. Description of the invention (2) However, due to the current production technology and cost constraints Exceptions are not used, ^ & and flash memory 闪 miscellaneous media τ, so the same confluence L body is not used in the data and address system, resulting in slow random read speed and can not be used to move the byte. Reverse and flash memory data can be read separately. This Access) #ill (Sequential AcceSs) ^ ^ (祚 Read page read operation must go through the set / lock command, set / miscellaneous, type. Ordering, etc. The data read and data transfer in page-reading mode are also different. In the conventional application, for the anti-flash memory operation, software control is used to generate the operation sequence A f The memory operation is complicated and inefficient. Therefore, how can the operation of the flash memory be performed without sacrificing the system? Benefits and high efficiency ^ 2 efficiency, the same as the low production cost of the memory itself, is the problem that the program development I = flash division needs to be solved. A more physical engineering [Objective and summary of the invention] The invention mainly provides a memory operation method and device, so as to provide users with a hardware control interface for performing data reading, entry, deletion, and reading of identification codes of the memory. According to the above-mentioned purpose, the memory operating device of the present invention includes: at least a control state register for recording the control state of each module and unit of the device, and receiving and transmitting control signals ^ ^ Control module; one for receiving ^ body data address transmission signals from a central processing unit and flash-locking for memory data storage 2

16971.ptd

V. Description of the invention (3) Address latch comparison module for address comparison;-, data buffer unit;-a signal for receiving the temporarily misstored waiting to be transmitted operation signal and issuing according to the signal-ζζ ,, and The memory system issued by the memory reads and writes and erases the data. The memory is used to secure the module, and a memory control signal is used to generate the bus # = 2. The memory control signal is generated with a transmitter and a receiver. And—the second σ industrial signal and at least the bus control module of the controller through the memory operating device, ^ when reading data, the method of making the address widely ordered redundant memory operation system data Whether it is stored in the buffer unit is compared with the data in the buffer unit which is judged by the module to read the data. # Right 疋 makes the control module self-report to a receiving unit; if not, then a The bus control module sends data to the memory control signal generation module. The second control module sends a read signal to the memory, and then uses the read data 5 to generate a data read signal to the bus control module. Group sends data to the buffer In addition to unit through, to write personal data ", the receiving unit. Number to the control signal generation module; i causes the control module to send a write letter and send a write signal to the memory f times' to cause the control signal to generate a module mode; further, the address flashes S It is wrong to let the memory enter the write data line. The first time the data is written, the data comparison module is sent to the central processing unit to execute the control k generation module to flash lock, and finally, the memory is used to execute the data. Write again. "," ,, the input signal and the flash address signal to the recorder. In the erase mode, it is the erase signal sent by the human element. "7 The control module will erase the central processing unit for a long time. ', The shell material address is transmitted to the control signal

16971.ptd 589536 V. Description of the invention (4)-Generating module; Secondly, the control signal generating module sends an erasing signal. And the data address to be erased to the memory is used to allow the memory to enter the erasing. Data mode; and finally, the central processing unit is caused to judge whether the memory erasing is successful. Furthermore, when reading the identification code mode, the control module is instructed to transmit the read identification code signal sent by the central processing unit to the control signal generating module, and secondly, the Rong control 彳 § number generating module issues A reading of the identification code signal to the side memory allows the body to send the identification data; and finally, the central processing unit is caused to read the identification code. Compared with the conventional memory operation technology, the memory operation method and t of the present invention are set at k for the user to perform data reading, writing, erasing, and reading identification of the memory through a hardware control interface. Code, to improve the efficiency of memory operation, avoid the increase of memory operation cost, and solve the problem of compatibility between different versions of operation = body program. [Inventive Example] Please refer to the memory operator for reading the memory data on the flash memory 10 and reading the body identification code. The user uses the memory operation to reset the display including other bases. The invention is illustrated in the following examples

Method and memory operating device 1 are operations of personal computer 2 applied to a memory 2 of a NAND flash. The operation mode includes at least writing of memory data and erasing of memory data. And remember,. In addition, the personal computer 10 includes a central processing unit 12 for driving the 1 according to a memory operation instruction input by the personal computer 10. In addition, the personal computer 1 storage unit and wheel-in and

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589536 V. Description of the invention ^^ " " '-一 ~ _ and equipment are necessary for the operation of general personal computers. The government does not describe the structure here, ϊ 2 2 2 2 2 图 图 2 'ΐ 其中' 其中 ΐ ΐ 2 2 2 其中 其中 2 ΐ '' '' ΐ 其中 其中 其中 其中 其中 其中 其中 其中 2 The lock comparison module 22, a buffer unit, a memory module 26, and a bus control module. Suzette;:; Note that the body ° 2V has been connected to the central processing unit 1 12 and # = # of body 2. Among them, the central processing unit 12 contains the data sink, the memory 2 contains the bus, the bit write: / resource miscellaneous, the renrenzheng / shell multiplexing bus, the bit The address latch generates signals such as p P-1 lock, chip activation, reading, and writing. In addition, the reading of the data in memory 2 by this element I2 is similar to that of read-only memory (ROM). The control module 20 includes a control state temporary storage unit (not shown in the figure) &5; memory operation device 1 records received from the central processing order: 丄 2: memory operation instructions issued by the cat Operating state, and in accordance with the operation ^ i, each module and unit of the memory operating device 1 receives and transmits and controls the address latch comparison mode The group 22 is used to flash lock the transmission signal of the memory data address of the central processing unit 2 to perform the comparison of the storage address of the memory. The comparison of the storage address of the memory data is used to perform the operation. Whether the memory data exists. The second buffer unit 24 is used to provide a specific memory area of the memory operating device i to retain the data waiting to be transmitted.

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589536 V. Description of the invention (6) The memory control signal generating module 2 6 receives the memory operation signal sent by the control module 20 and sends a control signal to the memory 2 according to the operation signal to control the memory 2 Memory 2 performs data reading, writing, and erasing. The bus control module 28 generates bus commands and control signals and includes at least a transmitter, a receiver, and a mode controller (not shown) for the central processing unit 1 and the memory. 2 and the buffer unit 24 transmit and receive data. Through the memory operating device 1, the steps of implementing the memory operating method are as follows: When reading data, first, the central processing unit 12 is caused to issue a reading based on the data that the user wants to read. Take the data address request signal to the address latch comparison module 2 2. Secondly, the address latch comparison module 22 is made to judge whether the data to be read by the read data address request signal has been stored in the buffer unit 24. If so, the control module 20 is read from the buffer unit 24 and then sent to the central processing unit 1 2 via the bus control module 28; if not, the control module 2 is sent 0 sends a read signal to the memory control signal generating module 2 6 to generate a data read signal to the memory 2, after that, the memory 2 will enter a data read mode to read the desired read The fetched data is transmitted to the buffer unit 24. Then, the data is transmitted to the central processing unit 12 through the bus control module 28. It should be noted that, in this embodiment, the buffer unit 24 is divided into four buffers. When the data to be read is not stored in the buffer unit 24,

16971.ptd Page 9 589536 V. Description of the invention (7) When any buffer is read, the data is read from the memory 2 and placed in the buffer unit 24 with the lowest priority (priority). The priority of the buffer is based on the value obtained by comparing the previous priority with the current priority in combination with a look-up table, and the look-up task is performed by a look-up table circuit 202. And each buffer has a specific number of bytes as the boundary address, and the address and data of the buffer are updated synchronously. When writing data, first, the central processing unit 12 is caused to send a write data address request signal to the address latch comparison module 22 according to the data the user wants to perform writing. Secondly, the address latch comparison module 22 is caused to latch the currently written data address and transmit a write request signal to the control state temporary storage unit of the control module 20. After that, the control module 20 is caused to send a write request signal to the memory control signal generating module 26, and the request signal and the address are written to the memory control signal generating module 26 through the memory control signal generating module 26. The memory 2 is driven into a data writing mode. Finally, the central processing unit 12 transmits the data to be written to the memory 2 through the control module 20. When erasing data, first, the central processing unit 12 is caused to send an erasure data address request signal to the address latch comparison module 22 according to the data to be erased by the user. Secondly, the address latch comparison module 22 is configured to latch the current erasure data address and send a request erasure signal to the control state temporary storage unit of the control module 20.

16971.ptd Page 10 589536 5. After the description of the invention (8), 'the control module 20 sends a request erasing signal to the memory control signal generating module 26, and then generates a module through the memory control signal The group 2 6 sends an erase request signal and an erase address to drive the memory 2 to perform data erase. Subsequent 'makes the central processing unit 12 pass the judgment of whether the data is erased in memory 2 or not. When the identification code is read, first, the central processing unit 12 is caused to send an identification code reading request signal to the address latch comparison module 22 according to the identification code that the user wants to perform reading. Secondly, 'the address latch comparison module 22 will read the identification code bit this time, knock the door lock and send a signal requesting to read the identification code to the control module 5 0 of the control state temporary storage unit. . After that, 'the control module 20 sends a request to read the identification code signal to = $, the body control signal generation module 26, and sends the request to read the identification code signal and reads through the memory control signal generation module 26. The identification code address is driven, and the memory 2 executes reading the identification code. After fetching ', the memory 2 transmits another code to the central processing unit 12 俾 through the bus control module 2 8 for reading. Refer to FIG. 3 (A), which shows the memory operating method of the present invention, which is to execute the process of writing data into the memory. In step S3 01, the central processing unit 12 is instructed to send a read data address request signal to the address flash and comparison module 22 according to the data that the user desires. Then, step S302 is performed. In step S3 0 2, the address flash lock comparison module 2 2 determines the read.

Page 11 589536 V. Description of the invention (9) Whether the data to be read by the data address request signal has been stored in the buffer unit 24, if not, proceed to step S 3 0 3; otherwise, proceed to step S 3 0 6. In step S 303, the control module 20 is caused to send a read signal to the memory control signal generating module 26 to generate a data read signal to the memory 2, and then proceed to step S 3 0 4. In step S304, the memory 2 will enter a data reading mode to transfer the data to be read into the buffer unit 24, and then proceed to step S305. In step S305, data is transmitted to the central processing unit 12 through the bus control module 28. In step S306, the control module 20 is caused to read data from the buffer unit 24 and then send the data to the central processing unit 12 through the bus control module 28. Please refer to FIG. 3 (B), which shows the flow of executing the memory reading method by the memory operation method of the present invention. In step S 3 11, the central processing unit 12 is caused to send a write data address request signal to the address latch comparison module 22 according to the data to be written by the user, and then step S is performed. 3 1 2. In step S 3 1 2, the address latch comparison module 22 is configured to latch the currently written data address and send a write request signal to the control state of the control module 20 temporarily. In the unit, step S3 1 3 is performed next. In step S3 1 3, the control module 20 is caused to send a request writing signal to the memory control signal generating module 26, and the request writing signal is sent through the memory control signal generating module 26. Write address to drive the memory

16971.ptd Page 12 V. Description of Invention (10)

The body 2 enters a write data mode. Then, in step S34, the & person performs step S31 4. The T central processing reserves a 20 to transmit the information of the person who wants to write to the ⑼ ^ 12, that is, through the control module, please refer to Figure 3 (C), which is ^ body 2. The method is to execute the memory erasure tree, a memory operator who is not the present invention. In step S321, the user is instructed to participate. Issue of data for erasing—Erasing management unit 12 locks comparison module 2 2 according to the user's desire, and then sends a Satoshi λ address request signal to the address and latches it in step S322, so that the address ^ The data address is latched and transmitted_ In the song comparison module 22, the control status temporary erasing unit is erased, the 2 1 erasure signal is sent to the control module 20 in step S323, and the control step is executed. S323. To the memory control signal generation module, the number generation module 2 6 sends out the heart rate, n through the δ δ hidden body control signal body 2 to perform data erasure, and then steps and addresses to drive the memory.

It 1 ^ ^ Qingcha read Figure 3 (D), which is the method of displaying the identification code of the memory to read the flow ... The private owner in step S331, so that the Nakamoto Lu port 0 to perform reading The central processing of the mantis w 12 is locked according to the user's desire to lock the comparison mode and group ^ 2,] ^ ^ Γ ^ read the request signal to the address flasher and proceed to step S 3 3 2.

At step S3] 9tb X identification code address is given = j lock comparison module 22 reads, transmits and clears the identification code signal to the control

589536 V. Description of the invention (11) The module 2 0 controls the code signal in step S333 to the memory control signal generating module code address to drive the record S334 ° transmits the identification code data in step S334 28 The above description is only a good example. The memory operations that are not used for invention are defined in the following application body or method. If the changes are equivalent to the following or equivalent, the state is temporarily stored in the unit, and then step s333 is performed. 'Let the control module 20 issue a request to read the identification and control number generation module 26, 俾 issue a request to read the identification code signal through the memory ^ and read the identification memory 2 to execute the reading identification code, and then proceed Steps to the body 2 are read by the bus control module book processing unit 12. In the present invention, downshifting limits the scope of this c method and device comparison method as well as the technical content of the shang jin yi bei. The scope of this patent is that the technical content of the patent is a broadly described patent application: 2 The technologies completed by Taxi will be regarded as exactly the same as those defined in 14 circles, and are covered by this patent scope.

16971.ptd Page 14 589536 Schematic description [simple schematic description] Figure 1 is a schematic diagram of an application architecture, used to show the basic structure of the memory operating device of the present invention applied to a personal computer; Figure 2 is a The schematic diagram of the basic structure is used to show the basic structure of the memory operation device; and Figures 3 (A) to 3 (D) are a flowchart showing the flow of the memory operation method of the present invention in performing the memory operation . [Symbol number] 1 Memory operating device 2 Memory 10 Personal computer 12 Central processing unit 2 0 Control module 22 Address latch comparison module 2 4 Buffer unit 26 Memory control signal generation module 28 Bus control mode group

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Claims (1)

589536 VI. Application for patent scope 1. A memory operation method for providing a user to perform a memory operation in an electronic device through a memory operation device. The electronic device includes at least a central processing unit and a memory. The memory The method includes: making a central processing unit send a read data address request signal to a bit latch comparison module according to the data the user wants to read; and making the address latch comparison module judge Whether the data to be read by the read data address request signal has been stored in a buffer unit; if so, a control module is caused to read the data from the buffer unit and then transmit the data through a bus control module. Data to a central processing unit; if not, the control module is caused to send a read signal to a memory control signal generating module to generate a data read signal to the memory, and the memory will enter a The data reading mode is used to transmit the data to be read into the buffer unit, so as to transmit data to the center through the bus control module. Processing unit. 2. For the method according to item 1 of the patent application scope, wherein the electronic device may be any one of a personal computer, a notebook computer, a palmtop computer, a personal digital assistant, a server, and a workstation. 3. For the method of claim 1 in the scope of patent application, the memory may be a reverse flash memory (N A N D F 1 a s h Me m 〇 r y). 4. A memory operation method for providing a user to perform a memory operation in an electronic device through a memory operation device. The electronic device includes at least a central processing unit and a memory. The memory gymnastics 16971.ptd Page 16 589536 6. The method of patent application includes: making a control module send a write signal to a control signal generating module; making the control signal generating module send a write signal to the memory In order to put the memory into a write-lean mode, an address latch comparison module latches the data write address when the central processing unit performs the first write; and the control signal is generated. The module sends a write signal and a flash lock address signal to the memory to perform data writing. 5. If the method of claim 4 is applied, the electronic device may be any one of a personal computer, a notebook computer, a palmtop computer, a personal digital assistant, a server, and a workstation. 6. If the method according to item 4 of the patent application is applied, the memory may be a reverse flash memory (N A N D F 1 a s h Me m 〇 r y). 7. A memory operation method for providing a user to perform a memory operation in an electronic device through a memory operation device. The electronic device includes at least a central processing unit and a memory. The memory operation method includes: A control module is instructed to transmit the erasing signal and the data address to be erased from the central processing unit to a control signal generating module; the control signal generating module is to issue an erasing signal and the data address to be erased Until the memory is put into the data erasing mode; and the central processing unit is caused to judge whether the memory erasing is successful. 16971.ptd Page 17 589536 6. Scope of patent application 8. For the method of the seventh scope of patent application, the electronic device can be a personal computer, a notebook computer, a palmtop computer, a personal digital assistant, a server, and a workstation Any of them. 9. The method according to item 7 of the patent application scope, wherein the memory can be a reverse flash memory (N A N D F 1 a s h Me m 0 r y). 1 0. A memory operation method for providing a user to perform a memory operation in an electronic device through a memory operation device. The electronic device includes at least a central processing unit and a memory. The memory operation method includes : Order a control module to transmit the read identification code signal sent by the central processing unit to a control signal generation module; make the control signal generation module send a read identification code signal to the memory so as to make the memory Sending the identification code data; and causing the central processing unit to read the identification code. 1 1. The method according to item 10 of the patent application scope, wherein the electronic device may be any one of a personal computer, a notebook computer, a palmtop computer, a personal digital assistant, a server, and a workstation. 12. The method according to item 10 of the scope of patent application, wherein the memory can be a NAND flash memory and a NAND flash memory. 1 3. A memory operating device for providing a user to perform memory operations in an electronic device. The electronic device includes at least a central processing unit and a memory. The memory operating device includes: 'a control module To record the control status of each module and unit of the memory operating device and receive and transmit control signals; 16971.ptd Page 18 589536 VI. Patent application One-bit latch comparison module is used to receive the memory data address transmission signal sent from the central processing unit and flash lock it to perform memory data storage bit Address comparison; a buffer unit for temporarily storing data to be transmitted; a memory control signal generating module for receiving a memory operation signal sent by the control module and sending a control signal to a memory according to the signal The system controls the memory to perform data reading and writing and erasing; and a bus control module for generating bus commands and control signals for the units and modules of the memory operating device to transmit data to each other. 14. The device according to item 13 of the scope of patent application, wherein the electronic device may be any one of a personal computer, a notebook computer, a palmtop computer, a personal digital assistant, a server, and a workstation. 15. The device according to item 13 of the scope of patent application, wherein the memory can be a reverse flash memory (N A N D F 1 a s h Me m 0 r y). 16. The device according to item 13 of the scope of patent application, wherein the control module further includes a control state temporary storage unit. 17. The device according to item 13 of the scope of patent application, wherein the bus control module includes a transmitter, a receiver and a mode controller. 18. The device according to item 13 of the scope of patent application, wherein the device further includes a table lookup module to judge the priority order of each buffer in the buffer unit. 16971.ptd Page 19