TW589536B - Memory operating method and device - Google Patents
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589536 五、發明說明(1) 【發明領域】 一種記憶體操作方法以及裝置, 士 於一種透過硬俨穿置择祚批引f 更评而a之,係有關 【發明背景】體置彳作控制圮憶體之方法與裝置。 I1通者資訊科技之發展,雷工太 呈現逐年倍增之趨勢’UK:::::;體容量已 =產品本身成本一半以上:::: = : = =已 目的,部分定吾士士士 _ 產成本之 閃記憶體(κ ΐ本之記憶體產品應運而生,例如快 體(EE:PRQm m〇ry),相較於電子抹除式唯讀記,1# 不i ’編憶體得-次寫…區塊“ Ϊ 位:特別之燒錄設備,物今記憶體市場佔有ί = fi;今:Λ閃記憶體包括有反或快閃記憶體(_ 記憶體之資料讀陕寫閃抹1己除隐體(NAND Flash)等。針對快閃 ΐ : ( 2)曰曰曰Μ包含有失Λ Γ C *低之固態記憶 :f大可達3至35個區塊',:戈ε f數目取決於記憶體密 能,僅需將失效區換於/ 塊不會影響有效區塊之 &塊於位址對映表中遮罩起來即可589536 V. Description of the invention (1) [Field of the invention] A method and device for operating a memory, which is more easily evaluated through a hard penetrating device, and a, which is related to the background of the invention [body background] operation control Method and device of reminiscence. With the development of I1's information technology, LeiGongtai has shown a trend of doubling year by year. 'UK :::::; The body capacity has been equal to more than half of the cost of the product itself ::: = = = _ Production cost of flash memory (κ copy of the memory product came into being, such as fast body (EE: PRQm mory), compared to the electronic erasing type read-only memory, 1 # 不 i 'EDIT memory De-write ... block "Ϊ Bit: special programming equipment, the market share of physical memory ί = fi; now: Λ flash memory includes anti- or flash memory (_ memory data read Shaanxi write Flash erase 1 to remove hidden memory (NAND Flash), etc. For fast flash ΐ: (2) said that M contains a loss Λ Γ C * low solid state memory: f can reach 3 to 35 blocks' ,: The number of ε f depends on the memory density. You only need to change the invalid area to / block, which will not affect the & block of the valid block in the address map.
1 ; i f^: ^ A (η 5 ^4§ 以區塊i ds二為2 5 6或512個位元、组(進 元級。I右& t 作,則一區塊為4k、8k或161^ 具有快速編輯與抹降之分处 ^ q i 6k位 589536 五、發明説明(2) 然由於現時之生產技術及成本之限 / , · 之位址/資料分開之匯流排方式,反 住住不採用並 4丁 ,^ &及快閃記愔雜介τ 例外,故於資料與位址係採用同一匯流 L體亦不 取,導致隨機讀取速度慢且不能案位元組隨 外,反及快閃記憶體之資料讀取得區分輯。此 Access) #ill ( Sequential AcceSs) ^ ^ ( 祚讀頁讀取操作須經過置/鎖命令、置/雜〃、式。進订 等三少驟’而讀頁模式下之資料讀取與傳^讀取資料 亦有所不同。在習知之應用中,對於反及椒^閃記憶體 作係採取以軟體控制來產生操作時序之方法A f憶體之操 為複雜且效率低。是故,如何能夠於不犧牲系:作流程較 時兼顧傳統快閃記憶體之操作便利與高效^ 2效率,同 記憶體本身之低廉生產成本,乃程式開發 I =快閃 師所亟待解決之問題。 一更體工程 【發明目的及概述】 為解決上述習知技術之缺點,本發明之主要 提供一種记憶體操作方法以及裝置,藉以提供使用者於 一硬體控制介面,用以執行記憶體之資料讀取、入過 除及讀取識別碼。 .、、、入、抹 根據以上所述之目的,本發明之記憶體操作裝置勺人 有:一至少包括有一控制狀態暫存器用以記錄該^憶^二 作裝置之各模組與單元之控制狀態並接收傳送控制信^ ^ 控制模組;一用以接收來自一中央處理單元所發出^ 體資料位址傳送信號並予以閃鎖以進行記憶體資料儲存21 ; if ^: ^ A (η 5 ^ 4§ With block i ds as 2 5 6 or 512 bits and groups (advanced level. I right & t operation, then a block is 4k, 8k Or 161 ^ has the division of quick editing and erasure ^ qi 6k bit 589536 V. Description of the invention (2) However, due to the current production technology and cost constraints Exceptions are not used, ^ & and flash memory 闪 miscellaneous media τ, so the same confluence L body is not used in the data and address system, resulting in slow random read speed and can not be used to move the byte. Reverse and flash memory data can be read separately. This Access) #ill (Sequential AcceSs) ^ ^ (祚 Read page read operation must go through the set / lock command, set / miscellaneous, type. Ordering, etc. The data read and data transfer in page-reading mode are also different. In the conventional application, for the anti-flash memory operation, software control is used to generate the operation sequence A f The memory operation is complicated and inefficient. Therefore, how can the operation of the flash memory be performed without sacrificing the system? Benefits and high efficiency ^ 2 efficiency, the same as the low production cost of the memory itself, is the problem that the program development I = flash division needs to be solved. A more physical engineering [Objective and summary of the invention] The invention mainly provides a memory operation method and device, so as to provide users with a hardware control interface for performing data reading, entry, deletion, and reading of identification codes of the memory. According to the above-mentioned purpose, the memory operating device of the present invention includes: at least a control state register for recording the control state of each module and unit of the device, and receiving and transmitting control signals ^ ^ Control module; one for receiving ^ body data address transmission signals from a central processing unit and flash-locking for memory data storage 2
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五、發明說明(3) 址比較之位址閂鎖比較模組;— 、 資料之緩衝單元;一用以接收該暫時錯存等待被傳送 操作信號並依據該信號發出—押 ζ、、'且所發出之記憶體 制該記憶體進行資料讀寫抹除二5唬至—記憶體藉以押 模組,·以及一用以產生匯流排# =之2憶體控制信號生成 有一發送器、一接收器及—卩二σ工制信號且至少包括 式控制器之匯流排控制模 透過該記憶體操作裝置, ^ 於讀取資料時,係令該位址广订冗憶體操作之方法係·· 資料是否儲存於該緩衝單元内鎖f較模組判斷所欲讀取之 該緩衝單元内讀取資料後復# 右疋 則令该控制模組自 料至一接收單元;若否,則,由一匯流排控制模組傳送資 至該記憶體控制信號生成模級二控制模組發出一讀取信號 該記憶體,復將所讀取之資5藉以生成一資料讀取信號至 該匯流排控制模組傳送資料儲存至該緩衝單元中以透過 此外,於寫人資料時",接收單元。 號至該控制信號生成模組;i令該控制模組發出一寫入信 發出一寫入信號至該記憶體f次’令該控制信號生成模組 模式;再者,令該位址閃S错以讓該記憶體進入寫入資料 行第一次寫入時將資料 比較模組於該中央處理單元執 5亥控制k號生成模組發送 予以閃鎖,以及最後,令 憶體藉以執行資料寫又。、”、、入信號及閃鎖位址信號至該記 又,於抹除模式時,係人 元所發出之抹除信號 ’、7該控制模組將該中央處理單 机久欲抹次 卞 ’、貝料位址傳送至該控制信號V. Description of the invention (3) Address latch comparison module for address comparison;-, data buffer unit;-a signal for receiving the temporarily misstored waiting to be transmitted operation signal and issuing according to the signal-ζζ ,, and The memory system issued by the memory reads and writes and erases the data. The memory is used to secure the module, and a memory control signal is used to generate the bus # = 2. The memory control signal is generated with a transmitter and a receiver. And—the second σ industrial signal and at least the bus control module of the controller through the memory operating device, ^ when reading data, the method of making the address widely ordered redundant memory operation system data Whether it is stored in the buffer unit is compared with the data in the buffer unit which is judged by the module to read the data. # Right 疋 makes the control module self-report to a receiving unit; if not, then a The bus control module sends data to the memory control signal generation module. The second control module sends a read signal to the memory, and then uses the read data 5 to generate a data read signal to the bus control module. Group sends data to the buffer In addition to unit through, to write personal data ", the receiving unit. Number to the control signal generation module; i causes the control module to send a write letter and send a write signal to the memory f times' to cause the control signal to generate a module mode; further, the address flashes S It is wrong to let the memory enter the write data line. The first time the data is written, the data comparison module is sent to the central processing unit to execute the control k generation module to flash lock, and finally, the memory is used to execute the data. Write again. "," ,, the input signal and the flash address signal to the recorder. In the erase mode, it is the erase signal sent by the human element. "7 The control module will erase the central processing unit for a long time. ', The shell material address is transmitted to the control signal
16971.ptd 589536 五、發明說明(4) -- 生成模組;其次,令該控制信號生成模組發出一抹除信號 . 及欲抹除資料位址至戎記憶體藉以讓該記憶體進入抹除資· 料模式;以及最後,令該中央處理單元判斷該記憶體抹除 是否成功。 再,於讀取識別碼模式時,係令該控制模組將該中央 處理單元所發出之讀取識別碼信號傳送至該控制信號生成 模組,其次,令戎控制彳§號生成模組發出一讀取識別碼信 號至邊圮憶體藉以讓讜圮憶體送出識別碼資料;以及最 後,令該中央處理單元讀取該識別碼。 相較於習知之記憶體操作技術,本發明之記憶體操作 方法以及t置彳于k供使用者透過一硬體控制介面,執行記 憶體之資料讀取、寫入、抹除及讀取識別碼,俾提昇記情 體操作之效率、避免記憶體操作成本增加以及解決操作= 體程式不同版本間相容性之問題。 【發明實施例】 請參閱第 記憶體操作方 為反及快閃記 1 0上進行該記 體資料讀取、 體識別碼讀取 用者透過該個 憶體操作袭置 復包含其他基 具中顯示於以下實施例中 尽發明之 丄圖16971.ptd 589536 V. Description of the invention (4)-Generating module; Secondly, the control signal generating module sends an erasing signal. And the data address to be erased to the memory is used to allow the memory to enter the erasing. Data mode; and finally, the central processing unit is caused to judge whether the memory erasing is successful. Furthermore, when reading the identification code mode, the control module is instructed to transmit the read identification code signal sent by the central processing unit to the control signal generating module, and secondly, the Rong control 彳 § number generating module issues A reading of the identification code signal to the side memory allows the body to send the identification data; and finally, the central processing unit is caused to read the identification code. Compared with the conventional memory operation technology, the memory operation method and t of the present invention are set at k for the user to perform data reading, writing, erasing, and reading identification of the memory through a hardware control interface. Code, to improve the efficiency of memory operation, avoid the increase of memory operation cost, and solve the problem of compatibility between different versions of operation = body program. [Inventive Example] Please refer to the memory operator for reading the memory data on the flash memory 10 and reading the body identification code. The user uses the memory operation to reset the display including other bases. The invention is illustrated in the following examples
法以及記憶體操作裝置1,係應用於一屬性 憶體(NAND Flash)之記憶體2之個人電腦 憶體2之操作,其操作模式至少包含有記憶 記憶體資料寫入、記憶體資料抹除以及記, 。又,該個人電腦1〇復包括有一用以依據/ 人電腦1 〇所輸入之記憶體操作指令驅動該 1之中央處理單元1 2。此外,該個人電腦1 本之儲存單元及輪出入設備,由於該等單Method and memory operating device 1 are operations of personal computer 2 applied to a memory 2 of a NAND flash. The operation mode includes at least writing of memory data and erasing of memory data. And remember,. In addition, the personal computer 10 includes a central processing unit 12 for driving the 1 according to a memory operation instruction input by the personal computer 10. In addition, the personal computer 1 storage unit and wheel-in and
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589536 五、發明說明^^ " " ' --一~_ 及設備均為一般個人電腦運作所必要 之,核先敘明。 政在此不另文述 構,ϊ ΐ閱2圖’其中顯示該記憶體操作裝置1之基本年 構如圖所示,該記憶體操作裝置1包含有一 γ制、 2〇二「位址閂鎖比較模組22、一緩衝單元以、1一記情 η ί成模ϊ26以及一匯流排控制模組以。須特;:; 記伊體°2V己Λ Λ裝置1需連接該中央處理單元12與該 =體2之#號。其中,該中央處理單元12包含有資料匯 該記憶體2則包含匯流排、位寫:/資⑻ 雜、人人 正/貝行複用匯流排、位址閂 产p P-1鎖、晶片致㊣、讀取及寫人等信號。又該 元I2對該記憶體2資料之讀取與—般對唯讀記憶體 (ROM)之方式並無不同。 該控制模組20係包含有一控制狀態暫存單元(未圖示 一以&供忒5己憶體操作裝置1記錄接收自該中央處理單 :丄2:斤發出之記憶體操作指令與操作狀態,並依據該操作 ^ i Ϊ動該記憶體操作裝置1之各模組與單元接收傳送控 該位址閂鎖比較模組22係用以將該中央處理單元丨2所 憶體資料位址傳送信號予以閃鎖藉以進行記憶體 二枓儲存位址比較,透過記憶體資料儲存位址之比較以 疋欲執行操作之該記憶體資料是否存在。 二該緩衝單元24係用以提供該記憶體操作裝置i一特定 之屺憶體區域俾保留正等待被傳送之資料。589536 V. Description of the invention ^^ " " '-一 ~ _ and equipment are necessary for the operation of general personal computers. The government does not describe the structure here, ϊ 2 2 2 2 2 图 图 2 'ΐ 其中' 其中 ΐ ΐ 2 2 2 其中 其中 2 ΐ '' '' ΐ 其中 其中 其中 其中 其中 其中 其中 其中 2 The lock comparison module 22, a buffer unit, a memory module 26, and a bus control module. Suzette;:; Note that the body ° 2V has been connected to the central processing unit 1 12 and # = # of body 2. Among them, the central processing unit 12 contains the data sink, the memory 2 contains the bus, the bit write: / resource miscellaneous, the renrenzheng / shell multiplexing bus, the bit The address latch generates signals such as p P-1 lock, chip activation, reading, and writing. In addition, the reading of the data in memory 2 by this element I2 is similar to that of read-only memory (ROM). The control module 20 includes a control state temporary storage unit (not shown in the figure) &5; memory operation device 1 records received from the central processing order: 丄 2: memory operation instructions issued by the cat Operating state, and in accordance with the operation ^ i, each module and unit of the memory operating device 1 receives and transmits and controls the address latch comparison mode The group 22 is used to flash lock the transmission signal of the memory data address of the central processing unit 2 to perform the comparison of the storage address of the memory. The comparison of the storage address of the memory data is used to perform the operation. Whether the memory data exists. The second buffer unit 24 is used to provide a specific memory area of the memory operating device i to retain the data waiting to be transmitted.
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589536 五、發明說明(6) 該記憶體控制信號生成模組2 6係接收該控制模組2 0所 發出之記憶體操作信號並依據該操作信號發出一控制信號 至該記憶體2藉以控制該記憶體2進行資料讀寫抹除之工 作。 該匯流排控制模組2 8係產生匯流排命令和控制信號且 至少包括有一發送器、一接收器及一方式控制器(均未圖 示),用以於該中央處理單元1、該記憶體2及該緩衝單元 2 4間進行資料之傳送接收。 透過該記憶體操作裝置1,於實施該記憶體操作方法 之步驟係如下所述: 於讀取資料時,首先,令該中央處理單元1 2依據使用 者所欲執行讀取之資料發出一讀取資料位址請求信號至該 位址閂鎖比較模組2 2。 其次,令該位址閂鎖比較模組2 2判斷該讀取資料位址 請求信號所欲讀取之資料是否已儲存於該緩衝單元2 4内。 若是,則令該控制模組20自該緩衝單元24内讀取資料後復 藉由該匯流排控制模組2 8傳送資料至該中央處理單元1 2 ; 若否,則令該控制模組2 0發出一讀取信號至該記憶體控制 信號生成模組2 6藉以生成一資料讀取信號至該記憶體2, 之後,該記憶體2即會進入一資料讀取模式藉以將該所欲 讀取之資料傳送至該緩衝單元2 4内。俾以透過該匯流排控 制模組2 8傳送資料至該中央處理單元1 2。 須特別說明者,係於本實施例中,該緩衝單元2 4分為 四個緩衝區,當所欲讀取之資料未儲存於該緩衝單元2 4之589536 V. Description of the invention (6) The memory control signal generating module 2 6 receives the memory operation signal sent by the control module 20 and sends a control signal to the memory 2 according to the operation signal to control the memory 2 Memory 2 performs data reading, writing, and erasing. The bus control module 28 generates bus commands and control signals and includes at least a transmitter, a receiver, and a mode controller (not shown) for the central processing unit 1 and the memory. 2 and the buffer unit 24 transmit and receive data. Through the memory operating device 1, the steps of implementing the memory operating method are as follows: When reading data, first, the central processing unit 12 is caused to issue a reading based on the data that the user wants to read. Take the data address request signal to the address latch comparison module 2 2. Secondly, the address latch comparison module 22 is made to judge whether the data to be read by the read data address request signal has been stored in the buffer unit 24. If so, the control module 20 is read from the buffer unit 24 and then sent to the central processing unit 1 2 via the bus control module 28; if not, the control module 2 is sent 0 sends a read signal to the memory control signal generating module 2 6 to generate a data read signal to the memory 2, after that, the memory 2 will enter a data read mode to read the desired read The fetched data is transmitted to the buffer unit 24. Then, the data is transmitted to the central processing unit 12 through the bus control module 28. It should be noted that, in this embodiment, the buffer unit 24 is divided into four buffers. When the data to be read is not stored in the buffer unit 24,
16971.ptd 第9頁 589536 五、發明說明(7) 任一緩衝區時,即自該記憶體2中讀取該資料並置於該緩 衝單元2 4中優先級(p r i 〇 r i t y)最低之緩衝區中,而該緩 衝區之優先級係依據先前優先級與目前優先級比較後所得 之值結合查表而出,而該查表工作則係透過一查表電路 2 0 2為之。且每一個緩衝區均有一特定數量之位元組為邊 界位址,且緩衝區之位址與資料是同步被更新的。 於寫入資料時,首先,令該中央處理單元1 2依據使用 者所欲執行寫入之資料發出一寫入資料位址請求信號至該 位址閂鎖比較模組2 2 。 其次,令該位址閂鎖比較模組2 2將本次寫入資料位址 予以閂鎖並傳送一請求寫入信號至該控制模組2 0之該控制 狀態暫存單元中。 之後,令該控制模組2 0發出一請求寫入信號至該記憶 體控制信號生成模組2 6,俾透過該記憶體控制信號生成模 組2 6發出請求寫入信號及寫入位址以驅動該記憶體2進入 一寫入資料模式。 最後,該中央處理單元1 2即透過該控制模組2 0將欲寫 入之資料傳送至該記憶體2。 於抹除資料時,首先,令該中央處理單元1 2依據使用 者所欲執行抹除之資料發出一抹除資料位址請求信號至該 位址閂鎖比較模組2 2。 其次,令該位址閂鎖比較模組2 2將本次抹除資料位址 予以閂鎖並傳送一請求抹除信號至該控制模組2 0之該控制 狀態暫存單元中。16971.ptd Page 9 589536 V. Description of the invention (7) When any buffer is read, the data is read from the memory 2 and placed in the buffer unit 24 with the lowest priority (priority). The priority of the buffer is based on the value obtained by comparing the previous priority with the current priority in combination with a look-up table, and the look-up task is performed by a look-up table circuit 202. And each buffer has a specific number of bytes as the boundary address, and the address and data of the buffer are updated synchronously. When writing data, first, the central processing unit 12 is caused to send a write data address request signal to the address latch comparison module 22 according to the data the user wants to perform writing. Secondly, the address latch comparison module 22 is caused to latch the currently written data address and transmit a write request signal to the control state temporary storage unit of the control module 20. After that, the control module 20 is caused to send a write request signal to the memory control signal generating module 26, and the request signal and the address are written to the memory control signal generating module 26 through the memory control signal generating module 26. The memory 2 is driven into a data writing mode. Finally, the central processing unit 12 transmits the data to be written to the memory 2 through the control module 20. When erasing data, first, the central processing unit 12 is caused to send an erasure data address request signal to the address latch comparison module 22 according to the data to be erased by the user. Secondly, the address latch comparison module 22 is configured to latch the current erasure data address and send a request erasure signal to the control state temporary storage unit of the control module 20.
16971.ptd 第10頁 589536 五、發明說明(8) 之後’令該控制模組2 0發出一請求抹除信號至該記憶 體控制信號生成模組2 6,俾透過該記憶體控制信號生成模 組2 6發出請求抹除信號及抹除位址以驅動該記憶體2執行 資料抹除。 隶後’令該中央處理單元1 2通過狀態為記憶體2資料 抹除成功與否之判斷。 於識別碼讀取時,首先,令該中央處理單元1 2依據使 用者所欲執行讀取之識別碼發出一識別碼讀取請求信號至 该位址閂鎖比較模組2 2。 其次’令該位址閂鎖比較模組2 2將本次讀取識別碼位 ,乂門鎖並傳送一請求讀取識別碼信號至該控制模組2 0 之5亥控制狀態暫存單元中。 之後’令該控制模組2 0發出一請求讀取識別碼信號至 =$,體控制信號生成模組26,俾透過該記憶體控制信號 成模組26發出請求讀取識別碼信號及讀取識別碼位址以 驅動,記憶體2執行讀取識別碼。 取後’令該記憶體2透過該匯流排控制模組2 8傳送識 另’碼^料至該中央處理單元1 2俾供其讀取。 清參閱第3 ( A)圖,其係顯示本發明之記憶體操作方 〆之於執行記憶體寫入資料之流程。 =步驟S3 01中,令該中央處理單元12依據使用者所欲 行=取之資料發出一讀取資料位址請求信號至該位址閃 、貞比較模組22,接著進行步驟S3 02。 於步驟S3 0 2中,令該位址閃鎖比較模組2 2判斷該讀取16971.ptd Page 10 589536 5. After the description of the invention (8), 'the control module 20 sends a request erasing signal to the memory control signal generating module 26, and then generates a module through the memory control signal The group 2 6 sends an erase request signal and an erase address to drive the memory 2 to perform data erase. Subsequent 'makes the central processing unit 12 pass the judgment of whether the data is erased in memory 2 or not. When the identification code is read, first, the central processing unit 12 is caused to send an identification code reading request signal to the address latch comparison module 22 according to the identification code that the user wants to perform reading. Secondly, 'the address latch comparison module 22 will read the identification code bit this time, knock the door lock and send a signal requesting to read the identification code to the control module 5 0 of the control state temporary storage unit. . After that, 'the control module 20 sends a request to read the identification code signal to = $, the body control signal generation module 26, and sends the request to read the identification code signal and reads through the memory control signal generation module 26. The identification code address is driven, and the memory 2 executes reading the identification code. After fetching ', the memory 2 transmits another code to the central processing unit 12 俾 through the bus control module 2 8 for reading. Refer to FIG. 3 (A), which shows the memory operating method of the present invention, which is to execute the process of writing data into the memory. In step S3 01, the central processing unit 12 is instructed to send a read data address request signal to the address flash and comparison module 22 according to the data that the user desires. Then, step S302 is performed. In step S3 0 2, the address flash lock comparison module 2 2 determines the read.
第11頁 589536 五、發明說明(9) 資料位址請求信號所欲讀取之資料是否已儲存於該緩衝單 元2 4内,若否則進行步驟S 3 0 3 ;若否則進至步驟S 3 0 6。 於步驟S 3 0 3中,令該控制模組2 0發出一讀取信號至該 記憶體控制信號生成模組2 6藉以生成一資料讀取信號至該 記憶體2,接著進行步驟S 3 0 4。 於步驟S 3 0 4中,該記憶體2即會進入一資料讀取模式 藉以將該所欲讀取之資料傳送至該緩衝單元2 4内,接著進 行步驟S 3 0 5。 於步驟S 3 0 5中,透過該匯流排控制模組2 8傳送資料至 該中央處理單元1 2。 於步驟S 3 0 6中,令該控制模組2 0自該緩衝單元2 4内讀 取資料後復藉由該匯流排控制模組2 8傳送資料至該中央處 理單元1 2。 請參閱第3 ( B)圖,其係顯示本發明之記憶體操作方 法之於執行記憶體讀取資料之流程。 於步驟S 3 1 1中,令該中央處理單元1 2依據使用者所欲 執行寫入之資料發出一寫入資料位址請求信號至該位址閂 鎖比較模組2 2,接著進行步驟S 3 1 2 。 於步驟S 3 1 2中,令該位址閂鎖比較模組2 2將本次寫入 資料位址予以閂鎖並傳送一請求寫入信號至該控制模組2 0 之該控制狀態暫存單元中,接著進行步驟S3 1 3。 於步驟S3 1 3中,令該控制模組2 0發出一請求寫入信號 至該記憶體控制信號生成模組2 6,俾透過該記憶體控制信 號生成模組2 6發出請求寫入信號及寫入位址以驅動該記憶Page 11 589536 V. Description of the invention (9) Whether the data to be read by the data address request signal has been stored in the buffer unit 24, if not, proceed to step S 3 0 3; otherwise, proceed to step S 3 0 6. In step S 303, the control module 20 is caused to send a read signal to the memory control signal generating module 26 to generate a data read signal to the memory 2, and then proceed to step S 3 0 4. In step S304, the memory 2 will enter a data reading mode to transfer the data to be read into the buffer unit 24, and then proceed to step S305. In step S305, data is transmitted to the central processing unit 12 through the bus control module 28. In step S306, the control module 20 is caused to read data from the buffer unit 24 and then send the data to the central processing unit 12 through the bus control module 28. Please refer to FIG. 3 (B), which shows the flow of executing the memory reading method by the memory operation method of the present invention. In step S 3 11, the central processing unit 12 is caused to send a write data address request signal to the address latch comparison module 22 according to the data to be written by the user, and then step S is performed. 3 1 2. In step S 3 1 2, the address latch comparison module 22 is configured to latch the currently written data address and send a write request signal to the control state of the control module 20 temporarily. In the unit, step S3 1 3 is performed next. In step S3 1 3, the control module 20 is caused to send a request writing signal to the memory control signal generating module 26, and the request writing signal is sent through the memory control signal generating module 26. Write address to drive the memory
16971.ptd 第12頁 五、發明說明(10)16971.ptd Page 12 V. Description of Invention (10)
體2進入一寫入資料模式,接Μ、 於步驟S3 14中,該由& 者進行步驟S31 4。 T央處理留一 20將欲寫人之資料傳送至該⑼^ 12即透過該控制模組 請參Μ第3( C)圖,其係^體2。 法之於執行記憶體抹除眘树、一不本發明之記憶體操作士 於步驟S321中,令該中参卢祆。 執行抹除之資料發出—抹除資2理單元12依據使用者所欲 鎖比較模組2 2,接著進行半聰λ位址請求信號至該位址閂 於步驟S322中,令該位址^ 資料位址予以閂鎖並傳送_於颂比較模組22將本次抹除 之該控制狀態暫存單元中,二1抹除信號至該控制模組20 於步驟S323中,令該控行步驟S323。 至該記憶體控制信號生成模組 號生成模組2 6發出喑東枯心产% n透過忒δ己隐體控制信 體2執行資料抹除,接著進驟及位址以驅動該記憶The body 2 enters a write data mode. Then, in step S34, the & person performs step S31 4. The T central processing reserves a 20 to transmit the information of the person who wants to write to the ⑼ ^ 12, that is, through the control module, please refer to Figure 3 (C), which is ^ body 2. The method is to execute the memory erasure tree, a memory operator who is not the present invention. In step S321, the user is instructed to participate. Issue of data for erasing—Erasing management unit 12 locks comparison module 2 2 according to the user's desire, and then sends a Satoshi λ address request signal to the address and latches it in step S322, so that the address ^ The data address is latched and transmitted_ In the song comparison module 22, the control status temporary erasing unit is erased, the 2 1 erasure signal is sent to the control module 20 in step S323, and the control step is executed. S323. To the memory control signal generation module, the number generation module 2 6 sends out the heart rate, n through the δ δ hidden body control signal body 2 to perform data erasure, and then steps and addresses to drive the memory.
It 1 ^ ^ 清茶閱第3 ( D)圖,其係顯 法之於執行記憶體讀取識別碼之流月…體私作方 於步驟S331中,令今中本卢 0口 執行讀取之螂w 中央處理早兀1 2依據使用者所欲 鎖比較模、组^2,】〗^ Γ ^別碼讀取請求信號至該位址閃 接者進仃步驟S 3 3 2。It 1 ^ ^ Qingcha read Figure 3 (D), which is the method of displaying the identification code of the memory to read the flow ... The private owner in step S331, so that the Nakamoto Lu port 0 to perform reading The central processing of the mantis w 12 is locked according to the user's desire to lock the comparison mode and group ^ 2,] ^ ^ Γ ^ read the request signal to the address flasher and proceed to step S 3 3 2.
於步驟S3]9tb X 識別碼位址予以= j鎖比較模組22將本次讀取 、头並傳运一晴求讀取識別碼信號至該控At step S3] 9tb X identification code address is given = j lock comparison module 22 reads, transmits and clears the identification code signal to the control
589536 五、發明說明(11) 制模組2 0之該控制 於步驟S333中 碼信號至該記憶體 控制信號生成模組 碼位址以驅動該記 S334 ° 於步驟S334中 2 8傳送識別碼資料 以上所述僅為 佳實施例,非用以 發明之記憶體操作 定義於下述之申請 體或方法,若與下 或為等效之變更, 狀態暫存單元中,接著進行步驟s333。 ’令該控制模組20發出一請求讀取識別 控制化號生成模組2 6,俾透過該記憶體 ^發出請求讀取識別碼信號及讀取識別 憶體2執行讀取識別碼,接著進行步驟 至ίϊΐϊ體2透過該匯流排控制模組 本^明^处理單元12俾供其讀取。 本發明之記,降轉 限定本c方法以及裝置之較 方法以及裳晋ΐ貝技術内容之範圍。本 專利範圍ί Γ貫質技術内容係廣義地 述之申請專利:2他士所完成之技術實 均將被视為14圍所定義者完全相同, …叫盖於此專利範圍之中。589536 V. Description of the invention (11) The module 2 0 controls the code signal in step S333 to the memory control signal generating module code address to drive the record S334 ° transmits the identification code data in step S334 28 The above description is only a good example. The memory operations that are not used for invention are defined in the following application body or method. If the changes are equivalent to the following or equivalent, the state is temporarily stored in the unit, and then step s333 is performed. 'Let the control module 20 issue a request to read the identification and control number generation module 26, 俾 issue a request to read the identification code signal through the memory ^ and read the identification memory 2 to execute the reading identification code, and then proceed Steps to the body 2 are read by the bus control module book processing unit 12. In the present invention, downshifting limits the scope of this c method and device comparison method as well as the technical content of the shang jin yi bei. The scope of this patent is that the technical content of the patent is a broadly described patent application: 2 The technologies completed by Taxi will be regarded as exactly the same as those defined in 14 circles, and are covered by this patent scope.
16971.ptd 第14頁 589536 圖式簡單說明 【簡單圖式說明】 第1圖係一應用架構示意圖,用以顯示本發明之記憶 體操作裝置應用於一個人電腦上之基本架構; 第2圖係一基本架構示意圖,用以顯示該記憶體操作 裝置之基本架構;以及 第3 ( A)至3 ( D)圖為一流程圖,用以顯示本發明之 記憶體操作方法於執行記憶體操作之流程。 【圖式標號】 1 記憶體操作裝置 2 記憶體 10 個人電腦 12 中央處理單元 2 0 控制模組 22 位址閂鎖比較模組 2 4 緩衝單元 26 記憶體控制信號生成模組 28 匯流排控制模組16971.ptd Page 14 589536 Schematic description [simple schematic description] Figure 1 is a schematic diagram of an application architecture, used to show the basic structure of the memory operating device of the present invention applied to a personal computer; Figure 2 is a The schematic diagram of the basic structure is used to show the basic structure of the memory operation device; and Figures 3 (A) to 3 (D) are a flowchart showing the flow of the memory operation method of the present invention in performing the memory operation . [Symbol number] 1 Memory operating device 2 Memory 10 Personal computer 12 Central processing unit 2 0 Control module 22 Address latch comparison module 2 4 Buffer unit 26 Memory control signal generation module 28 Bus control mode group
16971.pui 第15頁16971.pui Page 15
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CN104239229A (en) * | 2013-06-20 | 2014-12-24 | 慧荣科技股份有限公司 | Data storage device and data reading method for flash memory |
TWI584117B (en) * | 2013-06-20 | 2017-05-21 | 慧榮科技股份有限公司 | Data storage device and data fetching method for flash memory |
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CN104239229A (en) * | 2013-06-20 | 2014-12-24 | 慧荣科技股份有限公司 | Data storage device and data reading method for flash memory |
US9563551B2 (en) | 2013-06-20 | 2017-02-07 | Silicon Motion, Inc. | Data storage device and data fetching method for flash memory |
TWI584117B (en) * | 2013-06-20 | 2017-05-21 | 慧榮科技股份有限公司 | Data storage device and data fetching method for flash memory |
CN104239229B (en) * | 2013-06-20 | 2018-06-08 | 慧荣科技股份有限公司 | Data storage device and data reading method for flash memory |
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