587373 玖、發明說明： 【發明所屬之技術領域】 本發明係一種具有新的自我内建測試電路的鎖相電路 ，本發明係一種可藉特殊用途KX簡稱ASIC)設計所完成 的自我内建滿試之鎖相電路最主要疋您扣在展生數祖系瓢 電路的計時(clock)或者是應澇於通說領域，該鎖相電路 除了具有測試的電路特牲之外，同時還可以由電路本身自 己產生出測試樣本來進符電路測試的功能，而不用假由外 部輪入測試樣本，可大幅縮短測試所需的時間和測試成本 ，亦可省下很多必備的量測儀器，僅僅只需要觀測鎖相電 路的輸出即可得到測試的結果和測試值。 【先前技術】 敬請參閱第一圖所示：係一般鎖相電路架構圖。一般 鎖相電路的架構可概分為六部分：頻率相位檢測器（Phase Frequency Detector ,簡稱為 PFD)、電荷泵浦(Charge P ump，簡稱為CP)、電壓控制振盪器(Voltage-Controlled Oscillator，簡稱為 VCO)、低通濾波器(Low-Pass Filte r，簡稱為 LPF)、除二(1/2)和除N(Divider-by-N)。 外部參考輸入信號(Reference Input)和Divide-by-N信號經由PFD電路作相位差比較後，並將其兩者關係轉 換成往上遞增(UP)和往下遞減(DN)兩個信號分別送給CP 電路，CP電路最主要是用來將PFD電路的數位信號轉換成 VC0電路可接受的類比信號之動作，CP電路在受到PFD電 路的UP和DN的控制信號而對LPF電路的電阻電容作充放 電之行為，VC0電路利用CP電路對LPF電路所產生之類比 信號而振盪出相對的高頻輪出頻率，然後再將此高頻頻率 送到除2電路作5 0 %的工作週期(duty cycle)波形整型 587373 動作，最後運用Divider-by~N將高頻信號降頻到接近參 考輸入信號(Reference Input)的低頻信號來給pFD電路 作相位差的比較，如此一直循環運作直到兩者的相位差極 為接近相等時’此時鎖相電路即完成鎖頻之動作。 在上述一般鎖相電路中，因為其鎖相電路是藉由遞迴 觀念來完成鎖頻之動作，在經過無數次的相位差比較、調 整VCO電路所振盪出來的高頻頻率，一直到外部參考輸入 信號(Reference Input)和Divider-by-N的信號是相同時 ，鎖相電路才完成其動作，由此可知鎖相電路是一種同時 兼具有數位電路以及類比電路的混合信號電路，所以就以 測試的觀點而言，其設計一個具有可測試特性的鎖相電路 是非常的困難且難以設計，因為鎖相電路兼具有數位和類 比電路的特性，所以在測試電路的設計上便需要考量到數 位和類比電路特點，同時當加入了測試電路之後，其測試 電路不能影響到原本鎖相電路的電路特性，同時所額外附 加的測試電路的硬體成本要達到最小，而且，測試電路本 身也要是可被測試，或者是自己可以測試自己的電路，當 確保測試電路無誤後，才能夠有足夠的證據來證明測試電 路所測得到的數據或者是資料是正確且可靠無誤的，因此 在想要把電路設計的具有DFT電路特性的電路，必需要 非常了解其電路本身的電路工作原理與特性，而且在不影 響電路特性的最大前提要求下，所付出的額外成本和能夠 測到有用的資料，如此才能夠算是一個好的電路。 鎖相電路是一種遞迴(recursive)動作的電路，它是 藉由不斷的作鎖相電路的外部參考輸入信號（Reference587373 发明 Description of the invention: [Technical field to which the invention belongs] The present invention is a phase-locked circuit with a new self-built test circuit. The present invention is a self-built circuit that can be completed by a special-purpose KX (ASIC for short) design. The most important part of the phase-locked circuit is that you buckle the clock of the ancestral ancestral scoop circuit or should be in the field of communication. In addition to the circuit characteristics of the test, the phase-locked circuit can also be The circuit itself generates test samples to enter the circuit test function, without the need to artificially roll in the test samples from the outside, which can greatly reduce the time and cost required for testing, and can also save many necessary measuring instruments. You need to observe the output of the phase-locked circuit to get the test results and test values. [Previous technology] Please refer to the first figure: the general phase-locked circuit architecture diagram. The architecture of a general phase-locked circuit can be roughly divided into six parts: Phase Frequency Detector (PFD), Charge Pump (CP), and Voltage-Controlled Oscillator. VCO for short, Low-Pass Filter (LPF for short), Divide by Two (1/2) and Divider-by-N. The external reference input signal (Reference Input) and Divide-by-N signal are compared with the phase difference through the PFD circuit, and the relationship between the two is converted into two signals: increasing (UP) and decreasing (DN). For the CP circuit, the CP circuit is mainly used to convert the digital signal of the PFD circuit into an analog signal acceptable to the VC0 circuit. The CP circuit is subjected to the UP and DN control signals of the PFD circuit to the resistance and capacitance of the LPF circuit. In the charging and discharging behavior, the VC0 circuit uses the CP circuit to oscillate the relative high-frequency wheel output frequency of the analog signal generated by the LPF circuit, and then sends this high-frequency frequency to the division 2 circuit for a 50% duty cycle (duty cycle) waveform shaping 587373 action, and finally uses Divider-by ~ N to down-frequency the high-frequency signal to a low-frequency signal close to the reference input signal (Reference Input) to compare the phase difference of the pFD circuit. When the phase difference is extremely close to equal ', the phase-locked circuit will then complete the frequency-locking operation. In the general phase-locked circuit mentioned above, because its phase-locked circuit uses the concept of recursion to complete the frequency-locking operation, after countless phase comparisons, the high-frequency frequency oscillated by the VCO circuit is adjusted to the external reference. When the input signal (Reference Input) and the signal of Divider-by-N are the same, the phase-locked circuit completes its action. It can be seen that the phase-locked circuit is a mixed-signal circuit with both digital and analog circuits. From a testing point of view, it is very difficult and difficult to design a phase-locked circuit with testable characteristics. Because the phase-locked circuit has the characteristics of both digital and analog circuits, it is necessary to consider the design of the test circuit. To the characteristics of digital and analog circuits, and when the test circuit is added, the test circuit cannot affect the circuit characteristics of the original phase-locked circuit, and the hardware cost of the additional test circuit must be minimized, and the test circuit itself is also If it can be tested, or if you can test your own circuit, only after ensuring that the test circuit is correct There is enough evidence to prove that the data or information measured by the test circuit is correct and reliable. Therefore, if you want to design a circuit with DFT circuit characteristics, you must know the circuit working principle and Characteristics, and without affecting the maximum premise requirements of the circuit characteristics, the additional cost and useful information can be measured, so that it can be considered a good circuit. A phase-locked circuit is a recursive circuit. It is used as an external reference input signal (Reference)
Input)和Divider-by-N信號兩者的相位差動作，利用此 相位差來調整VCO電路的振盪頻率輪出，如此不斷循環計 算運作，一直到鎖相電路達到鎖頻的動作為止，因此，在 測試上，不能夠把這個循環(l〇〇P)打斷，同時也不能夠將 測試電路加在這個循環（l〇〇p)的運行路徑上，因為，如果 將此循環(loop)打斷，則勢必無法完成鎖相電路的工作原 理特性，如此會無法保證鎖相電路的正確性，若如果把測 試電路加到鎖相電路的循環(1〇〇Ρ)的運行路徑上，則可能 會影響到鎖相電路原本的電路運作特性，使得鎖相電路的 電路特性會因此而產生偏移，如此便會違反不能影響原本 電路運作特性的要求前提，因此，所要附加的測試電路儘 量是以並聯的方式附加在鎖相電路當中，或者把測試電路 加到鎖相電路的循環(loop)運行路徑上，但所造成的影響 是最小的，甚至是沒有影響的。對數位電路而言，首重的 是電路功能正確和時間（timing)正確以及硬體成本是最小 的三個主要要求，而類比電路則是因為類比電路是線性(1 inear)的電路特性，因此除了電路功能正確之外，也非常 重視寄生效應與噪音(n〇ise)干擾的問題，所以，在測試 電路的設計考量上，類比電路的DFT電路遠比數位電路難 設計很多，對類比電路而言，增加一個測試電路在類比電 路中，若是額外的附加測試電路沒有考慮周詳，或是會引 起噪音、寄生效應等問題，則可能會使原本能夠正常運作 的類比電路’在增加了額外附加的測試電路之後而造成無 法正常工作或者是工作不正常的窘態，因此，對鎖相電路 而言，額外附加的測試電路儘量是數位電路，而且要結合 587373 到f相魏，其齡魏路也儘妓在触電路部份 或疋不影響鎖相電路的工作特性部份。 目月ϊ】鎖相電路的測試電路設計可區分成兩大類，其一 是早純測觸相電路_部元件是否有錯(fault)，還是 揍（fault free)，另外一種則是測試鎖相電路的參數， 如鎖相電路的麵細、、電路的增益值料，第一種 鎖相電路_財法，目義減要非常長_試時間才 能夠將全部的峨樣本全部就，雜可哺完整的測試 到鎖相電_部的全部元件，但是實祕不大。至於第二 種方法的>職電路槪較多種，但是所麟真正測試到鎖 相電路的參數的精確值卻不是很精準，而且所需要額外付 出的硬體成本都很大，因此，此種鎖相電路的測試電路所 付出的成本太高，所得到的經濟效益並沒有預期中來得高 ’本發明所設計具有自我内建測試功能的鎖相電路是利用 原本鎖相電路中的既有的電路，然後稍加修改部份電路， 再增加一個產生測樣本的電路，所以對於所要付出的硬體 成本，可以說是最小的，而且也沒有改變到原本鎖相電路 的動作原理，又可以準確測試到鎖相電路的參數。 【發明内容】 本發明所設計具有自我内建測試功能的鎖相電路是利 用原本鎖相電路中的既有的電路，然後稍加修改部份電路 ’再增加一個產生測試樣本的電路即可實現，因此所需要 付出的额外硬體成本可以說是最小的，而且可以測試到的 值也非常的準確。對測試者而言，鎖相電路最重要的參數 即為鎖住的頻率是否正確，其鎖相電路的擾動（jitter)值 是否在合理的範圍之内，鎖相電路的鎖頻範圍是否正嫁等 587373 等，由於VCO電路是鎖相電路的核心電路，同時也是鎖相 電路最難设計’同時也是最靈敏(sensitive)電路，因此 ，本發明將針對鎖相電路的VC0電路作為測試的目標，當 核心電路能夠達到DFT電路的特性之後，鎖相電路的其餘 的電路也就比較能夠實現DFT電路的特點，一個vc〇電路 的主要參數為VC0電路的輸入可控制電壓範圍，冗〇電路 的輸出振盈頻率範圍，藉由這兩項參數即可求得VC0電路 的最大、最小可控制輪入電壓和輪出振盪頻率。 【實施方式】 為使專精熟悉此項技藝之人仕業者易於深入瞭解本發 明的設計内容以及所能達成的功能效益，茲列舉一具體實 施例，並配合圖式詳細介紹說明如下： 為了設計一個可測試VC0電路特性的鎖相電路，本發 明將從三個方面來著手，使鎖相電路具有可測試功能的電 路(Design for Test，簡稱為DFT電路）特性的鎖相電路 ’本發明利用電荷泵浦(Charge Pump)電路對LPF電路作 充電(charge)或者是放電(discharge)動作而產生出類比 信號電壓，進而控制VC0電路輪入電壓，使VC0電路振盡 出相對應的輪出頻率的特點，利用此鎖相電路的電路特性 而作局部電路修改，使鎖相電路具有DFT電路特性： (1)修改LPF電路：LPF電路中的電容一般約在幾百 pf左右，對ASIC的佈局(layout)而言，要實際畫出一顆 這麼大的電容是不可能的，因此，一般均是畫出一個單位 (unit)的單位電容，然後採用並聯的方式，把電容並聯到 電路所求的規袼即可達到需求，如第二圖和第三圖所示， 即為以電路所表示之示意圖以及實際電容結構的示意圖〇 587373 本發明在LPF電路的電容分別加入開關，如第四圖所示， 如此則可利用開關来決定LPF電路中電容的充電(charge) 或者是放電(discharge)數量。 (2) 修改PFD電路：因為本發明想要在鎖相電路進入 測試模式(test mode)時，控制電荷泵浦(charge Pump)電 路對LPF電路作充電(charge)或者是放電(discharge)動 作時的電容數量，所以本發明在LPF電路的電容中加入了 開關來控制充電(charge)或者是放電(discharge)動作時 的電容數量，而若想要控制鎖相電路中電荷泵浦（Charge Pump)電路是要對LPF電路作充電(charge)或者是放電(di scharge)動作，則必需局部修改pfd電路，使得可以在鎖 相電路進入測試模式(test mode)時，可以自由控制電荷 泵浦(Charge Pump)電路是要作充電(Charge)或者是放電 (discharge)動作，如第五圖所示為局部修改的pjrj)電路 ，本發明僅在PFD電路的輸出部份加入了一個2X1的多工 器’以便來控制PFD電路是在正常模式（norfflai fflode)還 是在測試模式(test mode) 〇 (3) 增加測試電路：本發明在鎖相電路中加入測試電 路，其功用最主要是要控制使鎖相電路進入測試模式(tes t mode)或者是正常模式(η〇π^ι m〇de)，假若是在正常(n onnal mode)的狀況下，則鎖相電路是正常工作，若是進 入測試模式（test mode)，則要自己產生測試樣本來分別 控制PFD電路以及LPF電路，然後便可從鎖相電路的輪出 端觀測到鎖相電路的測試值，此測試電路可用Verilog c ode來撰寫，利用電路合成的方法將Veril〇g c〇de轉成 數位電路即可’如第六圖所示為鎖相電路加入了測試電路 後的方塊圖。 在解析其測試電路的工作理論之前，首先來檢視前面 所提及的要在鎖相電路中加入測試電路的幾項要求，先以 本發明所作的鎖相電路局部修改的電路來看，當在LPF電 路中的電容加入開關，因為鎖相電路的循環(1〇〇p)運作路 徑是在電荷泵浦(Charge Pump)電路輸出到VCO電路的輸 入，因此，本發明所修改及增加的開關並不在鎖相電路的 循環(loop)運作路徑上，因此，不會有影響到鎖相電路循 環(loop)運作的電路特點，再者，開關的導通電阻可以視 為LPF電路中的電阻值，而且，因為開關電阻是並聯模式 連接’所以在眾多開關電阻並聯後，其最後串接到LPF電 路的電阻(R)值時，已經是非常的小了，所以其影響性可 謂是非常的小，而且，在正常模式(normal mode)時，因 為開關是永遠導通，所以沒有因為開關的導通或者是載止 而產生問題，這些開關只有在測試模式(test mode)時才 會動作，因此，本發明針對LPF電路所作的局部電路修改 並沒有違反前面所提及的問題。至於在pj?l)電路修改部份 ，因為PFD電路本身為數位電路，在數位電路中要求的是 電路功能正破以及時間(timing)正破，所以，當本發明在 PFD電路中加入一個2X1的多工器時，雖然此舉是在鎖相 電路的循環（loop)運作路徑上加入了額外的元件，可是本 發明可以把這個2X1的多工器視為PFD電路的其中一個小 電路來着待，如此，只要PFD電路本身能夠符合到鎖相電 路的要求，如此即沒有所謂在鎖相電路的循環(lo〇p)運作 路徑上加入測試元件的問題，而且，因為ΡΙΦ電路為數位 電路，因此，只要能夠確保PFD電路的時間(timing)是正 587373 確無誤的，就不會有因為加入一個2X1的多工器而影響鎖 相電路的靈敏(sensitive)問題，因為把它着成是PFD電 路的内部子電路。最後本發明所加入的測試電路，因為它 疋並行於鎖相電路而沒有串接在鎖相電路的循環(l^P)運 作路徑上，所以沒有干擾鎖相電路的間題，而且，因為在 正常模式（normal mode)時，測試電路是不動作的，所以 不會造成鎖相電路在正常模式(normal m〇(je)時的噪音(no ise)干擾源，因此，在解析了上述三個電路之後，皆沒有 違反先前所提及的問題與要求，因此，在鎖相電路中加入 此測試電路是沒有問題的，接下來就要探討在加入此測試 電路後能夠測到怎樣子的資料舆測試的數學理論是否可以 佐證本發明的測試效果是否可行。 如第七圖所示為本發明建構一個測試的時序圖，接下 來將藉由此一測試時序圖來解說測試的數學理論與測試步 驊： (1) 當鎖相電路進入測試模式(test mode)時，首先 ,將控制PFD電路，使往上遞增(UP)信號為高(high),往 下遞減(DN)信號為低(LOW) ’此時’電荷果浦(charge Pum P)電路對LPF電路作充電(charge)動作，而且，此時LPF 電路上的開關全部為導通狀態，直到LPF電路中的電容充 電(charge)到VDD的狀態，此時電容上的電荷分別為：Input) and Divider-by-N signals. This phase difference is used to adjust the oscillation frequency of the VCO circuit. It is continuously calculated and operated until the phase-locked circuit reaches the frequency-locked operation. Therefore, In the test, it is not possible to interrupt the loop (100P), and it is also impossible to add the test circuit to the running path of the loop (100p), because if the loop is interrupted Failure, it is bound to fail to complete the working principle characteristics of the phase-locked circuit, so the correctness of the phase-locked circuit cannot be guaranteed. If the test circuit is added to the loop (100 〇) running path of the phase-locked circuit, it may be It will affect the original circuit operating characteristics of the phase-locked circuit, so that the circuit characteristics of the phase-locked circuit will be offset due to this. This will violate the premise that the operating characteristics of the original circuit cannot be affected. Therefore, the additional test circuit should be based on The parallel method is added to the phase-locked circuit, or the test circuit is added to the loop running path of the phase-locked circuit, but the impact is minimal, or even influential. For digital circuits, the first priority is the three main requirements for correct circuit function and correct timing and minimum hardware cost, while analog circuits are because the analog circuit is a linear (1 inear) circuit characteristic, so In addition to the correct function of the circuit, it also attaches great importance to the problem of parasitic effects and noise interference. Therefore, in the design considerations of the test circuit, the DFT circuit of the analog circuit is much more difficult to design than the digital circuit. In other words, adding a test circuit to the analog circuit, if the additional additional test circuit is not considered carefully, or it will cause noise, parasitic effects and other problems, it may make the analog circuit that could normally work normally add an additional additional After the test circuit, it causes the embarrassment that it cannot work normally or works abnormally. Therefore, for the phase-locked circuit, the additional test circuit is a digital circuit as much as possible, and it must be combined with 587373 to f phase Wei. The prostitutes are in the circuit contact part or the part that does not affect the working characteristics of the phase-locked circuit. Ϊ 月 ϊ】 The design of the test circuit of the phase-locked circuit can be divided into two categories. One is the early pure test of the phase-contact circuit _ whether the component is faulty or fault free. The other is to test the phase-locked circuit. The parameters of the circuit, such as the phase-locked circuit, the gain of the circuit, and the gain value of the circuit, the first phase-locked circuit _ financial method, the purpose of the reduction is very long _ test time to be able to get all the samples of E I have tested all the components of the phase-locked circuit, but they are not very secretive. As for the second method, there are many types of vocational circuits, but the exact values of the parameters of the phase-locked circuit that are actually tested are not very accurate, and the extra hardware costs required are very large. Therefore, this kind of The cost of the test circuit of the phase-locked circuit is too high, and the economic benefits obtained are not expected to be high. The phase-locked circuit designed by the present invention with a self-built test function uses the existing phase-locked circuit. Circuit, and then slightly modify some circuits, and then add a circuit to generate test samples, so the hardware cost to be paid can be said to be minimal, and it has not changed to the original principle of the phase-locked circuit, and it can be accurate Tested to the parameters of the phase-locked circuit. [Summary of the invention] The phase-locked circuit designed by the present invention with a self-built test function is to use the existing circuit in the original phase-locked circuit, and then modify some of the circuits slightly, and then add a circuit that generates test samples. , So the additional hardware cost required can be said to be minimal, and the values that can be tested are also very accurate. For the tester, the most important parameters of the phase-locked circuit are whether the locked frequency is correct, whether the jitter value of the phase-locked circuit is within a reasonable range, and whether the frequency-locked range of the phase-locked circuit is correctly married. 587373 etc., because the VCO circuit is the core circuit of the phase-locked circuit, it is also the most difficult circuit to design, and it is also the most sensitive circuit. Therefore, the present invention takes the VC0 circuit of the phase-locked circuit as the test target. After the core circuit can reach the characteristics of the DFT circuit, the remaining circuits of the phase-locked circuit will be able to realize the characteristics of the DFT circuit. The main parameter of a vc0 circuit is the input controllable voltage range of the VC0 circuit. Output vibration frequency range. With these two parameters, the maximum and minimum controllable wheel-in voltage and wheel-out oscillation frequency of the VC0 circuit can be obtained. [Embodiment] In order to make those who are familiar with this technology easily understand the design content of the present invention and the functional benefits that can be achieved, a specific embodiment will be enumerated, and it will be described in detail in conjunction with the drawings as follows: In order to design A phase-locked circuit that can test the characteristics of a VC0 circuit. The present invention will start from three aspects. The phase-locked circuit that allows the phase-locked circuit to have a circuit with a testable function (Design for Test (DFT circuit) for short). The charge pump circuit charges or discharges the LPF circuit to generate an analog signal voltage, and then controls the turn-on voltage of the VC0 circuit so that the VC0 circuit vibrates to the corresponding turn-out frequency. The characteristics of this phase-locked circuit are used to modify the local circuit to make the phase-locked circuit have DFT circuit characteristics: (1) Modify the LPF circuit: The capacitance in the LPF circuit is generally about several hundred pf. The layout of the ASIC In terms of layout, it is impossible to actually draw such a large capacitance. Therefore, it is generally to draw a unit capacitance of a unit. In parallel mode, the capacitors can be connected to the circuit in parallel to meet the requirements. As shown in the second and third figures, it is a schematic diagram of the circuit and a schematic diagram of the actual capacitor structure. The capacitors of the LPF circuit are added to the switches, as shown in the fourth figure, so the switches can be used to determine the amount of charge or discharge of the capacitors in the LPF circuit. (2) Modify the PFD circuit: Because the present invention wants to control the charge pump circuit to charge or discharge the LPF circuit when the phase-locked circuit enters test mode Therefore, in the present invention, a switch is added to the capacitance of the LPF circuit to control the amount of capacitance during the charging or discharging operation, and if it is desired to control the charge pump in the phase-locked circuit If the circuit is to charge or discharge the LPF circuit, the pfd circuit must be partially modified so that when the phase-locked circuit enters test mode, the charge pump can be freely controlled. The pump circuit is used for charging or discharging. As shown in the fifth figure, it is a partially modified pjrj circuit. The invention only adds a 2X1 multiplexer to the output part of the PFD circuit. 'In order to control whether the PFD circuit is in the normal mode (norfflai fflode) or in the test mode (test mode) 〇 (3) Add a test circuit: the present invention adds a test circuit to the phase-locked circuit, its function is the most If you want to control the phase-locked circuit to enter test mode (tes t mode) or normal mode (η〇π ^ ι m〇de), if it is in normal (n onnal mode), the phase-locked circuit is working normally If you enter test mode, you need to generate test samples to control the PFD circuit and the LPF circuit separately, and then you can observe the test value of the phase-locked circuit from the wheel-out end of the phase-locked circuit. This test circuit can use Verilog c ode to write, use the method of circuit synthesis to turn VerilOgcode into a digital circuit. 'The block diagram of the phase-locked circuit after adding the test circuit is shown in the sixth figure. Before analyzing the working theory of the test circuit, let's first review the aforementioned requirements for adding a test circuit to the phase-locked circuit. Let's first look at the partially modified circuit of the phase-locked circuit made by the present invention. The capacitor in the LPF circuit is added to the switch because the loop (100p) operation path of the phase-locked circuit is from the charge pump circuit (Charge Pump) circuit output to the input of the VCO circuit. Therefore, the switch modified and added by the present invention and It is not on the loop operation path of the phase-locked circuit, so there will be no circuit characteristics that affect the loop operation of the phase-locked circuit. Furthermore, the on-resistance of the switch can be regarded as the resistance value in the LPF circuit, and Because the switch resistors are connected in parallel mode, so after a large number of switch resistors are connected in parallel, the resistance (R) of the LPF circuit in series is already very small, so its influence is very small, and In normal mode, because the switch is always on, there is no problem caused by the conduction or stop of the switch. These switches are only in the test mode (te st mode), the local circuit modification of the present invention for the LPF circuit does not violate the aforementioned problems. As for the modified part of the pj? L) circuit, because the PFD circuit itself is a digital circuit, what is required in the digital circuit is that the circuit function is broken and the timing is broken. Therefore, when the present invention adds a 2X1 to the PFD circuit, In the case of a multiplexer, although this method adds additional components to the loop operation path of the phase-locked circuit, the present invention can treat this 2X1 multiplexer as one of the small circuits of the PFD circuit. Wait, as long as the PFD circuit itself can meet the requirements of the phase-locked circuit, there is no problem of adding a test element to the loop operation path of the phase-locked circuit, and because the PIΦ circuit is a digital circuit, Therefore, as long as the timing of the PFD circuit is positive 587373 is correct, there will be no sensitive problem that affects the phase-locked circuit by adding a 2X1 multiplexer, because it is made into a PFD circuit. Internal subcircuit. Finally, the test circuit added by the present invention does not interfere with the phase-locked circuit because it is parallel to the phase-locked circuit and is not serially connected to the loop (l ^ P) operation path of the phase-locked circuit. In normal mode, the test circuit is inactive, so it will not cause the noise source of the phase-locked circuit in the normal mode (normal m0 (je)). Therefore, the above three factors are analyzed. After the circuit, none of the problems and requirements mentioned above have been violated. Therefore, it is no problem to add this test circuit to the phase-locked circuit. Next, we will explore the information that can be measured after adding this test circuit. Whether the tested mathematical theory can prove whether the test effect of the present invention is feasible. As shown in the seventh figure, a test timing diagram is constructed for the present invention. Next, the test mathematical diagram and test steps will be explained by using this test timing diagram.骅: (1) When the phase-locked circuit enters test mode, first, the PFD circuit will be controlled so that the UP signal is high and the DN signal is low. ) At this time, the 'charge Pum P' circuit charges the LPF circuit, and at this time, all the switches on the LPF circuit are on until the capacitor in the LPF circuit is charged to VDD. At this time, the charges on the capacitor are:
C totals Qtotal(tl)/Vc(tl) = Qtotal(tl)/V D D CisQKtO/VcOii) =Qi(ti)/VDD (2) 接下來測試電路送出控制信號給pfd電路，使往 上遞增(UP)信號為低(LOW)，而往下遞減(DN)信號為高(ΉΙ GH) ’此時電荷泵浦(Charge Pump)電路使LPF電路要作放 587373 電discharge動作，同時測試電路送出控制信號到LpF電 路中的開關，使LPF電路中只有一個開關是導通狀態，其 餘均為截止狀態，因此，LPF電路中只有一個電容會作玫 電(discharge)動作，一直到電容上的電荷全部釋放為止 ，因此，此時C totals Qtotal (tl) / Vc (tl) = Qtotal (tl) / VDD CisQKtO / VcOii) = Qi (ti) / VDD (2) Next the test circuit sends a control signal to the pfd circuit to make it increase upward (UP) The signal is low (LOW), and the signal decreases downward (DN) is high (ΉΙ GH) 'At this time, the charge pump circuit causes the LPF circuit to discharge 587373 electric discharge, and at the same time the test circuit sends a control signal to The switches in the LpF circuit make only one switch in the LPF circuit be in the on state and the rest are in the off state. Therefore, only one capacitor in the LPF circuit will perform a discharge operation until all the charges on the capacitor are discharged. So at this point
Vc(ti) =VDDsVc(t2) =〇伏。 (3) 再來測試電路送出控制信號給PFD電路，使往上 遞增(UP)信號為低(LOW)，而往下遞減(DN)信號為低(LOW) ’此時電荷泵浦(Charge Pump)電路既不對LPF電路要作 充電（charge)動作，也不作放電動作，同時 ，測試電路送出控制信號到LPF電路中的開關，使lpf電 路中全部的開關都是導通狀態，此時LPF電路中所有的電 容會作電荷重新分配(charge share)動作，一直到電容上 的全部電荷全部一致為止：Vc (ti) = VDDsVc (t2) = 0 volts. (3) The test circuit sends a control signal to the PFD circuit, so that the UP signal is LOW and the DN signal is LOW. 'Charge Pump ) The circuit neither performs a charge operation nor a discharge operation on the LPF circuit, and at the same time, the test circuit sends a control signal to the switches in the LPF circuit, so that all the switches in the lpf circuit are on. All capacitors will perform a charge share action until all the charges on the capacitors are consistent:
Vc(t3)= i Qtotal(tl)-Ql(tl)) /Ctotal = VDD-Vstep Cl=Ql(t3)/Vc(t3) =Ql(t3)/ {： VDD-Vstep) (4) 測試電路送出控制信號給PFD電路，使往上遞增 (ϋΡ)信號為低(LOW)，而往下遞減(DN)信號為高(111诎）， 此時電荷泵浦(Charge Pump)電路使LPF電路要作放電(di scharge)動作，同時，測試電路送出控制信號到卿電路 中的開關，使LPF電路中只有一個開關是導通狀態，其餘 均為截止狀態，因此，LPF電路中只有一個電容會作放電 (discharge)動作，一直到電容上的電荷全部釋放為止， 因此’此時Vc (t3) = i Qtotal (tl) -Ql (tl)) / Ctotal = VDD-Vstep Cl = Ql (t3) / Vc (t3) = Ql (t3) / {: VDD-Vstep) (4) Test circuit Send a control signal to the PFD circuit, so that the upward (UP) signal is low (LOW), and the downward (DN) signal is high (111). At this time, the charge pump circuit (Charge Pump) circuit causes the LPF circuit to For di scharge operation, at the same time, the test circuit sends a control signal to the switch in the circuit, so that only one switch in the LPF circuit is on and the rest are off. Therefore, only one capacitor in the LPF circuit will discharge. (discharge) action until all the charge on the capacitor is discharged, so 'at this time
Vc(t3) = V D D — Vstep~~> Vc(t4) = 〇 伏。 (5)當測試步驟整個全部執行完畢時，即可看到如第 587373 八圖所示的時序圖。利用電容作充電(charge)和放電(以$ charge)時的電荷重新分配(charge share)原理而造成本 發明想要的測試樣本。 由上面的細和鮮顧㈣可知，本發簡測試理 論是正確無誤的，因此，可以知道這個測試的方法是可行 的，而且，就以實現DFT電路特性的鎖相電路所要付出的 硬體成本來着，本發明僅僅只需要數個開關，兩個2χι的 多工器以及一個測試電路即可實現，此種測試方法和所要 付出的硬體成本均是目前所有探討鎖相電路測試的論文當 申最節硬體成本的電路，而且所修改到鎖相電路是最少的 ，更重要的是它對於_電路的s敏度是最 小的，如第八圖所示為模擬結果圖，由此可證明本發明的 理論是正碟的。 本發明的優點： 1·可以自我產生出測試樣本來測試鎖相電路的參數^ 2·所需要付出的硬體成本非常的小。 3·所付出的額外電路為數位電路，對於整個鎖相電路的 影響非常小。 4·沒有改變原來鎖相電路的動作。 【圖式簡單說明】 第一圖：係一般鎖相電路架構圖。 第二圖：係本發明之鎖相電路方塊圖。 第二圖·係本發明之鎖相電路中實際電容結構圖。 第四圖·係本發明在LPF電路的電容再加上開關電路圖。 第五圖··係本發明修改PFD電路圖。 第六圖：係本發明具有DFT電路特性的鎖相電路圖。 587373 第七圖··係本發明測試時序圖。 第八圖：係本發明測試時序模擬結果圖。Vc (t3) = V D D — Vstep ~~ > Vc (t4) = 〇 volts. (5) When all the test steps are completed, you can see the timing chart shown in Figure 587373. The principle of charge sharing during charge and discharge (in terms of $ charge) using capacitors results in the desired test sample of the present invention. It can be known from the above detailed and unfounded test that the test theory of this briefing is correct. Therefore, it can be known that this test method is feasible, and the hardware cost of the phase-locked circuit to achieve the characteristics of the DFT circuit is to be paid. Therefore, the present invention only needs to be implemented by a few switches, two 2 × multiplexers, and a test circuit. This test method and the hardware cost to be paid are all the current papers discussing phase-locked circuit testing. The circuit with the most hardware cost reduction, and the least phase-locked circuit modification, more importantly, it has the smallest s sensitivity to _ circuit, as shown in Figure 8 is the simulation result chart, which can be Prove that the theory of the present invention is correct. Advantages of the present invention: 1. The test sample can be generated by itself to test the parameters of the phase-locked circuit ^ 2. The hardware cost required is very small. 3. The extra circuit paid is a digital circuit, which has very little effect on the entire phase-locked circuit. 4. The operation of the original phase-locked circuit is not changed. [Brief description of the diagram] The first picture: a general phase-locked circuit architecture diagram. Second figure: a block diagram of a phase locked circuit of the present invention. The second figure is a structure diagram of an actual capacitor in the phase locked circuit of the present invention. The fourth figure is a circuit diagram of the capacitor of the present invention plus a switch circuit. The fifth figure is a modified PFD circuit diagram of the present invention. Fig. 6 is a phase-locked circuit diagram with DFT circuit characteristics of the present invention. 587373 The seventh diagram is the test timing diagram of the present invention. FIG. 8 is a simulation result chart of the test sequence of the present invention.