TW586120B - Management system for defective memory - Google Patents

Abstract

A defect management system allows the usage of memory devices with a plurality of defective memory cells to be used for data storage. The system is especially suitable for the storage of streaming media data. The defect management system provides significant manufacturing costs benefits to products that store significant quantities of data in solid state memory, such as MP3 players or MPEG-4 video players. A non-volatile memory stores a map of defective areas within the memory devices that is generated using in built in self test (BIST) procedure. The system employed are low overhead and can be realise in software code or a hardware implementation. The technique can be applied to a very wide range memory technologies include DRAM, Flash, FeRAM and MRAM.

Description

586120

V. Description of the invention (i) [Technical field to which the invention belongs] The field of invention of the present invention relates to a defect management system. The memory device of the memory cell of the defect tube defect is particularly suitable for storing serial media Zhao data. [Previous Technology] For memory management, especially with a management system allows the use of a system containing multiple devices for storing data. The system

Six-Watt Semiconductor § Capsule devices contain millions of individual memory cells. One of the manufacturing procedures is to make the device so that every memory cell can be used and the data can be stored in a reliable way. Due to manufacturing technology limitations, a certain percentage of memory has one or more defective memory cells and cannot reliably store data. This prevents the structural device from being sold as a standard product. In most of this 'partially available' (P a r t i a 1) or " low quality " (downgrade) memory, most of the memory cells operate in a reliable manner. These memory devices are priced much lower than those with good memory crystals. The discount rate is much higher than that of unusable memory cells. So using these components in end applications that require data storage can: Save considerable costs. A number of different technologies have been developed for use in a particular application. A number of different technologies have been used in a considerable number of applications for this memory component. These techniques are also applied to DR A M and flash # ^ devices. Especially because it is widely used in pc. Furthermore, the manufacturing of DRa Μ is a highly competitive industry, and when entering the high-density manufacturing | setting, it will generate 4% larger before the manufacturing technology is optimized _

Page 5 586120 V. Description of the invention (2) Available memory devices DRAM and a certain technique. These additional columns are located in several steps of the test when the rows and rows are stored electronically in an erasable storage location, even when this repair is used. The reason why the redundant resources are limited in this way is that it cannot be mapped to the LAYOUT to limit the repair work, because of the degree. Secondly, in the case of redundant columns or rows of a group of resources " reconstruction ", the advantages of the device ratio of the memory module cannot be provided at the time of sale. Therefore, it is necessary to use many parts that have defects that are used in some types of low traps. They can be used in digital telephone answering and other systems, which must correspond to this or fusion (: when properly technology, It is mainly used. First, its flexibility in the chip. The ratio of these patterns to redundant parts is important to the redundancy. It is used in the low-level cost-of-order retrofit tester for general defect testing. Use the defect area of the internal calculation. Xu Yidang memory first and parallel. Some areas and co-ordination in the timing trap pattern. Such as the impact of the super 0 but one aspect of the memory. For example, the memory is not Compressed memory is located in the chip and is designed to find the defects of each device chip. There are still two reasons for allowing these redundancy. Any part of a generally redundant column is therefore required to have a grain size between the grains that exceeds the resource of the region. Therefore, the grain size is still in use. Characteristics and quality The part of building these assets can be used in toys (referred to as audio equipment, these devices are redundant technology parts. If you want to be redundant in the chip know any missing areas. But the body device must be in the The non-dimensional (TIMING) in the die and the inability to perform dimensional area redundancy may use this part because there are too many over-reconstructable ratios (these component information can still be used directly, with a shortage). Format

Page 6 586120 V. Description of the invention (3) ------ The defects of the digital audio in the body are only a temporary impact on the quality of the sound, although this is the essence of shock On " ·, method identification, but will not have an important impact on the device, function. However, this simple technique cannot be used in high-definition devices, or the conversion of data has been reduced: the avoidable impact of shrinking, the number of defects is much higher, and accepted Fans exist in the answering machine. The application should be further improved to strengthen the impact of single-bit defects, so that there are more and 'there are many available parts of the memory skull assembly

A technique for recovering part of the available DRAM devices in PC is called bit plane classification. An example of this technique is shown in Figure 1. 4 separate memory devices are shown in the label 10. Each memory device can read or write 4 bits simultaneously. Most types of shared memory have a width of at least 8 bits and usually x 6 or 32 bits. Each element's data is stored in a separate block in memory 102. In general, the data for different output bits can be substantially closer, but their logical address space is still separated.

Trap 0 defects This single defect affects a large number of individual memory cells. The designation 1 Q 4 shows a one-bit flat row containing a defective row in the memory. The label 105 is a bit plane row including a defect row. If defects are included, the bit plane technique simply discards an entire plane. Mark 1 06 indicates that the data pins of a defective data plane are not connected to an external system. The data bits provided by the memory are labeled 107. As shown in the figure, in fact, only a good memory cell plane connected to the data memory is used.

586120

V. Description of invention (4). Therefore, additional memory devices must be used to provide the required data access width. The advantage of this technology is that it is simple to operate, but there are some disadvantages. First, even if the data redundancy contains only a few defective memory cells, the entire data redundancy cannot be used. Secondly, other memory devices' must be adapted to achieve the required data width. Therefore occupying more area on PCB and consuming more power. If the write capacity of a byte is required in a memory system, more components are needed, because a single component cannot process the two-byte component containing data characters. Third, when the average number of defects rises to a certain number, some memory-inviting devices cannot be processed using this technique. However, it is actually possible that the actual number of defective memory cells in the shame Zhao device is quite small. A more complex technique is shown in Figure 2. Many of the defective memory devices are indicated by the designation 201. Each device is connected to a special mapping AS I C202. The device contains certain control logic units 203 and a memory array 204. This memory forms external redundancy, which isolates defects in the individual memory devices from data transmitted externally of the memory system on the external bus 20. Defective mappings are stored in the non-erasable memory device 205. As long as the control logic unit detects an action to be accessed, this operation switches the operation to a redundant memory array. According to this method, only a defective memory cell must be j. The memory device can be used moderately. However, it is a disadvantage to store in a few lights. Point: AS IC 202 must be in the data path between Ershu and the rest of the system. For the ^… I series Ding Ma Su system, this technique

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5. Description of the invention (5) The technique can be complicated. The necessary mapping relationship is so that the entire product is completely a copy without affecting the original 'this technology is more [inventive content] [the audio and video and / or video data of the invention to be solved is suitable These packets will be broken for use in the design. However, critical effects can still be included after a package is destroyed. (MP 3) in this format and [solution to the problem of the present invention provide a memory device, the timing of testing the various parts must be accurate and accurate in the future record of the missing challenges. It is not efficient to use the part first. Technical issues] Defect Management Department Store. These ones . This type of this type of ring data file will be lost and contain continuous broadcast information as appropriate, which will not impact performance. Second, the available memory devices are required to track individual components in a defect-mapped memory. It ’s a shame to fall into the mapping relationship, especially when it is necessary to maintain the available memory device. The system can serialize the media format. Data broadcasts generally contain stupid data in many important situations. Cross-consumption leads to simultaneous synchronization. As a result, for example, MPG — MPEG-2 video network media transmission, the quality of the data format will be the same, if all the playback data is 3, the signal of Layer3. Technical means] A defect management system is provided. The system includes a plurality of defect storage memory crystals.

The manufacturing process is related to storage defects in 2005. Test the degree of unit cell in these groups. Keep the test point at a low level. Perform operations to reduce the sound and characteristics of the cells. Therefore, a temporary break is allowed without sound signals in the remaining parts of the encapsulation. Including: at least one cell;

Page 9 586120

Erase memory, this memory has multiple memory blocks to store the locations of the above defects in the memory blocks; wherein the defect management system tests 1 defect memory device and configures the form of the non-erasable memory To indicate the position of the defect area in each memory device, and 'detect new defects during system use, and add the detected new defects to the defect mapping relationship in the non-erasable shame body. The features and advantages of the present invention can be further understood from the following description, and please refer to the accompanying drawings when reading. [Embodiment]

Example 3 shows an embodiment of the present invention. The data series area is displayed with the symbol fO 1. The data series area includes respective data frames 302. In these data frames 302, each data frame has the same length or a different length depending on the format used. Each data frame starts with a grid synchronization of 303. This allows the beginning of each data frame to be determined even when data loss or destruction occurs during data transmission. A data frame header 304 provides information related to the content of the data frame. Finally, it needs to be explained that the data payload of data frame 305 contains the contents of the media ship. Files with this feature are especially suitable storage for this type of defect management system. While doing the initial test job to find the memory

Location of the defect, but during the use of the memory, there may still be a small number of defects. Three. These defects are not expected to be fatal to the performance of the device. Ί i makes til 2 have a temporary effect on the quality of playback. In many cases, the user cannot recognize the defect at all.

586120 V. Description of the invention (7) Defect management technology is particularly suitable for use in certain devices' where the data of these devices are stored in cache memory for subsequent playback in a device. This stored data will not be transferred from the device to another storage vehicle. An example of this product is a portable MP 3 audio or MPEG-4 video player. Download media files from a personal computer to store in the device and play them back. It must be understood that the defect management technology of the present invention is particularly suitable for storage of serial media format data, but can also store data in other formats. If the range covered by the built-in self-test during the test is much better than the result of the mapping box marked as good, then the media can be regarded as a reliable storage medium for any type of data. The actual architecture of a system using one of these defect management systems is shown in Figure 4. The system has a plurality of memory devices 40 1. The number of memory devices used in the figure is not used in a system requiring the present invention, and the number shown in the figure is the smallest of the required number of memories. Any number of memory devices are suitable for the present invention. These memories may contain multiple defective memory cells. Although the number of defects needs to be limited to ensure that the entire article has some memory capacity, there is essentially no limit to the number of defects in a given device. The memory device is controlled by the address and the control signal 4 2. According to the architecture of the memory, the address and control signals can be signals that are not related to the addresses of the various memory devices, or can be shared common control and address signals, except for the selection of each device. Write data to these memories using data bus 4 0 3, or

586120 V. Description of the invention (8) The reader reads data from the memory. In the memory of the ancient times, the two are obscure, and the "number" can be a signal for sub-use. Basically, the memory device is used to shake the μμ in the fruit structure to provide a ratio of β. Any individual memory. Ren Ye, this does not reuse a common data bus architecture for memory width to reduce the number of pins. Memory controller 404. Basically, it can control the memory system's The accessor is connected to a defective anti-memory memory 405. Its capacity is larger than that of the main memory array, and there is a mapping relationship of defective areas in the array. When it is necessary to avoid defective memory cells, the memory Relevant areas in the body surface. During detection, the memory controller also calls for updating the defect mapping relationship. The overall system architecture is shown in Figure 5. The data series of the volume data is marked with 501 to indicate the level format. It will not be affected by the defect management system. The design of the operating product can be regarded as a black box system. 502 determines the address in the subject memory. It is where the input data is written. For example, it is possible to enter the interface 'its write Μρ 3 audio data to Store the entire controller 503 to determine who stores or reads data at the defect management point. This block is also stored according to the memory architecture, the signals that are open, or the use of multiple parallel arrays of memory for wider data access requirements. In the system, the actual controller in the memory controller can be a micro-processing action. The memory control is a non-erasable memory and is used for storing in the memory to access the memory array for the controller to access the defect. When a new defect is reflected, it should be recorded in the media stored in the system. The actual low-level audit in this data, so when the data is written to the controller, the main memory is stored and the data 501 comes from the PC in process Whether the system is in any space with the rest of the product

586120 V. Description of the invention (9) ^ interface, so the entire application can instruct the behavior of the defect management system. 0 The directory write controller 504 is tightly coupled with the write controller. The information stored by the tool is such as the start and end addresses in the memory of a specific media file or file block 2. This allows data to be obtained immediately. The directory information is written in a predetermined area in the main memory.

One The display memory array is located at the center of the figure, which is marked with 50.5. This may include several separate parts of available memory devices. A standard address decoding method is used to select individual devices based on the presented address. Remember that the controller receives data and addresses from the data write and directory write controllers. Data read and directory read controllers can access items in memory. Because the memory device used is partially available, the memory cell in any space in the memory array may be defective and therefore cannot be reliably stored in a data bit. … Maintaining the mapping of defects in the memory array 506 in the defect mapping memory. This is a non-erasable memory, and the capacity of the memory is basically a certain proportion in the main memory array. The antiquated body is stored in the mapping of the position of the defective block in the main memory array. "^

The directory read controller 507 can obtain the start and end information stored in the memory by the directory write controller. Therefore, the address of the start and end data of the data in a specific media file can be determined. '' The data read control 508 reads the data from the memory ship and sends these data to the output channel 509. If necessary, the controller is connected to the rest of the system to provide the required power ^. example

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= 丄 Can be connected to an Mp 3 decoder system to play back data previously stored in a device from a PC interface. The 2 trap cache memory controller is labeled 5 10. The function of the controller, when writing to a file, stores a cached map of the defects associated with a particular media file. This cache defect mapping can itself be stored in the master shame boat, and the cached pattern indicates the state of the defect when the defect is written to the media. The figure shows a new defect controller module 511. During the use of the article 'the module adds a detected new defect to the defective memory. Finally, there is a built-in self-test (B ϊ st) unit 5 12. The function of this unit is to perform a series of test operations on the memory array, and to catch the defect group to write into the defect mapping memory 506. This series of test procedures is generally performed only when the product is started or when the product is started when a specified test jig () is used during the manufacturing process. The signal 5 1 3 indicates when the b I s T test is performed. The memory cell within the memory device is again divided into a plurality of antipodal blocks. Each antipodal block contains a plurality of memory cells within a memory device. Each checkbox indicates the smallest executable area that can be marked as good or bad for the defect management system. If a pair of antipodes contains any defective memory cell, the antipod is marked as a bad antipod. If a pair of map blocks is marked as a good map block, all memory cells in the block must be able to reliably store data when performing a memory boat test on their memory cells. It is necessary to understand that in future use, under certain circumstances, these memory cells may not be able to reliably store data. In this case,

586120 V. Description of the invention (11) The mapping box will be marked as bad, otherwise, the bad mapping box cannot be turned into a well-marked mapping box.

The number of memory cells in the antipodal block determines the relationship between the main memory array and the size of the defective antipodal memory required. Only a single bit is required to represent a pair of mapping blocks in a defective mapping memory vessel. This simply shows that a pair of mapping squares is good or bad. For example, if each antipodal block contains 102 memory cells, and the size of the memory array is 64 MB, the defective antipodal memory must be 64 KB. The defect management system allows the size of the mapping block to be adjusted to meet the needs of practical applications. The larger antipodes minimize the need for defective antipodal memory, but the disadvantage is that more good memory cells are wasted in the memory array, even when the memory array contains only a few bad memory cells, Then the entire antipodal block must be marked as a bad memory cell, and no memory cell in the antipodal block is used.

A memory array containing multiple defective memory cells is shown in FIG. The memory contains a separate mapping block 602. The memory array contains a large number of defects 603, which affect a large number of adjacent memory cells. The antipodal box containing any defective memory cell must be marked as a bad memory cell. These memory cells are shaded in the figure. Marking 604 indicates the area of the bad enantiomeric block caused by defect 603. The memory array also contains row defects 6 0 5. In memory, row and column defects are very common due to the actual structure of the underlying layer. In the entire memory array (including word lines and bit lines), the memory array is actually connected to

Page 15 586120, description of the invention (12) Don't memorize the level and path of the unit cell or break these connections and mark them as bad notes. Vertically staggered tracks. If, it will produce a defective row or column of the memory cell in the figure with some 60 results in some way. Line defect 6 is marked. The memory array also contains a row of defects 6 0 7. Those who are marked as a defect management system due to a defect are indicated as 608 in the figure. Generally, the number of rows of memory cells and the number of rows of memory cells in a pair of squares is a power of two. This allows the correct address of the bad object in the defective mapping memory to be obtained directly from the main memory address. You can use a simple shift and addition operation to calculate the address, which is inefficient for using

It is especially important for the microprocessor to handle this management system in software. Figure 7 shows the relationship between the defect of the main memory array and the corresponding defect map. Defective memory arrays are labeled 7 0 1. The trapped mapped memory is labeled 702. A single bit in memory to an antipodal block in a beta-cathode array. In the case of the counterpart Fangpo Rabbit τ & & Horse Defective, the content of the defect mapping is marked as 1, if it is displayed, the goodness is marked as 0, and vice versa. Denotes the relationship between the 70 3; 1 Ms enantiomeric block in memory and bit 70 in the defective antipodal memory.

Trap cake: When writing or reading data from the memory boat array ', it checks for missing data. , $ Department. When accessing from the same position t in a specific antipodal block, the next address reaches the end of a pair of antipodal blocks, the address increases and points to the starting point of the antipodal block. In this way, 'during the writing of data in the memory vessel', defective maps will be skipped. The figure is labeled with the number of mapping blocks that are not in each good mapping block.

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5. Description of the invention (13) These numbers indicate that there are 47 good blocks in the accessible memory array. The shape of the antipodal block has a direct effect on the number of antipodal blocks. According to the actual structure of the defect, the antipodal block is marked as a bad antipodal block. % Figure 8 shows yes, in this example shift. That is, the total number in each pair is the same and the same. Region 8 has 8 maps. So it's more than a defective block. There are 4 out of 6 in total. In the horizontal direction, there is only a defect in the pair of mapping heights. The relationship 6 is 4 blocks. The processing column 囷 9 is only in the example array of the example. The shape memory array maps the squares and therefore must be 0 1 to show the difference relationship between those marked with the squares, these 8 enantiomers. So in the row offset antipodal squares can contain a single column 'these antipodes, so the defect is more effectively displayed with the circle 6' in the shape of the memory array of these antipodes has been aligned in its columns The defects of Duan Yi's unit cell are round defects which are not good. This antipodal block is marked as antipodal by the block, which is less effective than the block containing the memory array. The total number of squares that are not 80 is in the column mapping. In the same memory, the rows and columns of the mapped blocks and the defective mapped blocks are numbered in the water ratio to the number of mapped blocks in the mapped memory in FIG. 6, and the areas 80 are not marked as bad. Poorly contrasting squares. Of all 3 areas in a pole column, two are regarded as 'horizontal deflection arrays' and lack vertical offset than the column sections. However, it is too long flat. The size of the required antipodes is also similar. In this figure, Figure 9 shows the antipodal square block shown by 9 in the figure, and the example of the square block is relatively the same as the row, but the figure shows the configuration of the antipodal squared column due to the bad column. . Ie from memory. Must understand

586120 V. Description of the invention (14) The total number of memory cells in each antipodal block is the same as that in Fig. 6, so the size of the required antipodal memory is also the same. The area 901 shows the opposite square marked as defective among the circular defects. A total of 8 antipodes are marked as bad antipodes, compared to 9 in Figure 6. Therefore, there is not much difference between the two. Area 9 0 good antipodal squares. Only two were. Efficient compared to square counterparts. The area 903 is displayed due to the block. There are a total of 8 pairs in this area and 4 out of 6. There is no efficiency in dealing with column gaps. In the extreme example, all the columns are in the column, but it is not economical to obtain a new column in the memory of each column for a long time. More power is required to access the individual columns. 2 shows those marked as not marked or not due to row defects, while in Figure 6 there are 4 times where the vertically offset mapper has column defects and the mapper marked as bad is marked as bad, and When the image is trapped, the vertically offset antipodal blocks are compared. The antipodal blocks can contain only one line of memory array width. However, when a difference is obtained from a time ratio in the same column, the power and efficiency of this method appear to be different than that in the same column. Therefore, the size and shape of the general configuration surprise box are consistent with the subject and can be used If the defects are in the same shape as the defects found from the owner δ Ji Yi, the general distribution is 5 and the size is shifted in the memory boat device, then the horizontal offset is used: right: = listed in a strong bias. Shift, then use vertical :::: ying = there is a strong built-in self-test on the line defect (Β Τ ς memory device, to generate -_ # = purpose to test the coverage of the defect that can be recorded, then, If you can get enough, figure 找出 to find most of the defects in the device

586120 Fifth, the invention description (15), then the lack of memory is stored in the memory, only a small amount of BIST try the memory, generally. Therefore, several implementations of B I s T know the technology to compare the cost. Because = the actual device on which this is done $ Nested socket on the ‘memory device used for the final product Normally, at B I S T. In addition, δ 1 8 Τ is the same as the number of additional defects included in the normal IS test when testing Μ Β 1 S τ and φ in the BS IS feed. As if the defect was hardly the cause. Regardless, this step by step when the memory test, the entire related defects due to the poor use of the environment, the product program period, the process can be started, and the program will not be tested without the need to extend the situation during the T cover The scope of the body. Stored data Micro-control Management Department Others How to reduce the device is necessary to be mirrored by the manufacturing. Conductivity counter phase can then be avoided in this part. During the use of the product, the manufacturing of the device or the system must include the use of the integration of the use part into the program t. Moreover, the cost of the same common operating products produced by this product can be used in the product. It will not be avoided. This is because of the use of one during the testing period in the health environment. With some custom memory devices in the final system, tracking and avoiding defects in the tester. In this part of the test, when the product is first energized, a set of signals from an external input system is performed to perform the process during the normal use of the product, which requires expensive memory and tester resources and time. Environmental conditions such as voltage and temperature are suitable. This allows the defect-mapped memory to be cleared first during the B I S T and can and therefore can be reduced during the use of the product.

586120 V. Description of the invention (16) When the period defect is detected in all the trial periods in some memory ships, In fact, the BIST corresponds to the field. This operation is more like magnetic data storage. The BIST can contain any test pattern that contains multiple matches, reducing the direction of the address, and the error identified in the addressing memory (ie, recorded as 1 or 0) And coupled in the mistake of the note. For DRAM, in some tests, the weak memory cell with the highest leakage rate will be exceeded, and since all the test tasks are completed, the good capacity left in the memory is not, it is considered that the device has failed. (iterative test). This item does not detect any new defects or unstable devices and must be tested in some way. The part used in the product is available to a screening process. Therefore, it can be used fully without violating the parameters and exceeding the maximum standby current. Generally speaking, a good device has a poor area and a good area. When under test, mark the map box as a bad format operation to determine bad areas. Format the media. Test configuration group. But in general, it changes the pattern along the data, adds or recalls. Design these tests to find out that the memory cell can only be stored in a reliable way between adjacent memory cells in the memory array. 'It is necessary to periodically update its content. Large update time to detect the high data. The latter 'must be checked to ensure that it is greater than a predetermined minimum. If the B I S D also contains iterative tests, the test is to continuously test the memory until then. This allows the principle of maximizing the number of memory cells in the product when more memory devices have to be made on the device for a large number of defects. For example, it is not possible to share the performance of available memory devices for all parameters. '

586120 V. Description of the invention (17) Figure 10 is a flowchart of the screening procedure of the present invention. The sequence is started in step 1001 with an unclassified portion of the available memory device. The screening procedure is performed in step 1002. A number of different test jobs are performed in this program. It includes functional memory test and parameter test. These tests were not performed thoroughly, but simply provided an indication of the number of defective memory cells in a particular device. One possibility is to use a commercial memory tester with a suitable encapsulated processor. However, these testers are generally designed to test all good memory devices, and generally cannot calculate the number of defective memory cells in a memory device, and these tests use a pass / fail (P ass / iai!) Test criteria. For DRAMit, the other option is to use a (personal computer) -based tester. Load the memory device into the carrier of the zero-plug force socket, and insert it—tau ^ Good memory module plug " mjiyi body module Liangyi * dropped the first module slot to run the operating system and The procedure I should use ^ ^ f stealth test program to check the modules under test as flesh. L 锸, ’, and indicates which parts have the largest defect memory cell count ^ # ^ + 2, the choice is to test the 4b component in the environment of the final product. But I can hide from this. Then you can enter; mark: = use the product with zero insertion force socket to produce feedback ;: quasi :::::, "screen these components. From these components failed ^. Some components have passed the test ' And that: ί: Choose r: r to change the environmental parameters to improve the test so that the components are advanced for the access required for these components V21 ΐ 1 ^ 586120

V. Description of the invention (18) The final application is strict. Generally for all belts to reduce the chance of components passing the selection criteria by mistake. 1. Test parameter setting protection Mark 1 0 0 3 is the decision point for screening. Make less than a maximum allowable number of components (or ,,, memory cell number test organization, the number of defect mapping squares), test the BIS test requirements. The flow of invalid components is marked with 2004, and the parameter selection is discarded, or it is used in some low-level cases. These invalid components are marked with 105. The components of the defect-passing assembly process are then used to assemble the article. Management system will pass these

Program 1 0 6 indicates that the product is completely and partially available memory device group S τ executed by the product. This is the case. The defect mapping relationship is written in the erasure condition. The first time it is energized, as long as the device is subsequently energized, it can be reflected in memory. After completing the BIST test, Perform a pass check on the product. This test: Nothing, during the ST program, after finding a defective block, based on a minimum memory capacity in BI. There will be-equivalent protective bands in the second screening = somewhere available. ▲ At this stage; test period

Less. The label 1 0 0 8 indicates that the number of invalid defeats will be quite ready, and the process of pus + + 1 ^. These products will be replaced by the most memory components of the 1009. At the end of the labeling, good products suitable for loading will be left. In addition to: the directory information in the volume data storage must also be ΐΠΠsuch as media; = maintained in the same part of the available memory · the total amount of storage, generally compared with the size of media data

586120 V. Description of the invention (19) The catalogue information is quite small. The directory data maintains the start and end positions of the media files, or some of the directory data must be stored in a highly reliable manner. If the recorded data is destroyed, it will result in inaccessibility. [Problems of the practice] Although the BIST test department has been used Additional memory defects arise during the use of one memory article. The probability is quite large enough to make the directory capital memory array. It is necessary to provide additional redundant information that can be reconstructed in a reliable manner. A majority voting method is used to achieve this. Figure 11 shows this method, which is stored three times in an area of memory device information. This copy is stored in the body device to prevent the memory ship device from generating a common mode failure. However, in some environments, different areas of different memory devices. From the individual bytes of a directory information, 1 is used to indicate the bytes that have been damaged from the correct value. In general, the proportion of corrupted bytes is relatively small. As long as the data is read from the directory, it is from each subgroup. The majority resolves, and the controller reads different copies of the data from the directory labeled 1 i 〇 and the correct value. So if the two digits of the data are returned. Therefore, a humble group of bytes is held by information that is relevant to it, and therefore media files, such as specific attributes. This is the case for these ships, but in general, the information can not be more than bad and multi-purpose 110. Actually the same situation as the deputy 10 2 Show 1 1 Reading 4 in this book indicates that this may still happen when a byte is destroyed. The situation is directly stored in determining the number of directories. The memory of different directories in the directory is stored in the same label. X mark 〇3. Take each bit. It ’s necessary to decide exactly the same from the tuple, then ’will not affect

586120 V. Invention Description (20) The ability to destroy the stored data. Mark the different groups of 1 1 recorded data with the letters "quote." The controller can return the correct "0". Familiar with this technique to apply a reliable positive code (E c C stores additional errors in the original data. But If the configuration is designed at a relatively long cost, the device can be tested in the B device and all the environmental conditions will be detected during the test. The quality of the playback will not be too large as long as it is used, and the label is not overall. The number of copies of the directory can be increased to improve the prevention of being represented by 0 to 5 bytes. From two values, the surgeon must store it in a way.) The reset element appears more. This technique is provided as a simple treatment of the defects of the 1ST time. The extra production of a small shadow kite. Good product defects show the data bits in the read example. However, the second remaining correct is marked with 1. Learn about the disadvantages of storing the catalog data in this technology for cataloging to allow the original bit error. Counts of defects implemented during microcontroller 0. But, just as there is no guard band. Due to defects. Shock in play, but sub. This tuple. Byte 10 6 Intraoperative. For example, the catalogue of the data is processed scientifically. Some readings are done to get the table from the correct one that has been destroyed. To use it, it can be stored. This data can still be calculated to be a relatively soft ship after the data is reproduced. The last time was 7G from the target data. Most of the data was sent to his organization to store it by mistake, even when replying to these complex, and it is necessary to consume the test to test in some available memory. The program test cannot guarantee the completion Any institution can place the media file in time or around the time it is possible to use the product, and if there are any defects that may occur during most of the use, it is necessary to make the memory cell an antithetical block. So in the future

586120 V. Description of the invention (21) This map box is not used for data storage. This organization allows the learning and new defects to be permitted during the use of the product. A checksum method is used to allow new defects to be detected during the use of the device. This feeling is shown in Figure 12. Among them, the number 1 2 0 1 is displayed in the individual map box in the memory array. It is represented as an 8x8 memory cell square. This block can be copied across multiple planes of the device, such as 8 bits. Therefore, the two-digit hexadecimal value in the figure is associated with each memory cell 1 2 0 2. The number of bits associated with each memory cell depends on the memory architecture used. Moreover, it is preferable that each antipodal block in the actual system has a relatively large size. As shown by the arrow 1 2 0 3, it is in an adjacent position in a pair of mapped squares. , Store a check sum in each map box. The last value is shown in this box, and it is marked as i 2 04. The sum check value represents the sum of all other stored values in the map box. If the data is corrupted in the map box, the combined check value will be used for detection. When reading data, the total check value is calculated at any time. It is then compared with the stored total check value. If the two are different, the antipodal block has been destroyed due to a defective memory cell in the antipodal block. The antipodal block is then marked as corrupted in the defective antipodal memory. It is possible that if a series of bytes are corrupted, it is possible to produce the same total check value and therefore no errors can be detected. However, the chances of this happening are quite small. It is necessary to understand that the defect management system of the present invention does not need to be established without knowing the meaning of the data bytes to use the mechanism.

586120 V. Description of the invention (22) It is not possible to determine which particular memory cell or group of memory cells is defective using the total inspection. However, this condition is not necessarily required because all the items included in the total check value fall in the same antipodal box 'and therefore the entire antipodal box must be marked as a bad antipodal box. The designation 1205 indicates a defective memory cell and therefore cannot store data in a reliable manner. When reading the data of the mapping block, the relevant total check value 1 2 0 6 is detected. The difference between the total check of calculation and storage will result in the map box being marked as a bad map box 'and therefore the map box will not be used to store data in the future. Those skilled in the art must be aware of mechanisms that can use other simple collective inspections. For example, a cyclic redundancy code (CRC) can be used to more reliably detect data corruption in a pair of mapping blocks. The disadvantage is that more time must be spent. This is an important consideration when deploying a defect management system in a low-cost microcontroller. Certain restrictions are used to prevent too many antipodes from being marked as defective antipods during a single read of a media file. This is because when each person marks a new mapping block as a defective mapping block, the capacity of the system will be reduced. The aggregate inspection agency cannot identify the invalidity of the aggregate inspection due to memory traps ^ or other causes that are counted in the system. If for some reason (for example, the memory is broken due to power failure, the media player broadcast must not be marked with all of the mapping boxes, so adjust the image to the bad situation caused by the unavailability of the product. The maximum number of bad mapping blocks is set to a fixed number. Once the limit Φ1P phase limit exceeds the reading of a specific media file, page 26, 586120 5. Inventor (23) The case may know Any invalidity encountered in that other combined inspection.

Another way to configure this method is to use an error correction code in each mapping block instead of just a simple total check value. This must occupy a larger ratio of capacity throughout the storage device, but has the advantage that many different types of errors can be corrected. In this method, these errors are corrected, such as part of the reading process, so the quality of the reading is at least degraded. However, the mapped block is still marked as a defective block, because the next time when data is written to the block, the defect may exceed the number that can be corrected by E c C. The device handles this process in an undetectable manner, adding no impact on quality. The use of this procedure requires the integration of high-level data use parts that can be stored in memory devices. When memory recalls the title. Such as reading, a large number of low 0 — the existing cached information. When the new cache is misused, the pair will determine the jump result. In the first place, the data will be missed. body. The mapping box is marked with the pair, and the entire pair has been lost at one time, which is worse than the original file. The reading of the file and the writing of this defect are not bad for the detection of a new defect. The image block is read to detect the defect. Therefore, the image block is not useful in making the media broadcast defect itself write once. This storage is determined in the quick case. When the cache memory is used from the missing image, if the data is used, the quality of the file that is initially stored in the file is then affected. Defective maps stored in Defective Maps led to a huge drop in the archives of a question. The defect pairs that must be stored are the bad ones.

586120 V. Description of the invention (24) Array. Because this cached information must be stored reliably, the above-mentioned majority method can be used for directory information. This program is shown in FIG. 13, where the label 13 00 is the content of the mapping of the defect mapping memory determined by the filling pattern, and the defect pattern is displayed in the main memory array to indicate i 3 〇2 said. The main memory array 81 'copies the contents of the defect map cache into multiple partially available memory devices, as shown in 1-3. Some sections of ^ that maintain the cached data are marked as the part of the defect mapping related to the 13ny1 memory device serial; 2 are independently read from the written data and written into the system, U = different media miscellaneous The file can be marked as i by the controller for update operation. In the reading controller of 130Θ,… the result of feeding into the memory during the sequence is to generate an address to the main memory. The function of the miscellaneous phosphorus taking controller is to mark 1 3 0 7 in the reading process to indicate that 10 f skip is defective. Antipodal squares. This data is due to the total number of people stored = new defects in memory. When a difference is read back, this condition will be detected: Check the read between the f-number and the calculated data. The total is displayed by the defect detector ^ 3 0 8 When a new defect is detected, change 〇 9 to use the total check. The appropriate bit in the M-enantiomer of the antipodal block is reflected by the reaction to show the situation; = the block 2 is marked in the defect map, and the defect map becomes a value of 10. Therefore, if the same media is read again as the previous antipodal block in is still included in this:

Page 28 586120 V. Description of the invention In the picture of the box, and when the box is updated, the memory defect of the actual layout is recorded. The element line or the observable memory is located in the actual memory. 0 1 Entire mapping in separated columns 14 0 3 There is a trappable effective A 3 and A body performs a left-handed operation called logic (25) The same defect The new defect can avoid the memory array related external body memory The digital position of the address where the crystal affects the cluster element line has a logical representation that is internal to the device condition. The data is shown as necessary squares, enabling the area through, and the column of 0, and even the side address address space ο 〇, has the shadow cell in the fast mapping 〇. But the adjacent ones, this will mark the deduction in the address space part of the space. Figure 14 The address space #### Actual distribution of honey. In YES, in the memory cell is a whole array of defect sites, in the middle of the unit cell. It ’s hard to store bad address space 4 0 6 ’and it ’s simple for the poor.

When new data is written into the memory array, three memory banks are taken to contain the newly determined defect pair. In some instances, the internal memory device is affected, and only a single cell is affected in many instances. If the reader is one word or the entire number of rows. Metagroups are not always directed to the outgroup of metagroups of devices. This is because of the many (topology mapping), the actual permutations are related. A row of defects 1402 is distributed in the memory device to indicate every other column in the center. So get up. Less than ideal, two antipodal squares. Such as the box address can get this defect. The one-to-one conversion reduces the one shown in the defect. This simple exchange can therefore be performed quite simply on a soft microprocessor. The address space turned so far and the one shown on the right

Page 29 586120 V. Description of the invention (26) The reverse mapping of the office results in the distribution of a single defect as shown in FIG. All addressing of the device is performed in the actual address space, where the address space is converted into a logical address space before the memory device is addressed. Corrections for defects in the logical address space are shown in the memory array 1440. Row defects 1 4 0 5 now only affect adjacent columns. Therefore, only a single map box must be marked as a bad map box, and the total amount of space available for some improvements. By getting the actual insider, the topology is actually determined to determine the functional memory to get the device, although understanding can be correct. It is simple to logic, and can be manufactured by the manufacturer. It has been added in the text of the above-mentioned devices. The manufacturer's inevitable part of the enlightenment device is partially heuristic. The topology of the bad part in the device should be better to change the memory boat function. The method of free memory search for the implementation and modification of the antipodal antipodal mapping is taken as 1 Kai / u Ding. The mathematical algorithm of the publishing component is not ideal. The total number of antipodal squares can be trapped. It is a good approximation of the present invention without departing from it. Internally, the number of blocks required for the purpose is to reach the maximum 0, but this map of the present invention is the information. However, the impact of statistically determined addresses is different. In the hour, the spirit

Drawing number description: 301 indicates 302, 305 data frame 303 grid pivot synchronization 304 meter head 401 memory device

Page 30 586120 V. Description of the invention (27) 402 address and control signal 403 data bus 404 memory controller 4 0 5 defect map memory 5 0 1 input data 502 data write controller 503 entire controller 504 Directory write controller 505 flag

506 Defect map memory 507 Directory read controller 508 Data read controller 5 1 0 Defect cache controller 509 Output channel 511 New defect controller module 512 Built-in self-test (B I ST) unit 513 signal

5 1 4 System architecture mark 601, 604 mark 6 0 2 Mapping block 603 Defect 6 0 5 line defect 6 0 6 Bad memory cell 6 0 7 line defect

Page 31 586120 V. Description of the invention (28) 608 Defect management system person 7 0 1 Memory array mark 7 0 2 Defect map memory 703, 704 mark 801, 901, 902 Area 1001, 1 002 Decision of step 1003 screening Point 1 0 0 5 Flow of passing components 1 0 0 7 Flow of invalid components 1 0 0 8 Flow of invalid products I 0 0 9 Program II 0 1 Memory device 11 0 2 Each byte 1103 has a correct value Destroyed bytes 1104 Controller 1 2 0 1 Individual mapped block in the memory array 1 203 arrow 1202 shows the last value in this block 1 2 0 5 defective memory cell 1 2 0 6 Total check value 1301 Content of the mapping of the defect mapping memory determined by the defect pattern 1 302 The defect pattern is displayed in the main memory array 1 303 is copied to multiple partially available memory devices

Page 32 586120 V. Description of the invention (29) 1 3 0 4 The part that maintains the cached data can be marked by the memory device 1305 majority controller 1 3 0 6 The result is fed into the new defect in the 1307 memory. The 1308 height indicates the Read of total inspection 1 3 0 9 Defect detection block 1 4 0 1 Defective memory device 1 402 Single line defect 1 403, 1 406 Block 1 4 0 4 Memory array 1 4 0 5 line defect 586 120 Schematic Brief description FIG. 1 shows a bit plane system of the conventional technology to use a memory device with multiple defective memory cell locations. Figure 2 shows a more sophisticated system of conventional techniques to re-display defective memory locations', in which an external AS IC with internal memory resources is used to correct defects in multiple individual memory devices. Fig. 3 shows the format of the data frame in the media data to appropriately store the data in the device using the defect management technique described above. Fig. 4 shows the structure of an article used in the defect management system described above. Figure 5 shows the overall architecture of the defect management system of the present invention, which shows the actual memory blocks and control modules configured in software or hardware to perform defect management. Figure 6 shows an example of a memory array with multiple defects, in which a square memory defect block is shown, and the number of blocks marked as unusable is used to illustrate the impact of the defect. Fig. 7 shows the same memory array as Fig. 6, both of which contain the same defects. 'This example shows that the application cannot be erased by the memory device to store these defects. 8 shows the same memory array as in Fig. 6, where the memory Array packs the same flaw. The figure shows a horizontally extending antipodal block to show, but Sun is not the impact of the shape of the antipodal block on the total number of memory cells in the bad antipodal block. The display shows the same memory array as in FIG. 6, where the memory array contains the same defects. The figure shows an antipodal block extending vertically,

P.34 586120 Schematic illustration to show the impact of the shape of the antipodal block on the total number of memory cells in the box that must be marked as bad. Fig. 10 is a flow chart for screening a memory device through the program, wherein the memory device is used in a product having the defect management system of the present invention. Figure 11. An example of directory data storage in a partially defective memory system. In this example, a majority system for reading data is used to complete the data. There are several map boxes in each map box. Figure 12 shows several map boxes. A total inspection of the internal structure. = 13 shows the cache of defect mapping. y 4 is not in several of the mapping blocks. The impact of the standard block address topology of the mapping block is based on the fact that # cannot be added and cannot be used by the user. In the figure, Hai-Six has an inverse effect on the negative impact of the address topology. . Revealed-simple mechanism

Claims (1)

• A defect memory device removes the location of the memory trap, stores the shape of the memory of the defect management system, and adds the system trap. The location of the new missing 2 storage of the disturbance 0 management system, the system contains ... This device contains multiple defect storage memory cells; 'This memory has multiple memory blocks to store the memory blocks Internally test the defective memory ship device, and configure the state of failure to indicate a new defect during the use of the defective area in each memory device, and map the detected defect to erase the defect mapping . The defect management system of item 1 of the profit scope, wherein the frame delimits the boundary, so that during the use of the product, the quality of the media playback will only produce a short period of time. The defect management system is configured in the processor's firmware. 4. The defect management system according to item 3 of the scope of patent application, in which a firmware and a directory are written into the controller to store the start and end addresses of the data file in the defect memory device. 5. The defect management system according to item 4 of the patent application scope, wherein the firmware is a directory reading controller to obtain the start and end addresses of the data files stored by the directory writing controller. 6. The defect management system according to item 5 of the application, wherein the firmware is a defect cache memory controller that maintains a copy of the defect mapping relationship associated with a particular data segment. 7 · If the defect management system of item 6 of the patent application scope, where 586120 6. Scope of patent application Defect cache memory Zhao controller stores a copy of the defect mapping relationship in at least one memory device. 8 · If the defect management system of item 1 of the patent application scope, a new defect controller is used to detect new defects during the use of the system, and add the new defects to the defect mapping memory. 9 · If the defect management system of item 1 of the patent application scope includes a built-in self-testing agency to set the status of defect mapping memory at the beginning. 10. The defect management system of item 9 in the scope of patent application, wherein the built-in self-testing mechanism is arranged in the firmware of an embedded microprocessor. Work 1 · If the defect management system of item 10 of the scope of patent application is applied, the built-in self-testing institution starts with a set of external input signals to the embedded microprocessor. During the use of the product containing the defect management system During normal operation, this test action cannot be generated. 12 · The defect management system according to item 1 of the patent application scope, wherein at least one memory mechanism is formed by a memory array, and the defect block of the at least one memory device is included in the addressable memory location of the memory array Array. 13. If the defect management system of item 12 of the patent application scope, the size of the defective block is a power of two, so the conversion of the memory address to the address of the mapped block can be simplified. Λ — I4 · If the defect management system of item 12 of the patent application scope, the defect ancient secret α, the size of the block can be adjusted by the shape distribution of the defects detected by the memory device. Page 37 6. Scope of patent application 15. If the defect scope t of the patent scope is set to be the smallest usable in a screening agency: 16. The screening procedure is included in the scope of patent scope Type microprocessor 17. As in the scope of patent application, maintaining at least one memory device = data provides a reliable storage method. More than 18 · If the byte of the information is read by the majority controller in the scope of the patent application, if the byte of the information is destroyed, you can also get ... 19 · If the first checksum of the scope of the patent application and the The selection values are related. If the total inspection in the scope of the patent application does not comply with the stored data, the defect box is marked as 21 in the mapping memory. The 'data' makes the read controller never fail. 2, 2 · If the debt measurement of the new defect in the scope of Shenyan patent No. 21 leads to the need to update the new data into the main memory ship array, the defect management system, in which the test output is checked to verify the Defect management system, its implementation. For the defect management system, the directory information in it is for the defect management system in this item, its information, if a few directories are valid information. The defect management system, in which the value of the defect management system of the data items stored in the defective block, is added to the defective block. Defect management system for items, one section of the defect block is a defect management system that reads several items in the cache memory block, its defect memory ’, but it was not used as a more updated copy of the cache. Page 586120 Page 39