TW582092B - Damascene interconnect with bilayer capping film - Google Patents

Abstract

A damascene interconnect structure with a bi-layer capping film is provided. The damascene interconnect structure comprises a semiconductor layer and a dielectric layer disposed on the semiconductor layer. The dielectric layer has a main surface and at least one damascened recess provided on the main surface. A copper wire is embedded in the damascened recess. The copper wire has a chemical mechanical polished upper surface, which is substantially co-planar with the main surface of the dielectric layer. After polishing the upper surface of the copper wire, the upper surface is pre-treated and reduced in a conductive plasma environment at a temperature of below 300 DEG C. A bi-layer capping film is thereafter disposed on the upper surface of the copper wire. The bi-layer capping film consists of a lower HDPCVD silicon nitride layer and an upper doped silicon carbide layer.

Description

582092 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a metal interconnect structure, and more particularly to a copper-inlaid interconnect structure formed by a hi 1 lock. The shrinkage of the previous technology and the integration of the new material with the new material resulted in the inconsistent component size and technical challenges. The best material for the linear scale below 0.18 microns made it naturally The longest route of connection, its + 2t, 2π, internal connection process includes inlay and double-inlay ί ί ΐ Ϊ enemy process (dUal damascene is a kind of i, > / metal wire and plug (P 1 Ug) The upper and lower stacked structure I wires are connected by ϋ 7 to connect the different elements in each layer of the semiconductor wafer and the machine H w 2 to form a double damascene. When the structure is embedded, a finalization will be performed to make the Feng Yue process ( ChemiCal mechanical polish (CMP), and ί Τ: The surface of the film becomes very flat, which is very conducive to the subsequent processes such as various deposition processes (H0t〇_llth〇graphy), in order to prepare the structure so that With mUlUleVel interconnects, I structure is widely used in the manufacturing process of integrated circuits. However, the development of the U hibis Λ Θ road is becoming increasingly sophisticated and complex. How to improve the dual mosaic ϊ Ϊ Ϊ L and improve the manufacturing method of the dual mosaic structure is an important issue in the current integrated circuit manufacturing process. 1 Page 7 582092 V. Description of the invention (2) Please refer to Fig. 1. Fig. 1 is a schematic cross-sectional view of a conventional double-inlaid interconnect line aligned vertically. As shown in FIG. 1, the wafer 100 includes a lower-layer damascene conductor 102 and an upper-layer damascene conductor 104, and the two are electrically connected through a via 106. The lower-layer mosaic wire 102 and the upper-layer mosaic wire 104 are embedded in the lower-layer dielectric layer 108 and the upper-layer dielectric layer 110 by a damascene process, respectively. As known to those familiar with the industry, the formation of the interstitial hole 106 is integrally defined with the trench structure that accommodates the upper layer of inlaid conductor 104, and the interstitial hole 106 is formed in a lower dielectric layer. In the intermediate dielectric layer 112 between the layer 108 and the upper dielectric layer 110. Between the intermediate dielectric layer 11 2 and the upper dielectric layer 110, a stop layer 1 2 2 is formed. The lower-layer inlaid wire 102 is basically composed of a copper core 130, a barrier 126 covering the copper metal 130, and a seed layer 128. The upper layer | inlaid wire 104 is basically composed of a copper metal wire 136, a barrier layer 132 covering the copper metal wire 136, and a seed layer 134. In the copper damascene process, whether it is a single damascene process or a double damascene I process, generally, after forming the lower damascene conductor 102 and the upper damascene conductor 104, respectively, the lower damascene conductor 102 or the upper damascene conductor is exposed | The wire 1 0 4 is first subjected to surface reduction (reducti ο η) pretreatment, and then in-situ reacts in-situ with chemical vapor deposition (CVD) to inlay the lower-layer inlaid wire 102 or the upper-layer inlaid wire The surface of 104 is covered with capping 1 ayer 1 2 0 and 1 2 4. Reduction pretreatment is usually 1 using a wafer in a CVD machine at 40 ° C hydrogen plasma or ammonia plasma | cleaning exposed exposed lower-layer embedded wire 102 or upper-layer embedded wire 104 table

Page 8 582092

5. Description of the invention (3) surface to reduce or completely remove copper metal oxide residues that may be formed on the surface of the lower-layer inlaid wire i 〇 2 layer of inlaid wire 104. Next, a plasma enhanced chemical vapor deposition (PECVD) process is performed in the same CV Etai at a temperature of 400 ° C to deposit and form a silicon nitride protective layer 12 and 12 and the thickness can reach 50. 〇Age or more. However, the above-mentioned conventional mounting technology has caused serious leakage current problems. This is due to the high-temperature thermal process of surface reduction pretreatment of the lower-layer damascene conductor 102 and the upper-layer damascene conductor 104 and subsequent PECVD protective layer deposition. Causes a stress fracture of the lower dielectric layer iOS, the upper dielectric layer 110, and the silicon nitride / dead layer 120, 124, so that the subsequently filled copper metal may spread outward along this stress fracture, A so-called leakage churning (hiiiock) 140 is generated, as shown in FIG. This leakage hump 140 is the leakage path of the copper wire to the surrounding dielectric layer. It can be seen that the traditional copper damascene process is not ideal in terms of leakage current prevention and efficiency, and needs to be further improved. SUMMARY OF THE INVENTION The main purpose of Ming is to provide a town with a double-layered protective layer and an internal connection structure, which can reduce the thermal budget and suppress the occurrence of leakage humps. To achieve the above object, the present invention provides a

582092 V. Description of the invention (4) A damascene metal interconnect structure including a semiconductor wafer; a dielectric layer is provided on the semiconductor wafer, and a damascene recess is formed in the dielectric layer; a copper metal wire is provided, In the damascene cavity, the copper metal wire has an upper surface polished by CMP so that the upper surface is approximately flush with the dielectric layer; and a double-layered protective layer including a silicon nitride underlayer and a doped An upper layer of doped silicon carbide covers the upper surface of the copper metal wire. The upper surface of the copper metal wire layer is pretreated with a hydrogen plasma or an ammonia plasma after CMP grinding. The HDPCVD silicon nitride underlayer is deposited using a high-density plasma deposition (HDPCVD) method at 350 ° C. The present invention uses a high-density chemical vapor deposition (HDPCVD) process to deposit a silicon nitride underlayer and utilizes the characteristics of the HDP silicon nitride underlayer to perform reduction pretreatment starting from room temperature, reducing thermal budgets and inhibiting The generation of leakage turbulence. In addition, in order to make up for the insufficiency of the bottom layer of HDP nitride, a low dielectric constant doped silicon carbide upper layer is deposited thereon. The bottom layer of silicon nitride and the upper layer of doped silicon carbide with low dielectric constant constitute a bi-layer protect layer, which can greatly increase the burial degree and operation performance of the interconnection. In order for your review committee to have the technical content, please refer to the figure below. However, the drawings are for reference only. Further understanding of the features of the present invention The detailed description and accompanying description of the present invention is not intended to

582092 V. Description of the invention (5) Implementation mode Please refer to FIG. 2. FIG. 2 is a schematic cross-sectional view of an embedded interconnect according to a preferred embodiment of the present invention. As shown in FIG. 2, the semiconductor wafer 2000 includes a dielectric layer 212 on which a damascene trench 217 is formed. The conductive trench 2 1 7 is filled with a barrier layer 2 1 5, a seed layer 2 1 3, and a copper metal conductive layer 2 1 0. The dielectric layer 2 1 2 may be made of a low-dielectric constant material, including FLARETM, SiLKTM, a polymer (arylene ether) polymer, a parylene compound, and a polyimide system. Materials with a dielectric constant less than 3, such as polymers, fluorinated polyimide, HSQ, BCB, fluorosilica glass (FSG), silicon dioxide, porous silica, or Teflon . The barrier layer 2 1 5 includes titanium, titanium nitride (τ i N), nitride button (TaN), tungsten nitride (WN), and combinations thereof. The copper metal wire layer 210 has an upper surface 216 which has been ground by CMP. When the copper metal wire layer 2 10 is polished using CMP, the polishing stop layer 2 1 4 is used as the polishing end layer. Generally, silicon nitride is used. The upper surface 2 1 6 of the copper metal wire layer 2 1 6 is pre-treated with a reducing gas such as a hydrogen plasma or an ammonia plasma after CMP grinding, and is then covered with a double-layer protection. The bi-layer protection film includes a HDPCVD silicon nitride layer 220 and a doped silicon carbide layer 240. It should be noted that the 疋 ′ inlaid wire trench 2 1 7 may also have a via structure (v 丨 a), and then the copper metal filled in the via structure is a plug.

582092 V. Description of the invention (6) The effect of the present invention is mainly manifested in the use of a double-layered protective layer composed of a HDPCVD nitride nitride layer 22o and a doped silicon carbide doped silicon carbide layer 240. Among them, HDPCVD silicon nitride layer 220 is based on high-density plasma chemical 9 vapor deposition (HDPCVD) technology, between 30 (TC to 400 ° C, preferably low & operating temperature at 350 ° C, The source power is higher than 2 250 watts, and the bias power (bias power) is about 1 800 watts for the deposition of a silicon nitride layer 22 in a plasma environment. In the HDPCVD process, the temperature can be raised from room temperature, so The thermal budget can be reduced, and the stress cracking effect on the dielectric layer 2 12 and the silicon nitride layer 2 2 0 can be reduced. Please refer to FIG. 3, and another advantage of using the HDPCVD silicon nitride layer ^ 20 is that it can At a temperature lower than 30 (rc, source power (sour): higher than 3,000,000 watts (watt ^ environment), the upper surface is reduced by ammonia or hydrogen plasma for about 10 to 60 seconds. 21 6 Pretreatment, due to HDpcVD | process characteristics, the reduction pretreatment can start to warm up from room temperature. In high density 5 plasma environment, the pretreatment can be completed only at 300 ° C, reducing 埶 pre ^^ = general, it is recommended The thickness of the HDPCVD silicon nitride layer 220 is about 300 Å to 700 Å, preferably 500 Angstroms. The thickness of the HDPCVD silicon nitride layer 220 may be a thermal process. The resulting resistance is insufficient. The present invention additionally applies a carbide carbide layer on the HDPCVD silicon nitride layer 220 to a 24 ° doped carbide layer. The layer 240 may be an oxygen doped stone. It is a silicon carbide compound composed of Shi Xi, carbon, oxygen, nitrogen or anti-, I, and lice, respectively. Doped silicon carbide layer Page 12 582092

24 0 can be obtained from dimethyl silicon sintered (3 Ms) arsenite at less than 40 (TC ′, preferably less than 35 0t, / Xingjing (4-MS) as the precursor. Doped silicon carbide layer 24. It has the following features: deposition of the substrate and HDpcvdA ί ΐ ί Ϊ Π: the left side of the hybrid layer 240 has a lower dielectric layer, the number is wide, and the J is integrated. For example, please refer to FIG. 4, which is the present invention A schematic cross-sectional view of a dual damascene embodiment. As shown in FIG. 4, the semiconductor wafer 400 includes a lower layer of damascene conductor 402 and an upper layer of damascene conductor 404, both of which are inserted by filling a via 406. Plug connection. The lower-layer inlaid wire 402 and the upper-layer inlaid ^ line 4 04 are inserted into the lower-layer dielectric layer 408 and the upper-layer dielectric layer 4 10 after the damascene process, respectively. It is known that the formation system of the interlayer hole 406 and the trench structure accommodating the upper-layer inlaid wire 404 are integrally defined, and the interlayer hole 406 is formed between a lower dielectric layer 408 and an upper dielectric layer 410. In the middle dielectric layer 41 2. The lower-layer inlaid wire 40 2 is basically composed of a copper core 430 and a copper core 430. The layer 4 2 6 and the seed layer 4 2 8. The upper-layer inlaid wire 4 0 4 is basically composed of a copper metal wire 4 3 6, a barrier layer 4 3 2 covering the copper metal wire 4 3 6 and a seed layer 434 After forming the lower-layer inlaid wire 402 and the upper-layer inlaid wire 4 0 4 respectively, the lower-layer inlaid wire 402 or the upper-layer inlaid wire is exposed.

582092 V. Description of the invention (8) 40 4 Surface reduction pretreatment is performed on the surface, and then in-situ is inlaid with high-density plasma chemical vapor deposition (HDPCVD) under the reduction pretreatment. The surface of the conductive wire 402 or the upper-layer embedded conductive wire 404 is covered with a double capping layer 420 and 424. The purpose of the double-layered protective layers 420 and 424 is to prevent the copper surface from oxidizing and prevent the copper metal from diffusing outward. The double-layered protective layer 420 includes an HDP silicon nitride underlayer 420a and an upper layer of doped silicon carbide 420b, and the double-layered protective layer 424 includes an HDP silicon nitride underlayer 424a and an upper layer of doped silicon carbide 424b. The reduction pretreatment usually uses the wafer in a HDPCVD machine to clean the surface of the lower inlaid wire 40 2 or the upper inlaid wire 40 4 with a hydrogen plasma, N2H2 plasma, or ammonia plasma below 300 ° C to reduce the surface. Or completely remove the copper metal oxide residues that may be formed on the surface of the lower inlaid wire 402 or the upper inlaid wire 404. Next, a high-density chemical vapor deposition (HDPCVD) process is performed in the same HDPCV Etai at a temperature below 350 ° C to deposit and form a silicon nitride underlayer 420a or 424a with a thickness of about 500 angstroms. Compared with the conventional technology, the present invention uses a high-density chemical vapor deposition (HDPCVD) process to deposit and form a silicon nitride underlayer 420a or 424a, and utilizes the characteristics of HDP silicon nitride underlayer, which can be performed from room temperature The reduction pretreatment reduces the thermal budget and suppresses the occurrence of leakage chutes. In addition, ^ makes up for the shortcomings of the HDP silicon nitride bottom layer, and a doped silicon carbide top layer with a low dielectric number is deposited thereon. The bottom layer of silicon nitride and the low-k doped doped carbides constitute a bi-layer protective layer.

Page 14 582092 V. Description of the invention (9) protection) can greatly increase the reliability and operating performance of the interconnections in the integrated circuit. The above advantages show that the present invention has fully complied with the statutory requirements of industrial availability, novelty, and progress as stipulated by the Patent Law. 爰 An application is filed in accordance with the Patent Law. Please check and approve the patent in this case. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 15 582092 Simple illustration of the drawing Simple illustration of the drawing FIG. 2 is a schematic enlarged sectional view of a mosaic structure of the present invention. Figure 3 is a schematic diagram of the thermal budget of the reduction pretreatment of the present invention. FIG. 4 is a schematic cross-sectional view of a dual mosaic embodiment of the present invention. Schematic symbol description

Page 16 100 Wafer 102 Inlaid wire 104 Lower inlaid wire 106 Interlayer hole 108 Lower dielectric layer 110 Upper dielectric layer 112 Intermediate dielectric layer 120 Protective layer 122 Stop layer 124 Protective layer 126 Barrier layer 128 Seed Layer 130 copper metal line 132 barrier layer 134 seed layer 136 copper metal line 140 leakage hump 200 semiconductor wafer 210 copper metal 212 dielectric layer 213 seed layer 214 grinding stop layer 215 barrier layer 216 upper surface 217 wire trench 220 HDPCVD silicon nitride layer 240 doped silicon carbide layer 400 wafer 582092

Page 17 402 Lower inlay wire 404 Upper inlay wire 406 Dielectric hole 408 Lower dielectric layer 410 Upper dielectric layer 412 Intermediate dielectric layer 420 Double protective layer 422 Stop layer 424 Double protective layer 426 Barrier layer 428 Seed Layer 430 copper metal wire 432 barrier layer 434 seed layer 436 copper metal wire 420a HDP silicon nitride bottom layer 42 0b doped silicon carbide upper layer 424a HDP silicon nitride bottom layer 424b doped silicon carbide upper layer

Claims (1)

582092 VI. Scope of patent application 1 · A kind of metal-inlaid interconnect structure with a double-layer protective layer includes: ', a semiconductor wafer; a dielectric layer provided on the semiconductor wafer' the dielectric layer A mosaic recess is formed inside; a copper metal wire is 'set in the recess after the mounting', and the copper metal wire has an upper surface that has been ground by MP, so that the upper surface is approximately flush with the dielectric layer; And—the double-layer protective layer 'includes an HDPCV D gasification chip bottom layer and a doped silicon carbide upper layer overlying the upper surface of the copper metal wire. 2 · The inlaid metal interconnect structure with a double-layer protective layer as described in item 1 of the scope of the patent application, wherein the upper surface of the copper metal wire layer is ground by CMP, and then hydrogen plasma or ammonia (ammonia) is used. ) Plasma pretreatment. 3. As described in item 2 of the scope of the patent application, the inlaid metal interconnect structure with a double-layered compliance layer, wherein the hydrogen plasma or ammonia plasma pretreatment is below 300 ° It is carried out at C for about 10 to 60 seconds. 4. The inlaid metal interconnect structure with a double-layered protective layer as described in item 1 of the scope of the patent application, wherein the H D P C V D nitride nitride substrate is used at 350 °. (: High-density plasma deposition (HDPCVD) deposition method. 582092 VI. Scope of patent application 5 · The embedded metal interconnect structure with double-layer protective layer as described in item 1 of the scope of patent application, wherein the upper layer of doped silicon carbide can be Si COH or SiCNH. 6. A method of forming a damascene metal interconnect structure with a double-layered protective layer, comprising: providing a semiconductor wafer; depositing a dielectric layer on the semiconductor wafer; a damascene recess is formed in the dielectric layer Depositing a copper metal wire in the inlaid cavity; performing a CMP process so that the copper metal wire has an upper surface polished by CMP so that the upper surface is approximately flush with the dielectric layer; and deposition A double-layered protective layer includes an HDPCVD silicon nitride underlayer and a doped silicon carbide upper layer overlying the upper surface of the copper metal wire. 7. The method according to item 6 of the scope of patent application, wherein the upper surface of the copper metal wire layer is pretreated by CMP or hydrogen plasma or ammonia plasma. 8. The method according to item 7 of the scope of patent application, wherein the hydrogen plasma or ammonia gas plasma pretreatment is performed at a temperature below 300 ° C for about 10 to 60 seconds. 9. The method as described in item 6 of the patent scope, wherein the HDPCVD nitrogen