經满部中次標卑局兵工消费合作社印¾ 582076 A7 B7 五、發明説明（） 發明領域t 本發明與一種半導體製程中疊合標靶之結構有關，特 別是一種提升準確性之疊合標靶結構。 發明背景 近來在電路設計上有明顯節省空間的趨勢，電路元 件間也使用了二或三層的金屬內連線，且在產生某一特定 功能時所需主動元件的數量也持續減少。自從1C製造業開 始於晶片中加入多重金屬內連線後，準確對位技術便是確 認一膜層可以對準一底層的重要關鍵，而對位的精準性也 常被思考可以如何使多重層間之層與層有更精確的對應 。對接觸蝕刻或晶圓沈積而言，其每片晶圓上常有許多的 疊合標靶（overlay target)。爲了得到必要的精確量測，在 半導體製程中一般都會在晶片上使用疊合標靶，而這些對 準標記往往形成於晶圓的邊緣用來量測及確認膜層和膜 層間之疊合準確性。如同在先前技術中所熟知，在一量測 操作中，一具有疊合標靶之晶圓利用量測工具把晶片上的 疊合標靶當作參考點，可以很精確的對準晶圓上之前一膜 層。一般而言，量測工具會以雷射光束去感應疊合標靶的 位置。兩種對準方式分別如第一圖及第二圖所示，桌一圖 中的疊合標耙是所謂的盒中盒（box-in-box)型，一正方形 圖案10在一較大的正方形圖案12中形成，此其所以稱爲盒 中盒。量測工具藉著量測兩個正方形圖案間的階梯高度 本紙乐尺度適用中國國家標隼（CNS ) Λ4規格（210X 297公釐） -- (請先閱讀背面之注意事項#填寫本頁) 二丁 -" 582076 \Ί __ _Β7__ 五、發明説明（） (step height)來確定疊合之狀況。另一種精確對位即指條 中條型（bar-in-bar)疊合標靶，於複數個第二條狀結構22 所環繞之區域中形成複數個第一條狀結構20。此兩種疊合 標靶的度量方式都是藉著偵測圖案邊緣來精確對位。 一般而言，疊合標靶會在晶圓上形成圖案，當越來 越多的膜層加入1C時，然而在建造疊合標靶時會產生一個 問題，即其與接觸製程並不相容，特別是當元件的尺寸縮 小至次微米以下時，疊合標靶將遭遇一些問題。 經濟部中央標準局與工消资合作社印¾ (請先閱讀背面之注意事項再填寫本頁) 以縮小接觸製程而言，在次微米尺度的範圍中，該縮 小接觸的寬度小於0.3微米，然而，對準標記的維度卻大 約是40微米。疊合標靶圖案的邊緣或表面將被蝕刻過程所 破壞，其說明及相關圖示如下，如第三圖所示，在元件區 30中，一光阻層34形成圖案於一介電層36之上用以定義一 縮小接觸區。此外，亦藉著光阻層34在測量區32中定義出 一疊合標靶（盒中盒）區3 8，亦即同時使用光阻層34形成縮 小接觸及疊合標靶。然而，如第四圖所示，在蝕刻製程中 ，一高分子層40將沿著晶圓表面生成，此高分子層40是由 光阻層與參與蝕刻製程的氣體發生反應所產生之副產物 。一般而言，該高分子層將形成一罩幕並降低蝕刻效果。 如第五圖所示，當接觸點42在介電層3 6中形成後，疊合標 靶44的表面高度或圖案邊緣將形成平坦圓滑的上層表面 ，亦即，對精確量測而言，疊合標靶具有差的對比作用。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公楚） 經漪部中央標導局與Η消费合作社印裝 582076 A7 _ B7 五、發明説明（） 發明目的及槪沭： 本發明之目的在提升半導體製程中疊合標靶之準確性 一疊合標靶包括在一半導體晶圓中形成一基地區，在 基地區上形成複數個第一種圖案並構成一正方形或長方 形。該第一種圖案形成條狀結構，並可在一膜層上形成突 起的部份或凹下的部份，該條狀圖案之長度及寬度分別爲 八至二十，一至二微米。然後沿著基地區的四個邊緣形成 複數個第二種圖案，同樣的，第二種圖案可以是突起的部 份或凹下的部份，且該第二種圖案的形狀可以是正方形或 長方形。第二種圖案的維度大約爲0.5至1微米，在兩個相 鄰的第二種圖案間之距離大約爲0.3至0.8微米。 圖式簡單說明： 藉由以下詳細之描述結合所附圖示，將可輕易的 了解上述內容及此項發明之諸多優點，其中： 第一圖所示爲先前技術中之疊合標靶。 第二圖所示爲另一種先前技術中之疊合標靶。 第三圖爲半導體晶圓之截面圖’顯示根據先前技_ 定義接觸點及疊合標靶之步驟。 第四圖爲半導體晶圓之截面圖’顯示根據先前技術 蝕刻一膜層以形成接觸點及疊合標靶之步驟。 本纸張尺度適用中國囤家標準（CNS ) Λ4規格（210X 297公釐） 飞 -- - (請先閱讀背面之注意事項再填苟本頁) 582076 A7 --^______ 五、發明説明（） 第五圖爲半導體晶圓之截面圖’顯不根據先則技術 形成接觸點及疊合標靶後所產生的結果。 第六Α圖爲本發明疊合標靶之俯視圖。 第六B圖爲本發明疊合標靶之截面圖。 第六C圖爲本發明疊合標靶之截面圖。 第七圖爲半導體晶圓之截面圖，顯示根據本發明形 成一光阻以定義一疊合標靶區之步驟。 八圖爲半導體晶圓之截面圖，顯示根據本發明形成 疊合標靶區之步驟。 第九圖爲半導體晶圓之截面圖，顯示根據本發明形 成疊合標靶。 發明詳細說明： 本發明所要揭示的爲半導體製程中一種新的疊合標 靶結構。本發明對次微米元件製程中的對準技術有極大的 功用。更者，本發明亦提供了一具有良好陡峭邊緣之疊合 標靶，以便在精確確認疊合狀況之控制，本發明提供較佳 之對比及較好之疊合標靶以利於量測時產生較佳的對比 作用，關於本發明之詳細說明如下。 經4部中*標枣局兑Μ消费合作社印¾ (請先閱讀背面之注意事項再填寫本頁) 一般而言，疊合標靶都是藉著微影及鈾刻製程在一 Jfe 層或晶圓上形成圖案，如第六A圖所示，根據本發明形成 一可用來製造積體電路之疊合標靶60,疊合標靶一般都是 在晶圓的邊緣地區形成，從俯視圖來看，該疊合標靶60 本紙張尺度適用中國國家標準（CNS ) Λ4况格（210X297公釐） 好淹部中决樣卑局Μ,τ.消费合作社印^ 582076 A7 B7 五、發明説明（） 包括一形成於半導體晶圓上之基地區62,。該區域可以是 任何適當的形狀，如正方形，長方形或其他類似形狀。接 著於基地區62上形成複數個第一種圖案64(最好是四個） ，並構成一正方形或長方形以便精確對準。該第一種圖案 64最好是形成條狀結構，且在截面圖中可以是一膜層突起 的部份或凹下的部份，分別如第六B圖、第六C圖所示。 這兩個圖示爲第六A圖中A-A’連線之截面圖。該條狀圖64 之長度及寬度分別爲八至二十，一至二微米。 接著沿基地區62的四個邊緣形成複數個第二種圖案 66以便精確對準，該第二種圖案66具有相對於第一種圖案 64較小的尺寸。同樣的，該第二種圖案66如第六B圖、第 六C圖中所示，可以是一膜層突起的部份或凹下的部份， 且該第二種圖案66的形狀可以是正方形或長方形，該第二 種圖案66之維度大約爲0.5至1微米，兩個相鄰的第二種圖 案66間之距離大約爲0.3至0.8微米，第二種圖案66的設計 可以確保疊合標靶60具有良好陡峭之邊緣，以便在精確量 測時產生較佳的對比作用。 接著參照第七圖，根據本發明在一膜層72的頂層上形 成一光阻層70用以定義第一種、第二種圖案。則如同上述 ，參照第八圖所示，在形成第一種、第二種圖案的ri刻製 程中，一高分子層74將沿著該膜層72及該光阻層70的表面 形成。持續進行蝕刻製程以蝕刻膜層72，該高分子層74 及該光阻層70在此扮演一罩幕之角色。然而，該高分子層 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公潑） \^ ：訂 「^ (請先閱讀背面之注意事項再填寫本頁) 582076 A7 B7 五、發明説明（) 將在蝕刻過程中被移除，並由此形成作爲第二種圖案並具 有狹窄底部的凹槽部份76,以及作爲第一種圖案之凹槽部 份78，如第九圖所示。第一、第二種圖案76、7 8仍具有陡 峭的邊緣以利於邊緣偵測。如此一來，對縮小接觸製程或 其他半導體製程，該疊合標靶亦能提供精確對準。可變換 替代地，也可以只用第二種圖案76來做精確對準。 對熟習此項技術的人即可了解，對未來各種不同的 修正及類似的安排皆應包含於後附申請專利之精神及範 圍內。並且對其範圍應給予最廣泛之解釋，以便括及所有 修正與類似結構。另外，本發明雖以一較佳實例闡明如上 ，然其並非用以限定本發明精神與發明實體，僅止於此一 實施例爾。對熟悉此領域技藝者，在不脫離本發明之精神 與範圍內所作之修改，均應包含在下述之申請專利範圍內 (請先閱讀背面之注意事項再填寫本頁) 經漭部中决標導局吳工消费合作社印裝 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐）Printed by the Manchurian Intermediate Standards Bureau, Military Industrial Cooperative Cooperative ¾ 582076 A7 B7 V. Description of the Invention () Field of the Invention The present invention relates to the structure of a superimposed target in a semiconductor process, especially a superimposed superimposed accuracy Target structure. BACKGROUND OF THE INVENTION Recently, there has been a clear space saving trend in circuit design. Two or three layers of metal interconnects have also been used between circuit elements, and the number of active components required to produce a specific function has continued to decrease. Since the introduction of multiple metal interconnects in wafers in 1C manufacturing, accurate alignment technology has been an important key to confirming that a film layer can be aligned with a bottom layer, and the accuracy of alignment is often thought about how multiple layers can be made. The layers correspond more precisely to the layers. For contact etching or wafer deposition, there are often many overlay targets on each wafer. In order to obtain the necessary accurate measurement, stacked targets are usually used on the wafer in semiconductor processes, and these alignment marks are often formed on the edge of the wafer to measure and confirm the accuracy of the film layer and film layer overlap Sex. As is well known in the prior art, in a measurement operation, a wafer with a stacked target uses a measurement tool to use the stacked target on the wafer as a reference point, which can be precisely aligned on the wafer Before a film layer. In general, the measurement tool uses a laser beam to sense the position of the superimposed target. The two alignment methods are shown in the first and second figures respectively. The superimposed standard rake in the first table is a so-called box-in-box type. A square pattern 10 Formed in a square pattern 12, this is why it is called a box-in-box. The measuring tool measures the step height between two square patterns. The paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm)-(Please read the precautions on the back first # Fill this page) Ding- " 582076 \ Ί __ _Β7__ Five, the invention description () (step height) to determine the state of superposition. Another precise alignment is a bar-in-bar stacked target, forming a plurality of first strip structures 20 in the area surrounded by a plurality of second strip structures 22. These two superimposed targets are precisely aligned by detecting the edges of the pattern. Generally speaking, superimposed targets will form a pattern on the wafer. When more and more layers are added to 1C, a problem will arise when constructing superimposed targets, which is not compatible with the contact process. , Especially when the size of the component is reduced below sub-micron, the superimposed target will encounter some problems. Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and the Industrial and Commercial Cooperatives (please read the notes on the back before filling this page) to reduce the contact process. In the sub-micron range, the width of the reduced contact is less than 0.3 micron, The dimensions of the alignment marks are about 40 microns. The edge or surface of the superimposed target pattern will be damaged by the etching process. The description and related diagrams are as follows. As shown in the third figure, in the element region 30, a photoresist layer 34 forms a pattern on a dielectric layer 36. The above is used to define a reduced contact area. In addition, a stacked target (box-in-box) region 38 is also defined in the measurement area 32 by the photoresist layer 34, that is, the photoresist layer 34 is used to form a reduced contact and a stacked target. However, as shown in the fourth figure, during the etching process, a polymer layer 40 will be generated along the wafer surface. This polymer layer 40 is a by-product generated by the reaction between the photoresist layer and the gas participating in the etching process. . Generally speaking, the polymer layer will form a mask and reduce the etching effect. As shown in the fifth figure, when the contact point 42 is formed in the dielectric layer 36, the surface height or pattern edge of the superimposed target 44 will form a flat and smooth upper surface, that is, for accurate measurement, Superimposed targets have poor contrast. This paper size applies Chinese National Standard (CNS) Λ4 specification (210X297). Printed by the Central Bureau of the Ministry of Economics and Printing and Printing Cooperatives 582076 A7 _ B7 V. Description of the invention () Purpose of the invention and: 目的 Purpose of the invention In improving the accuracy of superimposed targets in a semiconductor manufacturing process, superimposed targets include forming a base region in a semiconductor wafer, forming a plurality of first patterns on the base region, and forming a square or a rectangle. The first pattern forms a strip structure, and can form a raised portion or a recessed portion on a film layer. The length and width of the strip pattern are eight to twenty and one to two microns, respectively. Then, a plurality of second patterns are formed along the four edges of the base area. Similarly, the second pattern may be a protruding portion or a concave portion, and the shape of the second pattern may be a square or a rectangle. . The second pattern has a dimension of about 0.5 to 1 micrometer, and the distance between two adjacent second patterns is about 0.3 to 0.8 micrometer. Brief description of the drawings: The above-mentioned content and many advantages of the invention can be easily understood through the following detailed description combined with the attached drawings, among which: The first figure shows the superimposed target in the prior art. The second figure shows another superimposed target in the prior art. The third figure is a cross-sectional view of a semiconductor wafer 'showing the steps of defining contact points and superimposing targets according to the prior art. The fourth figure is a cross-sectional view of a semiconductor wafer 'showing the steps of etching a film layer to form a contact point and superimposing a target according to the prior art. This paper size applies to China Standards (CNS) Λ4 specification (210X 297 mm) Fly--(Please read the precautions on the back before filling this page) 582076 A7-^ ______ 5. Description of the invention () The fifth figure is a cross-sectional view of a semiconductor wafer 'showing the results produced after forming contact points and superimposing targets according to prior art. The sixth view A is a top view of the superimposed target of the present invention. FIG. 6B is a cross-sectional view of the superimposed target of the present invention. Figure 6C is a cross-sectional view of the superimposed target of the present invention. The seventh figure is a cross-sectional view of a semiconductor wafer, showing the steps of forming a photoresist to define a superimposed target area according to the present invention. Figure 8 is a cross-sectional view of a semiconductor wafer showing the steps of forming a superimposed target region according to the present invention. The ninth figure is a cross-sectional view of a semiconductor wafer, showing the formation of a stacked target according to the present invention. Detailed description of the invention: What is disclosed in the present invention is a new superimposed target structure in a semiconductor process. The invention has great effect on the alignment technology in the sub-micron device manufacturing process. Furthermore, the present invention also provides a superimposed target with good steep edges, so as to accurately control the superposition of the superimposed condition. The present invention provides a better contrast and a better superimposed target to facilitate the comparison of the measurement results. For a better contrast effect, a detailed description of the present invention is as follows. Printed by the 4 Chinese * Bid Jujube Bureaus and M Consumer Cooperatives (please read the precautions on the back before filling this page). Generally speaking, superimposed targets are lithographic and uranium engraving processes on a Jfe layer or A pattern is formed on the wafer. As shown in FIG. 6A, a superimposed target 60 that can be used to manufacture integrated circuits is formed according to the present invention. The superimposed target is generally formed on the edge area of the wafer. See, this superimposed target 60 paper size is applicable to Chinese National Standard (CNS) Λ4 condition (210X297 mm) in the Ministry of Good Subjugation M, τ. Printed by Consumer Cooperative ^ 582076 A7 B7 V. Description of the invention ( ) Including a base region 62, formed on a semiconductor wafer. The area can be of any suitable shape, such as a square, rectangle, or other similar shape. Next, a plurality of first patterns 64 (preferably four) are formed on the base region 62, and a square or a rectangle is formed for precise alignment. The first pattern 64 is preferably formed into a stripe structure, and may be a protruding portion or a recessed portion of a film layer in a cross-sectional view, as shown in FIGS. 6B and 6C, respectively. These two diagrams are sectional views of the A-A 'line in the sixth A diagram. The length and width of the bar graph 64 are eight to twenty, one to two microns, respectively. A plurality of second patterns 66 are then formed along the four edges of the base region 62 for precise alignment. The second patterns 66 have a smaller size than the first patterns 64. Similarly, as shown in Figures 6B and 6C, the second pattern 66 may be a protruding portion or a recessed portion of a film, and the shape of the second pattern 66 may be Square or rectangular, the second pattern 66 has a dimension of about 0.5 to 1 micron, and the distance between two adjacent second patterns 66 is about 0.3 to 0.8 micron. The design of the second pattern 66 can ensure overlap The target 60 has a good steep edge, so as to produce a better contrast effect during accurate measurement. Referring next to FIG. 7, a photoresist layer 70 is formed on the top layer of a film layer 72 to define the first and second patterns according to the present invention. As described above, referring to FIG. 8, in the ri-engraving process for forming the first and second patterns, a polymer layer 74 will be formed along the surface of the film layer 72 and the photoresist layer 70. The etching process is continuously performed to etch the film layer 72. The polymer layer 74 and the photoresist layer 70 play a role of a mask here. However, the paper size of this polymer layer is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297). \ ^: Order "^ (Please read the precautions on the back before filling this page) 582076 A7 B7 V. Description of the invention () It will be removed during the etching process, thereby forming a groove portion 76 as the second pattern and having a narrow bottom, and a groove portion 78 as the first pattern, as shown in the ninth figure. The first and second patterns 76 and 78 still have steep edges to facilitate edge detection. In this way, the stacked target can also provide precise alignment for reduced contact processes or other semiconductor processes. Changeable Alternatively, only the second pattern 76 can be used for precise alignment. Those skilled in the art can understand that various future amendments and similar arrangements should be included in the spirit of the attached patent and Within the scope, and its scope should be given the broadest interpretation so as to include all amendments and similar structures. In addition, although the present invention is illustrated as above with a preferred example, it is not intended to limit the spirit and inventive substance of the present invention, End this example. Modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be included in the scope of patent application below (please read the precautions on the back before filling out this Page) Printed on paper of Wugong Cooperative Cooperative, China ’s Ministry of Economic Affairs, China ’s National Standards (CNS) Λ4 specification (210X 297 mm)