TW580673B - Semiconductor integrated circuit, liquid crystal drive apparatus, and liquid crystal display system - Google Patents

Abstract

The present invention is related to a kind of liquid crystal drive apparatus having the differential input circuit. It has a differential amplification section for receiving the differential signal, and the buffer section for generating the output signal based on the output of differential amplification section, such that the signal of display data is inputted through the input circuit, and signal output for driving liquid crystal is conducted according to the display data. A voltage VLCD for driving liquid crystal, which is larger than the power voltage VCC for logic application of operation voltage buffer section, is provided in the differential amplification section of the input circuit, and is disposed in the period without the input of display data, so as to block the waiting function of the operation current of differential amplification section.

Description

580673 A7 B7 V. DESCRIPTION OF THE INVENTION (i) Technical Field The present invention is effectively applied on the semiconductor integrated circuit of a differential circuit having a small amplitude differential signal interface, etc., and further on the use of the liquid crystal driver receiving etc. 2 The semiconductor integrated circuit for supplying power is a particularly useful technique. BACKGROUND ART For example a laptop computer or the like which, driven as a TFT in the display (thin film transistors: thin film transistor) liquid crystal drive data lines of the liquid crystal panel, for example, high-speed input of each pixel 6 yuan of digital display data, at the same time, according to These digital data generate 3 84 output voltages for liquid crystal driving in 64 gray levels. In recent years, in such a liquid crystal driver, an interface for transmitting and receiving digital data at a high speed is a low-amplitude differential signal interface using LVDS (Low Voltage Defferential Signaling) and its derivative specifications. By using such a small-amplitude differential signal interface, it is possible to reduce the power consumption and the electromagnetic interference (EMI) of the input and output signals compared with the CMOS-level interface. FIG. 5 is a MOSFET circuit diagram showing an example of a small-amplitude differential signal interface reviewed by the inventors before the present invention. For example, as shown in FIG. 5, the small-amplitude differential signal interface includes a differential amplifier section 61 that amplifies a differential voltage of an input differential signal, and a differential amplifier section 61 that is upgraded by a quasi-shift circuit 62 a. The output voltage is based on the output voltage, and the driving section 62 that generates the signal on the output side according to the output voltage, and the driving standard of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back first) (Fill in this page)

, Τ Intellectual Cooperative Employees of the 4th Bureau of Wisdom and Finance, Ministry of Economic Affairs, Inno-4-580673 A7 B7 V. Description of Invention (2) (Please read the precautions on the back before filling this page) The load connected to the output side will output the specified amplitude. Signal output section 63 and so on. In the differential amplifier section 61, a common source connected to a pair of differential input MOSFETs Q62 and Q63 is provided, and a constant current MOSFET Q61 for supplying a constant current is supplied. The constant current MOSFET Q61 controls the flow through the differential amplifier section. Mass current of 61. However, in a small-amplitude differential signal interface and a semiconductor chip provided with the interface, it is required to increase the allowable variation of the center voltage of the input differential signal and reduce the power supply voltage for logic supplied to the semiconductor chip to reduce power consumption. . However, in the small amplitude differential signal interface, is provided for the differential amplifier stage 61 is extremely common constant current supply supplied to the drive section 62 so that the output logic section 63 of the power supply voltage VCC with a source of the MOSFET Q61 , a power source voltage to reduce the VCC, a constant current MOSFET Q61 of the gate electrode, source voltage Vgs becomes small. Represented by the following formula (1) Formula drain current saturation region of the MOSFET. 1 = β (W / L) (Vgs-Vth) 2 ...... (1) Intellectual Property Office employee Economic Co-op printed here, / 5 is a constant, W is the gate width, L is the gate length, Zhi Vth is the threshold voltage. From this equation (1), it can also be seen that the voltage Vgs between the gate and source becomes smaller. When the threshold voltage Vth deviates from the reference value due to the process deviation of the MOSFET, this deviation will have a large effect on the current I. Or, in order to make the same current flow, the gate width must be made wider. This paper scale applicable Chinese National Standard (CNS) A4 size (210X29 * 7 mm) 580673 A7 B7 V. invention is described in (3) (Read the back of the precautions to fill out this page) and a lower power supply voltage VCC, differential input potential of the common source MOSFET Q62, Q 6 3 also sum reduced, therefore, since the differential input signal YP, YN variations of the center voltage of the current flowing through the differential amplifier stage 61 is relatively largely varies 'Consumption current and circuit characteristics change, so there is a problem that the allowable wide range of fluctuation of the center voltage of the input differential signals YP and YN cannot be increased. Furthermore, as soon as the potential of the common source of the differential input MOSFETs Q62 and Q63 decreases, the output voltage from the differential amplifier section also becomes low, and there is also a problem that a quasi-shift circuit 62a needs to be provided in the driving section 62 of the subsequent stage. However, since the level shift circuit 62a needs to flow a direct current, the consumption current is increased, so the general design is to make the direct current flowing through the level shift circuit 62a small. However, with this design, the rise of the signal in the quasi-bit shift circuit 6 2 a becomes slower, which causes a problem that the signal delay time becomes longer. From the above, in a semiconductor integrated circuit having an input circuit as shown in FIG. 5, the logic power supply voltage VCC cannot be set too low, and it is understood that there is a problem that the power consumption of the semiconductor chip cannot be reduced. The purpose of the present invention is to print the present invention of an employee consumer cooperative of the Bureau of Intellectual Property of the Ministry of Economic Affairs. The purpose of the present invention is to provide a semiconductor product with a differential circuit that can allow a wide variation in the center voltage of the input differential signal and can reduce the power consumption. Body circuit and liquid crystal driving device. Another object of the present invention is to provide a semiconductor integrated circuit and a liquid crystal driving device capable of widening the allowable width of the center voltage of the input differential signal and reducing the power supply voltage for logic to reduce power consumption. The foregoing and other objects and new features of the present invention will become apparent from the description of the detailed description and the drawings. ^ Paper scale applicable Chinese National Standard (CNS) A4 size (210X297 mm) " '' -6- 580673 A7 ___B7 V. invention is described in (4) reveal the invention (Please read the Notes on the back to fill out this page) Coming to a representative who as described in the present application of the invention to be disclosed, is as follows: that is, a set comprising: a source electrode connected in common to each other one of the differential pair of MOS transistors; and in this connection The constant current MOS transistor between the common source of the differential MOS transistor pair and the power supply voltage terminal amplifies the differential amplifier section of the differential input signal; and according to the output from one of the output terminals of the differential amplifier section The semiconductor integrated circuit of the differential circuit of the output stage that generates the output signal. The supply voltage at the power supply voltage terminal of the differential amplifier stage is higher than the second power stage voltage supplied to the output stage. voltage. According to this device, the second power supply voltage which is larger than the first power supply voltage can increase the gate and source voltage Vgs of the MOS transistor for constant current. It can be understood from the above formula (1) It is possible to reduce the influence of the deviation of the threshold voltage Vth of the transistor on the current, and further reduce the size of the transistor necessary to flow the same current. Printed by the Ministry of Economic Affairs, the Smart Finance 4 Bureau, and the 8th Consumer Cooperative Co., Ltd. The voltage on the drain side of the constant current MOS transistor can also be increased, and the change in the center voltage of the input differential signal can be suppressed. Caused current fluctuation. Therefore, the consumption current and the circuit characteristics do not change due to changes in the center voltage of the input differential signals YP and YN, and a circuit with a wide allowable change in the center voltage can be realized. In addition, the voltage on the drain side of the above-mentioned MOS transistor for constant current can also be increased, which can increase the output voltage from the differential amplifier section. This paper does not need to apply the Chinese National Standard (CNS) A4 standard (210X297mm) 580673 A7 __ _ B7 V. Description of the invention (5) (Please read the precautions on the back before filling this page) To set the quasi-shift circuit in the back section. Therefore, there will be no DC current flowing through the quasi-shift circuit, which can reduce power consumption. At the same time, the portion of the quasi-shift circuit is not needed, which can make the signal rise faster and shorten the signal delay time. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the semiconductor integrated circuit of the present invention is provided with: receiving a pair of differential signals input from the outside, and supplying signals corresponding to the voltage difference of the differential signals to the internal circuit An input circuit; and an internal logic circuit that receives a signal from the input circuit and performs a logical operation; and outputs a signal having an amplitude greater than that of the internal logic circuit to an external output circuit, and supplies the first internal logic circuit with a first A semiconductor integrated circuit having a power supply voltage and a supply voltage to the output circuit, a second power supply voltage that is higher than the first power supply voltage. The input circuit is provided with a differential MOS circuit having a pair of sources connected in common to each other. Crystal; and a constant current MOS transistor connected between a common source of the differential MOS transistor pair and a power supply voltage terminal, amplifying a differential amplification section of a differential input signal; and The voltage output from one of the output terminals generates the output section of the output signal. Supplying the first sub-power supply voltage. According to this device, the second power supply voltage is supplied to the differential amplifier section, so that the allowable width of the center voltage variation of the differential signal input to the input circuit can be widened, and the first power supply voltage for logic can be set. In order to be relatively low, the power consumption due to this can be reduced. In addition, because the second power supply voltage, which is higher than the first power supply voltage, is used as a power supply for high-voltage signal output in the output circuit, it is not necessary to apply Chinese national standards for differential amplification. CNS) A4 specifications (210X297 mm) " ~ 580673 A7 B7 V. Description of the invention (6) paragraph and prepare a new power supply voltage. Moreover, even when a certain direct current is flowing, the size of the transistor of the differential amplifier section can be made small without increasing the chip area. Specifically, it is a semiconductor integrated circuit for driving a liquid crystal panel and outputting a driving voltage for driving a liquid crystal panel based on the digital data by inputting digital data of each pixel formed by a differential signal into the input circuit. As the second power supply voltage, a liquid crystal driving power supply for driving a liquid crystal panel may be used. More specifically, the above-mentioned constant current transistor system is composed of a P-channel MOS transistor in which a bias voltage is applied to a gate and a constant current flows. Moreover, the above-mentioned differential amplification section has a common connection between the sources, and the gates respectively receive two differential input P-channel MOS transistors of a pair of differential signals, and these two differential input P-channels The common source of the MOS transistor is connected to the drain of the P-channel MOS transistor for constant current. Moreover, the liquid crystal driving device of the present invention is provided with a standby means for blocking the operating current flowing through the differential amplifier section in a differential type input circuit for inputting display data. According to this method, blocking unnecessary current flowing through the differential amplifier section can further reduce power consumption. It is desired to release the interruption of the operating current by the above-mentioned standby means based on the external signal of the timing at which the display data of the plurality of display data are continuously transferred, and on the other hand, based on the detection of the completion of the input of the continuously transferred display data, start to use Interruption of the operating current of the standby means. If it is based on this structure, it will not be produced for the control of standby means. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) t-shirt-(Please read the precautions on the back before filling this page) Order Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-9-Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 580673 A7 ____B7 V. Description of the Invention (7) The need to input new signals from the outside, the inputs and outputs exchanged with the outside The signal system can be maintained as it is. It is also possible to perform current control of the differential amplifier section. Also, it is expected that two input signals for each external clock are input in series to the above input circuit. The positive and negative phases of the external clock are two clock input circuits with mutually opposite inputs. Based on the two clock signals input through the two clock input circuits, the two inputs are given. Timing of taking in the signal. According to this structure, even if the conditions such as the manufacturing deviation of the semiconductor, the center voltage of the external clock of the differential, the power supply voltage, and the temperature change to some extent, as the deviation of the clock signal given to the timing of the input signal, Because it is not easily affected, the timing of taking in display data can be easily adjusted. The best form for carrying out the invention is as follows. A suitable embodiment of the invention will be described with reference to the drawings. < First Embodiment > Fig. 1 is a circuit diagram showing an embodiment of a small-amplitude differential signal interface suitable for applying the present invention in detail. In the figure, an example of the appropriate ratio “W / L” of the gate width W (#m) to the gate length (// m) is written next to the MOSFET. The small-amplitude differential signal interface (differential input circuit) of this embodiment is, for example, LVDS (Low) specified by the IEEE (Institute of Electrical and Electronics Engineers: Institute of Electrical and Electronics Engineers). This paper standard applies to the Chinese National Standard (CNS). A4 size (210X 297mm) (Please read the precautions on the back before filling this page)

-10- 580673 A7 B7 V. Description of Invention (8) (Please read the precautions on the back before filling this page)

Voltage Differential Signaling: low-amplitude differential signal interface, or its derivative technology, for example, small-amplitude differential signal interface (eg, 200mV ~ 500mV), in response to the voltage difference of these one pair of small-amplitude differential signals, output a high-level or low-level signal to the internal circuit. As shown in Figure 1, this small-amplitude differential signal interface consists of a pair of differential input MOSFETs Q2 and Q3 and a constant current MOSFET Q1 connected to a common source of the differential input MOSFETs Q2 and Q3. And the differential amplifier section 1 formed by the active load MOSFETs Q4 and Q5 connected to the drains of the differential input MOSFETs Q2 and Q3; and accepting the amplified output of the differential amplifier section 1 according to the output voltage, the output is accurate bit the driving section 2 of the low level signal to the output section 3 is constituted. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In the circuit of this embodiment, a logic power supply voltage VCC (for example, 2.7V to 3.6V) is supplied to the driving section 2 and the buffering section 3. On the other hand, a power supply voltage VLCD (e.g., 6V to 10V) for liquid crystal driving is supplied to the differential amplifier section 1 with a power supply voltage higher than the power supply voltage VCC for logic. Further, the electrode current is applied by a constant current constant voltage circuit and bias current generated by the smell of a MOSFET Q1 control voltage SVGP (e.g. 1.6V~1.8V), by the operation of the MOSFET saturation region, the differential input MOSFET Q2, Q3 supplied to the common bias current source side. In this case, a constant current of MOSFET Q1 gate, source voltage by supply voltage VLCD VgS with the liquid crystal driving voltage becomes larger than the circuit form of FIG. Therefore, it can be understood from the current formula I = yS (W / L) (Vgs-Vth) 2 in the saturation region of the MOSFET mentioned above that even if the paper size of the MOSFET is adapted to the Chinese National Standard (CNS) A4 specification (210X297 mm) ) -11-580673 A7 _B7_ V. Description of the invention (9) (Please read the precautions on the back before filling this page) Process deviation, the threshold voltage Vth deviates from the reference to some extent, and it will not cause too much drain current. Impact. Further, because the voltage Vgs between the gate and the source is relatively large, a desired current 値 can be obtained without increasing the gate width W of the MOSFET. Furthermore, the voltage of the node η 1 to which the source terminals of the differential input MOSFETs Q2 and Q3 are connected also becomes high. Even if the center voltages of the input differential signals YP and YN slightly change, the current flowing through the differential amplifier section 1 is also high. Not much change, the consumption current and circuit characteristics become constant. Therefore, it is possible to widen the allowable width of the fluctuations in the center voltage of the input differential signals YP and YN. In addition, because the voltage of the common source of the differential input MOSFETs Q2 and Q3 becomes high, the high-level voltage outputted to the output node n2 of the differential amplification section 1 can sufficiently turn on the P-channel MOSFET Q6 of the driving section 2 For example, the quasi-shift circuit 62a provided in the small-amplitude differential signal interface shown in FIG. 5 may not be required. Therefore, the part of the quasi-shift circuit is not needed, and the power consumption can be reduced. Moreover, the signal delay can be reduced. It is printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and supplies high power voltage to the differential amplifier section 1. For the reason of VLCD, it is desirable that the MOSFET constituting the differential amplifier section 1 and the driving section 2 that receives the output of the differential amplifier section 1 at the gate are composed of MOSFETs with high withstand voltage (for example, 7V withstand voltage). Next, the characteristics of the small-amplitude differential signal interface will be described quantitatively. Figures 3 and 4 are graphs showing the characteristics of the small-amplitude differential signal interface of Figure 1. Figure 3 is the case where the threshold voltage Vth of the MOSFET is high for both the P-channel type and the N-channel type due to process deviations. 4 lines were formed in the sheet of this low applied China national standard scale (CNS) A4 size (210X297 mm) " 'a -12 - 580673 A7 ___B7 V. invention is described (1〇) case. (Please read the notes on the back before filling this page.) In these charts, the horizontal axis is the voltage 値 of the power supply voltage VLCD that supplies the source of the constant current MOSFET Q 1 and the vertical axis is the voltage flowing through the differential amplifier section χ. DC current 値. In addition, according to each curve, the case where the center voltage Vref of the input differential signal is 0.5V, 1.2V, 2.4V and the case where the wafer temperature is -3 (T_C, 25 t :, 75 ° C. The following is based on the process deviation. The change of characteristics, the change of characteristics due to the center voltage Vref of the input differential signal, the change of characteristics of the power supply voltage VlCD. The amount of change in current 由于 due to process deviation is less than 10%. For example, at a wafer temperature of 25 ° C, Under the condition that the liquid crystal driving voltage VLCD = 8V, and the center voltage of the input differential signal = 1 · 2 V, a current of 6 7 # A can be obtained when the critical threshold voltage vth in FIG. 3 is formed to be high. On the other hand, in FIG. 4 of the threshold V th Zhi who is formed as a low current can be obtained Zhi 7 3 / z A, the difference between their lines of less than 10% of the Zhi. further, known by the curve since the current process deviation Zhi the amount of change in any of the wafer temperature? LCD driving voltage VLCD, the same differential input voltage signal at the center of economic Affairs intellectual property Bureau staff changes in consumer cooperatives print center differential input signal voltage Vref in Figures 3 and Chart of Figure 4 It is shown in solid lines and broken lines and the center line of two points. Know if the same characteristic chart of the same wafer temperature and the critical Zhi voltage V th, almost no bias current is generated depending on the input Zhi center differential signal voltage Vref . further, since a change in current Zhi the supply voltage VLCD (forming the threshold Zhi voltage of FIG. 3 V th is high, the wafer temperature of -3 situation 0 ° C of) the larger context of this paper scale applies China national standard (CNS > A4 size (210X297 mm) ~ -13 - 580673 A7 _____B7_ V. invention is described (Ή) (read precautions to fill out the back of the page), is 26 // A / 5V, in the case of standard (wafer temperature 3〇 ° C), of 20 β A~17 μ A / 5V, the variation amount is small. by this operation done to minimize the current design, the maximum current Zhi does not become extremely large, so that current consumption can be reduced. Figures 6 to 8 show the characteristic curve of the conventional small-amplitude differential signal interface shown in Figure 5. The critical threshold voltage Vth of the MOSFET of Figure 6 is formed at both the P-channel and N-channel, and the power supply voltage VCC The maximum value is 3.6V, Figure 7 The critical threshold voltage Vth and the power supply voltage VCC are both referenced. Figure 8 shows the critical threshold voltage Vth is formed high, and the minimum power supply voltage VCC is 2.7V. In these curves, the horizontal axis represents the constant The gate width W of the current-use MOSFET Q1, and the vertical axis represents the DC current 値 flowing through the differential amplification section 1. In addition, the central voltages Vref of the input differential signals are shown by the curves as 0.5V, 1.2V, and VCC- the case of 1.2V. Printed in the conventional small-amplitude differential signal interface of the employee ’s consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the gate width W of the current MOSFET Q1 is set to 100 // m, and the center voltage Vref of the input differential signal is 0.5 to VCC. when the variation between -1.2V, in the FIG. 6 case, the current is Zhi 563 VA~326μΑ, for variation of 40% or more. Similarly, in the case of FIG. 7, it is 330 // Α ~ 190μΑ, which is more than 40%, and in the case of FIG. 8, it is also 173 y Α ~ 101 " A, and the variation is more than 40%. In addition, when the center voltage of the input differential signal is constant (Vref = 1.2V), other conditions change to the maximum, that is, the threshold voltage of the MOSFET Vth is min, the power supply voltage VCC is max3.6V, the chip The temperature is -30 ° C (point A in Figure 6). The threshold voltage of the MOSFET is changed to Vth is max, the power supply voltage VCC is min2.7V, and the chip temperature is 75 ° C. when) A4 size (210X29 * 7 mm) -14- 580673 A7 B7 ___ V. invention is described in (12) C point) of 484 // A current Zhi changed to 123 // A, decreases. In the case where the current is minimized, a design that can guarantee the operation is performed. The maximum current becomes extremely large, and the current consumption cannot be reduced. In almost the same conditions, a small-amplitude characteristic of the differential WH signal interface of FIG. 1 embodiment of the present study embodiment, the MOSFET threshold voltage Vth of the most Zhi

Small, wafer temperature - 30 ° C (FIG. A 4 of 'point) changes in conditions Zhi voltage Vth of the maximum wafer temperature 75 ° C (FIG. 3 of C as the critical MOSFET's' points) conditions, to know the current Zhi by a 96 // A becomes 54 // A, and the reduction is reduced by 43%. As described above, according to the small-amplitude differential signal interface according to the above embodiment, the differential amplification section 1 is supplied more than the logic power supply voltage VCC. Due to the high liquid crystal drive voltage VLCD, the threshold voltage Vth of the MOSFET due to process deviation, the center voltage Vref of the input differential signal, and the power supply voltage VLCD change slightly even if the current flows through the differential amplifier stage 1 値There is almost no change, and the characteristics of the differential amplifier section 1 can be maintained normally (for example, rise, fall time, output, voltage, etc.). Therefore, it is possible to widen the variation allowable width of the center voltage of the input differential signal. Hereinafter, an example in which the small-amplitude differential signal interface described above is applied to a semiconductor integrated circuit that receives two power supply voltages will be described. Fig. 2 is a block diagram showing the overall configuration of a liquid crystal drive driver including the small-amplitude differential signal interface in the signal input section. The liquid crystal driver 100 of the liquid crystal driving device of this embodiment is, for example, a data line for driving a TFT liquid crystal panel of a display of a notebook computer, and is not particularly limited, and is formed on a semiconductor wafer such as single crystal silicon. This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)

Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-15- 580673 A7 B7 V. Description of the Invention (13) (Please read the precautions on the back before filling this page) The LCD driver 100 of this embodiment has the small amplitude difference mentioned above 1,1 activation signal interface 2 to 10 in the form of high speed small amplitude differential input signal is input from the outside, for example, each pixel of the digital display 6 yuan data DATA00P, DATA00N~DATA22P, when the external DATA22N pulse CLP, CLN . In addition, the data register 104 temporarily retaining the input digital data and the data held in the data register 104 are sequentially shifted by a designated bit, a data latch circuit 1 22 that retains one row of data, and a data register 104 The data is transferred to the designated position of the data latch circuit 1 22. The shift register 1 2 1 is used to convert the digital data in one row of the data latch circuit I 2 i into the analog display of the gray scale of each pixel. the signal D / a converter 123, according to the driving voltage generating Y1~Y384 TFT liquid crystal panel 123 to analog signal by the D / a converter, the output data of the output line buffer 124 and the like. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The driver section 2 and buffer section 3, data register 1 04, shift register 121, and data latch are supplied to the LCD driver 100 from the outside of the chip and used as a small amplitude differential signal interface 1 01 power supply operation of the liquid crystal internal logic circuit 123 and voltage VCC and the like used in a liquid crystal driving voltage Y1~Y3 84 of the driving power supply voltage VLCD. By the liquid crystal driving resistance division circuit (not shown) with the power supply voltage VLCD, is divided into a plurality of gray scale voltage VI~V 10 as the gray scale display, is supplied to the D / A converter 123 and output buffer 124 . The liquid crystal driving power supply voltage VLCD is also supplied to the differential amplifier section 1 of the small-amplitude differential signal interface 101. For example, according to this LCD driver 100, the digital display data DATA00P, DATA00N ~ DATA22P, DATA22N and the external clock CLP, CLN input voltage input from the outside can be made wider and wider. At the same time, this paper scale is applicable to China national standard (CNS) A4 size (210X297 mm) -16- 580673 A7 _ _B7_ five described (14) with the logic power supply voltage VCC to the invention hardly affects the characteristics of small amplitude differential signal interface 1 10, and therefore This power supply voltage VCC can be set low. By this, it is possible to achieve low power consumption of a semiconductor wafer at a higher speed of operation. Although the invention made by the present inventors has been specifically described above based on the embodiments, the present invention is not limited to the above embodiments, and various changes are possible without departing from the scope of the gist. For example, although the specific circuit configuration of the small-amplitude differential signal interface is exemplified, there are various well-known modification examples such as the differential amplifier section. Depending on the differential amplifier section, the circuit configuration of the latter section may be variously modified. Moreover, it is not limited to a MOSFET, and may be formed of a bipolar transistor. The logic power supply voltage VCC, the liquid crystal drive voltage VLCD, and the size of the MOSFET may be appropriately changed as shown in the embodiment. Next, a description will be given of a configuration example in which the power supply voltage supplied to the differential amplifier section 1 of FIG. 1 can be applied to a voltage other than the power supply voltage VLCD for liquid crystal driving. In Fig. 1, although the source terminal of the constant current MOSFET Q1 (Fig. 1) is connected to the power supply voltage VLCD for liquid crystal driving, the case where the source terminal is connected to the second power supply voltage VDD2 will be described below. FIG. 9 is a diagram showing an example of a selection circuit that can select a second power supply voltage VDD2 to be supplied to the small-amplitude differential interface from a plurality of voltages. This embodiment is a suitable one (for example, four from the higher voltage) of the power source voltage VLCD for liquid crystal driving and the gray level power sources V0 to V10 supplied externally for the gray level driving of the liquid crystal. One of them is the second power supply voltage VDD2 of the differential amplifier section 1 supplied to the small-amplitude differential interface 101. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) " '-17- (Please read the precautions on the back before filling this page)

Intellectual Property Office Order Economic Co-op employees printed portion chi bad economy consumption Property Office employee cooperative printed 580673 A7 ___ B7 V. Description of the Invention (15) of the differential amplifier stage, such as the power supply voltage VDD2 1 than the logic supply voltage VCC used If it is too large, the effect can be obtained. On the contrary, if it is too large, it is necessary to excessively increase the withstand voltage of the component, so the power consumption will be slightly larger. Therefore, in this embodiment, the gray-scale power supply VO, VI, which has a potential lower than the power supply voltage VLCD for liquid crystal driving, can be selected as the power supply voltage VDD2 of the differential amplifier section. In the case where the power supply voltage VLCD is too large, the ratio can be applied. Its small gray-scale power supply V0, VI ... The gray-scale power supplies V0 to V 1 0 are divided into a predetermined ratio by resistance division in the liquid crystal driver, thereby generating, for example, a 64X2 gray-scale driving voltage. The driving voltage may be due to the characteristics of the obtained liquid crystal panel differs Zhi, thus, the gray level as the external input power V0~VI 0 'which is the resistance division' can be made of the internal voltage generated in the drive becomes Zhi can vary. Therefore, the gray-scale voltages V0 to V10 are different depending on the applicable system, and in the case of applying to the power supply voltage VDD2 ', one of several gray-scale voltages V0' VI ... can be selected. In the selection circuit of FIG. 9, the power supply line Lvdd2 supplying the power supply voltage VDD2 of the differential amplifier section of the small amplitude differential interface 1 〇1 and the power supply line L00 to which the power supply voltage VLCD and the grayscale voltages V0 to V3 for liquid crystal driving are applied respectively High-withstand voltage switching MOSFETs MSI ~ MS5 are respectively set between L0 and L3, and are connected through the source terminal and the drain terminal thereof. Furthermore, a selection signal is supplied to the gate terminals of these switching MOSFETs MSI to MS5. The selection signal is, for example, an input terminal dedicated to the liquid crystal driver, and is supplied externally through this input terminal. Or set a control register in the LCD driver. According to the setting in this control register, the paper size of the control register applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page )

-18- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 580673 A7 _ _B7 V. Description of Invention (16) Supply. In this way, as the power supply voltage VDD2 of the differential amplifier stage 1, one of the gray-scale voltages V0 to V3 is applied, and the allowable width of the center voltage of the differential input signal can be increased to reduce the power supply voltage VCC for logic. , Also can obtain the speed of the internal circuit and reduce the effect of power consumption. Furthermore, in the liquid crystal driver of this embodiment, in the case where the power supply voltage VLCD for liquid crystal driving is very high, an appropriate one can be selected from the lower grayscale voltages V0 to V3 to be used as the power supply voltage VDD2 of the differential amplifier stage 1. Therefore, it is not necessary to raise the withstand voltage of the components of the differential amplifier section 1 too high, and it is possible to suppress the increase in power consumption caused by the too high lifting. The configuration of the liquid crystal driving power supply voltage VLCD and the grayscale voltages V0 to V3 can be selected as the power supply voltage VDD2. Various configurations can be used, and the configuration is not limited to the configuration using the switching MOSFET. Figures 10 and 11 lines showed in the case of the COF package, by wiring on the wiring film may choose a configuration example of the power supply voltage. This embodiment of the liquid crystal drive system configuration 100 is configured using the package (Chip on Film ·· film wafer) encapsulated in a package as a semiconductor wafer wiring film 52 of the liquid crystal driving device 51 formed on the COF. In this embodiment, the semiconductor wafer 52 setting circuit integrated liquid crystal driver 100 of the second supply voltage connection VDD2 pad G0 outside, by selecting the wiring film wirings suitably 51, the can of the liquid crystal driving power source voltage VLCD and ash by the The power supply voltage VDD2 is selected among the step voltages VO, V: l, for example, as shown in FIG. 10 and FIG. 11, the power supply voltage VDD2 is connected by the wirings H1 and H2 shown by dotted lines formed on the wiring film 51. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

-19-580673 A7 B7 V. Description of the invention (17) One of pads GO and the input pads of the LCD drive power supply voltage VLCD J00〇 or grayscale voltages V0, VI ... One of pads 0, Π ... , One of the liquid crystal driving power supply voltage VLCD and the grayscale voltages VO and V can be selected as the power supply voltage VDD2. Fig. 12 and Fig. 13 show examples in which the second power supply voltage VDD2 can be selected by the wiring pattern of the main limiting method. This embodiment of the semiconductor wafer in the manufacturing process system 52, the wiring pattern is selected by the power supply voltage VDD2. 12 and FIG. 13 camel, for example, by appropriately selecting the wiring patterns Lvdd2 liquid crystal driving power supply line the second supply voltage VDD2 or pad J00 grayscale voltage V0, VI ··· input welding power source voltage of the input pad VLCD As one of the wiring patterns of the pads J0 to J3, one of the liquid crystal driving power supply voltage VLCD and the grayscale voltages VO, VI, ... can be selected as the second power supply voltage VDD2. Fig. 14 shows a configuration example in which a second power source voltage can be selected by cutting a fuse element provided on the semiconductor wafer 52. In this example, for example, a fuse element FS is provided between the power supply line Lvdd2 of the power supply voltage VDD2 and the input pads for the liquid crystal drive power supply voltage VLCD and the grayscale voltages VO, VI, etc., at the wafer stage, or the stage of the semiconductor wafer and the package. does not require cutting the fuse element can be selected by a liquid crystal driving power source voltage VLCD the grayscale voltage VO, _ V · Bu one of the second power supply voltage VDD2. The fuse element FS is cut by a laser, for example, and cut by a predetermined current flowing through a probe. Fig. 15 shows an example of a circuit for generating a second power supply voltage to be supplied to the small-amplitude differential interface 101. This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)

Ministry of Economic Affairs Intellectual Property Office staff eradicating poverty cooperatives printed -20- 580673 A7 B7 V. Description (18) invention (Please read the back of the precautions to fill out this page) In the above embodiment, although the display as supplied to the differential The second power supply voltage VDD2 of the amplifying section 1 directly uses the liquid crystal driving power supply voltage VLCD and the gray-scale voltages VO, VI, etc., but this embodiment uses the liquid crystal driving power supply voltage VLCD to generate a lower voltage than it. 2 Power supply voltage VDD2 is supplied. Various known techniques can be applied to the voltage generating circuit. For example, as shown in FIG. 15, resistors R1 and R2 are used to divide the liquid crystal driving power supply voltage VLCD with a resistor, and the divided potential is output through the voltage output device 40. In FIG. 15, although the second power supply voltage VDD 2 is generated by using the power supply voltage VLCD, the gray-scale voltages V0 and VI may be used instead of the power supply voltage VLCD, and further, they may be used. Generated voltage 0 < Second embodiment > Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This second embodiment is described in the first embodiment where the LCD driver 100 is added to block the input differential when it is not needed Display data DATAP, DAT AN small-amplitude differential interface 1 0 1 of the differential amplifier stage 1 operating current standby function. I.e., in the first embodiment described small amplitude differential of the differential interface 10 is an enlarged supply voltage (VLCD, VDD2) is higher than the supply voltage of the internal circuit (VCC), therefore the segment 1, segment 1 of the differential amplifier Consumption of electricity has become an issue that cannot be ignored. Further, in the liquid crystal system, for example, by liquid crystal drive 8 of the first embodiment, therefore produced 100, the system power consumption becomes large. Therefore, in this embodiment, a description will be given of the liquid crystal driver 100 in which the standby function is added to the differential amplifier section 1 of the first embodiment and the power consumption can be extremely reduced. This paper scale applicable to Chinese National Standard (CNS) A4 size (210X297 male thin) " " -21 - Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed 580673 A7 B7 V. description of the invention (19) Figure 16 lines showed an additional An example of a circuit diagram of a small-amplitude differential interface according to the second embodiment of the standby function is shown. In this small-amplitude differential interface, the main change point of the small-amplitude differential interface 1 0 1 in FIG. 1 is that the current control voltage SVGPD0 for supplying a certain operating current and the second power supply voltage VDD2 can be switched between a constant current bias voltage terminal of the gate of the MOSFET Q1. In addition, a switching MOSFET Q21 is set to forcibly maintain the potential of the output node n4 of the differential amplifier section 1 at a low level when the differential amplifier section 1 is inactive. Switching constant current system configuration with a bias voltage of the MOSFET Q1 of: driving a logic high voltage MOSFET with the purposes of the standby signal STB is converted to the pseudo high-voltage bit shift circuit 5; and a connection / blocking the power supply voltage VDD2 High-withstand-voltage P-channel switch MOSFET Q15 for the gate terminal of constant current MOSFET Q1; and high-withstand-voltage P-channel switch for connecting / blocking the current control voltage SVGPD0 and the gate terminal of MOSFET Q1 for constant current MSOFET Q16; and inverter INV20 for signal inversion. When the difference between the power supply voltage VCC and VDD2 hardly exists, the quasi-bit shift circuit 5 may be omitted. As the basis of the above-described configuration, the standby signal STB is at the low level of the state, the connecting switching current control voltage SVGPD0 MOSFET Q16 is turned on, the switching power supply voltage VDD2 is connected off the MOSFET Q15. By this, the electrode is applied with a constant current of MOSFET Q1 gate current control voltage S VGPD0, section 1 is supplied to the differential amplifier operating current. Furthermore, the switching MOSFET Q21, which is not connected to the output node n4, is turned off and has no effect. This switch MOSFET Q21 is an N-channel type. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling this page)

-22- 580673 A7 B7 V. Description of the Invention (2) The signal input to its gate can turn off the switching MOSFET Q21 even if it is not level-shifted in the quasi-shift circuit 5. On the other hand, the standby signal STB - is set to the high level, the switching power supply voltage VDD2 is connected MOSFET Q15 is turned on, a current control is connected to a closed switch voltage SVGPD0 the MOSFET Q16. As a result, the power supply voltage VDD2 is applied to the gate of the constant current MOSFET Q2 to block the operating current of the differential amplifier stage 1. Furthermore, at this time, the switching MOSFET Q21 of the output node n4 is turned on, and the potential of the output node n4 is forcibly reduced to the ground GND. As a result, the states of the driving section 2 and the buffering section 3 are stable, and the through current is blocked. Although the above-mentioned standby signal STB is omitted, for example, in a liquid crystal driver having the small-amplitude differential interface described above, the timing control circuit for generating an internal timing signal based on a clock signal and a timing pulse input from the outside is used. supply. Fig. 17 is a configuration diagram showing an example of a liquid crystal display system configured by adding a liquid crystal driver having the standby function described above. In the following, in order to make the description easy to understand, the method is changed to refer to the external clock CLK1 of the input data latch circuit 122 in FIG. 2 as the horizontal clock CL1 and the external clocks CLP and CLN of the input differential amplifier 12 This is called the transfer clock CL2. In this figure, 33 is a liquid crystal panel with a thin film transistor (thin film transistor) array and a three-primary color filter capable of color display, and 32 is a gate of the TFT array. Line and horizontal scanning clock CL3 are sequentially driven scanning driver (gate line driver), 34 series of liquid power supply necessary for liquid crystal driving. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) (please read the notes and then fill in the back of this page)

Economic Intellectual Property Office employee printed -23- Economic Co-op Intellectual Property Office employee consumer cooperative printed 580673 A7 B7 V. Description of the Invention (21) crystal driving power supply circuit, 35 a drive system of the source lines of the TFT array of additional standby A liquid crystal driver (source line driver) of a functional liquid crystal driving device: 31 is a controller that supplies display data to the liquid crystal driver 35 and a control device that gives control signals and operation timing to the liquid crystal driver 35 and the scanning driver 32. . Further, the liquid crystal display system is also provided with terminals and wirings for supplying the above-mentioned circuits 31, 32, 34, 35 with a power supply voltage VCC and a ground potential G N D as reference potentials. The liquid crystal driving power supply circuit 34 generates the counter electrode voltage VCOM to the liquid crystal panel 33 and the voltages VGON and VGOFF for the gate line driving of the TFT array of the scan driver 32 and the liquid crystal driving for the liquid crystal driver 35, respectively. Power supply voltage VLCD and gray scale voltages V0 ~ V9. The supply wiring LVS of the voltages VLCD and V0 to V9 output from the power supply circuit 34 are wirings for supplying the respective voltages VLCD and V0 to V9 to each of the liquid crystal drivers 35, and are also provided in the liquid crystal system of the present invention. Therefore, without changing the wiring LVS of the liquid crystal system, the liquid crystal driver (100, 35) of the present invention can be used in the liquid crystal system. -In the liquid crystal display system of this embodiment, a plurality of (for example, eight) liquid crystal drivers 35 are provided in accordance with the number of source lines of the liquid crystal panel 33. In addition, the plurality of liquid crystal drivers 35 respectively drive 3 84 (128 pixels X 3 primary colors) corresponding source lines, and on the other hand, the gates are sequentially driven by the scan driver 32, and the liquid crystal panel 33 All areas are displayed. The liquid crystal driver 35 shown in Fig. 17 can constitute a liquid crystal system even if it is provided as the drive driver 100 of the first embodiment. FIG. 18 is a timing chart illustrating the operation of the liquid crystal display system. In this figure, the paper size applies to the Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page}

-24- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 580673 A7 ____ B7 V. Description of the Invention (22) 'The upper 2 paragraphs and the lower 3 paragraphs are recorded with different time axis scales. And, FRM signal line represents the frame during the hearing of the news box. In the liquid crystal display system of FIG. 17, the controller 31 outputs the horizontal clock CL1 indicating the horizontal period and the transfer clock CL2 to the transfer timing of the display data DATA to each of the liquid crystal drivers 35... In addition to the display data DATA. Wait. Display data DATA to the three primary colors based XI line (1024 pixels) of the data transfer unit, is transferred in a continuous horizontal period. The display data DATA and the transfer clock CL2 each use a differential signal. Furthermore, the display data DATA of one row of the plurality of liquid crystal drivers 35 which are successively transferred from one row of display data DAT A are each taken of three primary colors X128 pixels carried by each driver. The input timing of the display data DATA is notified so that only the corresponding display data DATA start signal EIO is input to each liquid crystal driver 35 at another timing. The start signal EI0 is first output from the controller 31 to the first liquid crystal driver 35. Based on this, the first liquid crystal driver 35 starts to display data. Thereafter, the transfer is continued. Before the liquid crystal driver 35 of the first number completes the input of the data, the liquid crystal driver 35 sends the start signal EIO to the second liquid crystal driver 35. According to the start signal EIO in the second liquid crystal driver 35, the input of the display data is also started. Before the input of the data in charge is completed, the start signal EIO is transmitted to the next LCD driver 35. In addition, this processing is performed by the liquid crystal driver 35 in the first stage to the final stage, and all the display data in one line are divided, and a plurality of liquid crystal drivers 35 are input. Also in Figure 18, the aggregation is input by the controller 31 and each LCD driver 35. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

-25- 580673 A7 B7 V. Description of the invention (23) (Please read the precautions on the back before filling in this page) The start signal EIO issued is recorded as a paragraph, EIOO is output by the controller 31 'EI01 is caused by The EI08 is output by the first liquid crystal driver 35, and the EI08 is output by the last liquid crystal driver 35. The start signal EI08 generated by the last LCD driver 35 has no output destination. Each liquid crystal driver 35 transfers the start signal EIO to the next stage timing. For example, it is obtained by calculating the transfer clock CL2 after the input of the start signal EIO in the timing control circuit built in each liquid crystal driver 35. As shown in FIG. 17 and FIG. 18, the display data DATA is transferred to the liquid crystal driver 35 at the timing of both the rising and falling of the clock signal CL2P. The transfer rate consists of 18 bits of gray-scale data of 6 bits of 1 pixel per 1 clock of 3 primary colors, and 9 bits of one and a half on each side of the 1 clock. The display data DATA transfers the data of 3 primary colors X 1 line during the period of 1 level, and the blank period during which the display data is not transferred is transferred to the next line. In the transfer of the display data DATA of one line, each liquid crystal driver 35 inputs only the display data DATA of the responsible part, and does not perform input processing between other parts of the transfer. Therefore, in the LCD driver 35 of this embodiment, the LCD driver 35 of this embodiment does not perform the input of the display data DATA described above, so that the small-amplitude differential interface 101 is put into a standby mode to reduce power consumption. deal with. Fig. 19 is an example of a timing chart showing the operation timing of the standby process performed by each liquid crystal driver. The standby processing is performed by a timing control circuit built into the liquid crystal driver 35 and utilizing signals necessary for display control of the liquid crystal display system. FIG CL 1 pulse train 19 as restoration of signal from the standby mode with the sheet using the present horizontal dimensions suitable for Chinese National Standard (CNS) A4 size (210X297 mm) -26- 580673 A7 B7 V. (24) The Example illustrates the invention . That is, at the timing control circuit of each liquid crystal driver 35, the horizontal clock CL 1 from the controller 31 is input, and when the rise is detected, the standby signal STB output by the timing control circuit is set to a low level. The standby mode is cancelled. On the other hand, the standby mode is started when the standby control circuit of each liquid crystal driver 35 detects the completion of the input of the display data DATA of each task. The timing control circuit of each liquid crystal driver 35 starts the input of the display data DATA based on the start signal EIO input after the horizontal clock CL1, and the counter clock CL2 is calculated by a counter while the display data D A T A is fetched. Also, parts (3 primary colors XI 28 pixels) of the last data display data DATA is served by the calculation of the counter of Zhi detected by the small-amplitude differential interface 101 is 122 or data latched in the data latch circuit subsequent stage The timing of the latch circuit of the register 104 and the like. Furthermore, based on this detection, the standby signal STB outputted to the small-amplitude differential interface 101 is set to a high level and shifted to the standby mode. FIG. 20 shows another example of the operation timing of the standby process. This example uses the start signal EIO as a signal for restoring from standby mode. That is, the timing control circuit built into each of the liquid crystal drivers 35 makes the standby signal STB supplied to the small-amplitude differential interface 101 to a low level when the rising of the start signal EIO is detected, and the standby mode is released. The start of the standby mode is the same as the example of FIG. 19. As described above, as in the liquid crystal driver 35 and the liquid crystal display system according to this second embodiment, during the period when the display data DATA is not transmitted in each liquid crystal driver, the differential amplification section 1 of the small amplitude differential interface 1 0 1 this paper was operating current scale applicable Chinese national standard (CNS) A4 size (210X 297 mm) (please read the back of the precautions to fill out this page) • custom installation · Ministry of economic Affairs intellectual property Office employees consumer cooperatives printed -27 - 580673 A7 B7 V. Description of the invention (25) blocked, therefore, the differential amplifier supply voltage (VDD2) of paragraph 1 even higher than the supply voltage of the internal circuit (the VCC), the power consumption can be more reduced. (Please read the precautions on the back before filling in this page.) In the example of Figure 19 and Figure 20, the latter can generate standby mode more efficiently and reduce the power consumption. However, when the start signal EIO is input, In the case where the period from when the input of the display data DATA is started is short, the standby release of the small-amplitude differential interface 1 01 may be too late, so in that case, the example of FIG. 19 can be applied. < Third embodiment > Fig. 21 is a circuit diagram of an input section for displaying data and transferring a clock in the liquid crystal driver of the third embodiment. The third embodiment is an improvement of the input circuit of the transfer clock CL 2 to the transfer timing of the display data DATA in the liquid crystal driver shown in the first and second embodiments. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the differential transfer clock CL2 (the positive phase side is shown as CL2P and the negative phase side is shown as CL2N) using a differential amplifier, based on the characteristics of the differential amplifier , CL2 easy to make by the pulse rise time of the differential amplifying section transfers the same and fall time, based on conditions of the central differential voltage signal, the power supply voltage, temperature or the like, the deviation is generated at these times. Therefore, the delay time of the rising signal (hereinafter referred to as the rising delay) and the falling time of the falling signal (hereinafter referred to as the falling delay) are shifted by the clock CL2 of the differential amplifier. Therefore, the clock CL2 is transmitted with one differential amplifier input, and the two ends of this input clock are used to perform two differential display clocks at one clock. The paper size of the capital paper applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm) -28- 580673 A7 B7 V. Description of the invention (26) (Please read the precautions on the back before filling this page) DATA (the positive phase side is DATAP, the negative phase side is DATAN) In some cases, for example, when the center voltages of the transfer clocks CL2P and CL2N inputted from the outside are greatly deviated, the clock distortion of the transfer clock CL2 may become large, and the display data DATA may not be fetched correctly. Moreover, in order to avoid this problem, in the case of the above-mentioned configuration, only the conditions of the signal CL of the transfer clock CL2 and the waveform of the display data DATA input from the outside can be strictly specified. Therefore, in the liquid crystal driver of the third embodiment, as shown in FIG. 21, the two differential amplifiers 12, 13 having the input transfer clock CL2 are provided, and the two differential amplifiers 1 and 2 are transmitted through the two differential amplifiers. And when the two systems are entered,

Clock signal CC3, CC4, shown in the latch circuits 15 and 16 latch data DATA DATA square display data based adjustment input of the delay circuit 14 through small-amplitude differential interface 1〇1 differential amplifier 11 and the timing. Further, the latch circuit 15, 16 is provided in the data lines constituting the register 104 after a small amplitude differential interface section 101 (FIG. 2). -The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed one of the two differential amplifiers 12 and 13. The differential amplifier 12 is input to the positive-phase input terminal of the positive-phase transfer clock CL2P, and the negative-phase input. Terminal input negative phase transfer clock CL2N. The differential amplifier 13 on the other side inputs a negative-phase transfer clock CL2N at its positive-phase input terminal and a positive-phase transfer clock CL2P at its negative-phase input terminal. Further, one of the latch circuits 15 to 12 by the rise of the clock signal of the differential amplifier CC4 taken into the display data DATA, the other of the latch circuit 16 is taken by the rising of the clock 13 to the differential amplifier of the signal CC3 Input display data This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) -29- 580673 A7 _B7 V. Description of the invention (27) DATA. (Please read the precautions on the back before filling in this page.) Figure 2 2 shows the waveforms of the display data of the circuit in Figure 21 and the delay amount of the transfer clock. According to the above configuration as the FIG. 22 (a) shown in camel, although the rise delay and fall delay of the differential amplifier 12, 13 varies, but the differential amplifier of the n-1 2, 3 and the negative-phase input terminal The phase input terminals are reversely connected to each other. The rising timing T3 of the signal CC3 after passing the differential amplifier 13 and the rising timing T4 of the signal CC4 after passing the differential amplifier 14 are respectively decreased by the transfer clock CL2P (= signal CC1). The timings T1 and T2 are added to the timings of the rise delays DF and DR of the differential amplifiers 12 and 13, respectively. Therefore, according to the input method of the transfer clock CL2 according to this third embodiment, the rising of the signal CC4 giving the latch timing to the latch circuit 15 and the rising edge of the signal CC3 giving the latch timing to the latch circuit 16 occur The intervals are equal, so it is not easy to get the display data DATA. Therefore, conditions such as the clock CL2 of the differential transmission and the center voltage of the differential display data DATA can be relaxed, and further, the transmission of the display data DATA can be performed at a higher speed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the invention made by the present inventors has been described in detail based on the embodiments, the present invention is not limited to the above-mentioned first to third embodiments, without departing from the scope of the invention. , There are various possible changes. For example, in the third embodiment, although the horizontal clock CL 1 and the start signal EIO are used to release the standby mode, other signals used in the system that know the start of the transfer of continuous display data can be used. Release the standby mode. In addition, regarding the start of the standby mode, the Chinese paper standard (CNS) A4 (210X: 297 mm) is applied to the paper size. -30- 580673 A7 B7 V. Description of the invention (28) When the signal is transmitted, the signal can also be used to start the standby mode. In addition, the standby signal itself can be input from outside the chip, and the standby signal is supplied to each liquid crystal driver by a controller or the like that controls the timing of each block in the liquid crystal display system. In the standby mode, the configuration of blocking the operating current of the differential amplifier section of the small-amplitude differential interface 101 is shown in the third embodiment as the configuration of the bias voltage of the switching current MOSFET Q1. There are various ways to configure the power supply voltage VDD2. In the second embodiment, the standby mode is described for each horizontal period. For example, in the horizontal period when the display data is not transferred first and last during the horizontal period, it may be changed. These horizontal periods are all controlled as standby modes. In addition, the standby mode is generated only at the beginning and the end of the frame period, and the standby mode is released during the horizontal period in which the display data is transferred. This configuration can also reduce the power consumption compared to the conventional configuration. Moreover, in the input circuit of the timing and pulse CL2 of the third embodiment, the two differential amplifiers of the input and timing clock CL2 need not both be made into the same circuit configuration, as long as the rising delay or the falling delay is equal, the circuit configuration may be Free form. In addition, in the first embodiment, in order to stably acquire the differential display data DATA, the operating voltage of the differential amplification section 1 is made smaller than the operating voltage of the driving section 2 and the buffering section 3 of the latter stage in the small amplitude differential interface 101. The VCC is also large. Others, instead of making the operating voltage larger, use MOSFETs with low critical voltages in the components of the differential amplifying section 1, and the driving section 2 and the buffer section 3 in the latter section. This paper applies Chinese national standards (CNS) A4 size (210X297mm) (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

-31-580673 A7 B7 V. Description of the invention (29) (Please read the precautions on the back before filling this page) The components use a high critical voltage MOSFET to form a small amplitude differential interface 1 0 1. The same effect can be obtained in the case of the power supply, and the stable access of the display data DATA can be performed. If the simple g demonstrates the effect obtained by the representative of the inventions not disclosed in this application, it is as follows: That is, according to the present invention, in a differential circuit such as a small-amplitude differential signal interface, it is possible to The allowable width of the center voltage of the input differential signal is widened, and the effect of power consumption can be reduced. Furthermore, in semiconductor integrated circuits having a small-amplitude differential signal interface, it is possible to widen the variation allowable width of the input differential signal and reduce the power supply voltage for logic to reduce power consumption. In addition, with the standby function, during the blank period when the display data is not transferred, the operating current flowing through the differential amplification section of the small amplitude differential interface can be blocked, which can further reduce the power consumption of the liquid crystal drive circuit and the consumption of the liquid crystal system. electric power. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and by using the horizontal clock and start signal to know the continuous transfer of the display data, the standby function can be automatically released; The function of automatically starting the standby function does not need to set a new external signal for the standby function. It has the effect that the previous system can be used as it is. Furthermore, in the input interface where data is input twice with one clock using both edges of the differential clock signal, the two differential amplifiers have positive and negative input terminals opposite to each other. Input clock signal 'Use these clock signals to obtain data, which can reduce the clock distortion and take it stably. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -32- 580673 Intellectual Property Bureau, Ministry of Economic Affairs Printed by employees' consumer cooperatives A7 B7 V. Description of invention (30) Enter the information. Furthermore, it eases the waveform conditions of the differential clock signal and data signal, and enables higher-speed data transfer. Industrial Applicability In the above description, although the liquid crystal driver in the field of use of the background of the present invention is mainly described as an invention made by the inventor, the present invention is not limited to this. For example, it can be widely used Chip microcomputer and DSP (Digital Signal Processor: digital signal processor) have a semiconductor integrated circuit that has a small amplitude differential signal interface and accepts the supply of two power supply voltages for the internal logic circuit and interface. Brief Description of the Drawings Figure 1 is a circuit diagram showing an embodiment of a small-amplitude differential signal interface to which the present invention is suitable. Fig. 2 is a block diagram showing the overall configuration of a liquid crystal driver having a small-amplitude differential signal interface according to the present invention. _ Fig. 3 is a characteristic diagram of the small amplitude differential signal interface of Fig. 1 when the critical 値 voltage Vth of the MOSFET is high in both the P channel and the N channel. FIG 4 based MOSFET threshold voltage Vth of the Zhi N-channel and P-channel is formed for the characteristic table of FIG case of small amplitude low differential signal interface 1. Figure 5 is a circuit diagram showing one case of the review by the present inventors that small amplitude differential signal interface. Figure 6 is a MOSFET threshold voltage Vth Zhi in the P-channel and the N channel is formed as a characteristic graph of FIG case of low amplitude differential signals of small interface 5. This paper size applies to China National Standard (CNS) A4 (210X29? Mm) (Please read the precautions on the back before filling this page)

-33- economic Intellectual Property Office employee consumer cooperative printed 580673 A7 B7 V. Description of the Invention (31) in FIG. 7 Zhi-based threshold voltage Vth MOSFET of the P-channel and N-channel case is formed as a small reference Zhi of FIG. 5 Characteristic chart of the amplitude differential signal interface. FIG 8 lines of MOSFET threshold voltage Vth Zhi in the P-channel and the N channel is formed as a characteristic graph of FIG case of small amplitude differential signal high interface 5. Fig. 9 is a diagram showing a configuration example of a second power supply voltage that can be selected from a plurality of pluralities to be supplied to a small-amplitude differential signal interface. Fig. 10 is a plan view showing a C0F package in which a second power supply voltage can be selected by wiring on C0F, and the second power supply voltage selects a liquid crystal driving voltage VLCD. FIG. 11 is a state diagram showing the voltage for the second power supply voltage selection gray-scale driving in the COF package of FIG. Fig. 12 shows a schematic diagram of a semiconductor wafer in which the second power supply voltage configuration example can be selected in the main limitation of the aluminum wiring, and the second power supply voltage selection is a state of the liquid crystal driving voltage VLCD. Fig. 13 is a diagram showing a state in which the second power supply voltage selects a voltage for gray-scale driving in the semiconductor wafer of Fig. 12. Fig. 14 is a schematic diagram showing a semiconductor wafer in which a fuse is provided on the semiconductor wafer so that a second power supply voltage can be selected. Fig. 15 is a circuit diagram showing an example of a second power voltage generating circuit supplied to a small-amplitude differential signal interface. Fig. 16 is a circuit diagram showing a small-amplitude differential signal interface according to a third embodiment of the additional standby function. Figure Π shows the liquid crystal driver using the additional standby function. This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page)

-34- 580673 A7 B7 V. invention described configuration diagram showing an example of the system (32) liquid crystal display. FIG. 18 is a timing chart illustrating the operation of the liquid crystal display system of FIG. 17. FIG. Fig. 19 is a timing chart showing an example of an operation timing of a standby process performed by each liquid crystal driver. Fig. 20 is a timing chart showing another example of the operation timing of the standby processing performed by each liquid crystal driver. Fig. 21 is a circuit diagram showing an input portion for displaying data and transferring a clock in the liquid crystal driver of the embodiment. Fig. 22 is a waveform diagram showing the relationship between the display data and the transfer clock in the circuit of Fig. 21; Comparison of main components (please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 Differential amplifier section 2 Drive section 3 Output section 11, 12, 13 Differential amplifier 14 Delay circuit i 5 , 16 latch circuit 31 drives the scan controller 32 3 3 TFT color liquid crystal panel 34. The liquid crystal driving power supply circuit 35 drives the liquid crystal driver 100 applies the present paper China national standard scale (CNS) A4 size (210X297 mm) -35- 580673 A7 B7 V. Description of the invention (33) 101 104 small amplitude differential interface data register 121 of the shift register 122 data latch circuit 123 D / A converter 124 output buffers (read the back side of the page and then fill precautions ) Ministry of economic Affairs intellectual property Office workers consumer cooperatives 8 ¾ printed in this paper scale applicable Chinese national standard (CNS) A4 size (210X297 mm) -36-

Claims (1)

580673 A8 B8 C8 D8 6. Application for Patent Scope Annex 2 Patent Application No. 901 28937 Amendment to Chinese Patent Application Scope (Please read the notes on the back before filling out this page) Amendment on March 3, 1992 1. A semiconductor product circuits, which system is provided comprising: a source electrode connected in common to each other one of the differential MOS transistor is connected to the MOS transistor of the differential current between the source electrode common power supply voltage terminal and the MOS transistor, A semiconductor integrated circuit of a differential type circuit that amplifies a differential input signal and a differential circuit that generates an output signal based on a voltage output from an output terminal of one of the differential amplification sections, which is characterized by: ··· The supply voltage to the power supply voltage terminal of the differential amplifier section is a second power supply voltage which is higher than the first power supply voltage supplied to the output section. '' Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2-a semiconductor integrated circuit, which is provided with: a pair of differential signals input from the outside; An input circuit for an output signal of a voltage difference; and an internal logic circuit that receives a signal from the input circuit to perform a logic operation; and an output circuit for an external output signal having a larger amplitude than the signal of the internal logic circuit, for the above internal A semiconductor integrated circuit that supplies a first power supply voltage to a logic circuit and supplies a second power supply voltage that is higher than the first power supply voltage to the output circuit, wherein the input circuit includes: Connect a pair of differential MOS transistors with a current transistor connected between the common source of the differential MOS transistor pair and the power supply voltage terminal to amplify the differential amplification section of the differential input signal; and The voltage output from one of the output terminals of the differential amplifier section generates the output section of the output signal. Zhang applicable China National Standard Scale (CNS) A4 size (210X297 mm) 580673 ABICD six, patent applications range of the differential amplifier stage power supply voltage terminal for supplying the second power supply voltage. 3. The patent application scope of paragraph 2 of the semiconductor integrated circuit according to of that system one kind of digital data signal to each pixel formed by the differential signal when the input circuit is input, and, according to the digital data signal from said output circuit The semiconductor integrated circuit for liquid crystal driving that outputs a driving voltage for driving a liquid crystal panel uses the liquid crystal driving power supply voltage for driving the liquid crystal panel as the second power supply voltage. 4. The semiconductor integrated circuit as described in item 2 or 3 of the scope of the patent application, wherein the current transistor system is a first P-channel MOS transistor that applies a bias voltage to the gate. 5. The semiconductor integrated circuit as described in item 4 of the scope of patent application, wherein the differential MOS transistor system of the above pair has a second P-channel MOS that receives one of the differential signals of the pair at the gate, respectively. The common source of these second P-channel MOS transistors is connected to the drain of the first P-channel MOS transistor. 6 · A liquid crystal display system, characterized in that: it has a differential input circuit that is provided with a differential amplification section that accepts a differential signal and an output section that generates an output signal based on the output of the differential amplification section, and passes through the input circuit data input display, a liquid crystal display according to the driving output data, while the operating voltage is provided as the differential amplifier stages of the supply operation of the output section drive ratio of the larger voltage supplied to the liquid crystal driving voltage of the liquid crystal device; and based on A liquid crystal panel for displaying the liquid crystal driving output of the liquid crystal driving device, and a control device for outputting display data and signals for operation control to the liquid crystal driving device. This paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the back of the precautions to fill out this page), 1T Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed -2-580673 Ministry of Economic Affairs intellectual property Office employee consumer cooperative printed A8 B8 C8 D8 six, patent range 7.1 - kinds of liquid crystal drive device, which system is provided having a differential receiving amplifier stage with differential signals based on the output of the differential amplifier stages to generate an output the differential signal output section of the input circuit, the input circuit through which the input display data, while driving the liquid crystal device of the liquid crystal drive output signals according to the display data, wherein: the differential amplifier section is provided to block the fluid Standby means through the operating current of the differential amplification section. 8. The liquid crystal driving device according to item 7 in the scope of the patent application, wherein the operating voltage supplied to the differential amplifier section is higher than the operating voltage for the liquid crystal driving section which is higher than the operating voltage supplied to the output / segment. 9. The liquid crystal driving device according to item 8 in the scope of the patent application, wherein the liquid crystal driving voltage supplied to the differential amplification section is a gray scale power source inputted externally in order to generate a gray scale driving voltage for the gray scale driving liquid crystal panel. 10. The liquid crystal driving device as described in any one of items 7 to 9 of the scope of patent application, wherein a common connection between the source and the friend is set in the differential amplification section, and a pair of differential signals is received at the smell pole respectively. two differential input MOS transistor; and the two differential input MOS transistor of the common source lines connected to the drain, the source electrode of the current operating voltage supplied to the MOS transistor, the standby switching means is applied based A means for biasing the gate of the MOS transistor to the above current. 11. The scope of the patent in any one of the liquid crystal drive apparatus described in item 7~9, wherein the external signal includes a timing according to the display data of the display of a plurality of successive transfer, blocking is released by means of the operation of the standby current ; on the other hand, according to the continuous transfer of display data input over the subject of this paper scale Bu with the Chinese national standards (CNS) A4 size (210X297 mm) --- (please read the back of the precautions to fill out this page) -3 - 580673 A8 B8 C8 ____D8 six, patented measuring range, the start control means for interrupting the operation by the standby current means the o (read precautions to fill out the back of the page) 12. the scope of the patent application The liquid crystal driving device described in any one of items 7 to 9 includes a clock input circuit for inputting two differential external clocks. In one of the two clock input circuits, the external clock The positive phase signal input of the pulse is the positive phase input terminal, and the negative phase signal is input to the negative phase input terminal. In the other clock input circuit, the negative phase signal of the external clock is input to the positive phase. The input terminal and the positive-phase signal are input to the negative-phase input terminal. On the other hand, each of the external clocks has two input signals input in series and the aforementioned input circuit, and the timing of fetching the two input signals They are given based on the two clock signals input through the two clock input circuits. 13 · The liquid crystal driving device described in item 12 of the scope of patent application, which includes the above-mentioned two inputs in which each of the latches is input in series in an external clock. · One of the signals is the first latch and the other latch. 2 clock signal input of each latch circuit of the timing system according to the second latch, the first latch and the second latch of the input clock are transmitted through the imparting of the two. Economic Intellectual Property Office employee printed consumer cooperative application 14. The liquid crystal drive apparatus according to item 12 patentable scope of which two clock signal input through the input circuit of the two clock is increased or decreased by the One of them gives the opportunity. 15 · A liquid crystal display system, comprising: a liquid crystal panel having a plurality of source lines and a plurality of gate lines; and a plurality of source lines connected to the plurality of source lines, which are to be displayed on the above-mentioned liquid crystal surface based on the paper size Applicable to China National Standard (CNS) A4 specification (210X297 mm) 580673 A8 B8 C8 __ D8 VI. Display data of the patent application board to generate source line drivers that selectively drive the driving signals for the above source lines; and (Please read the precautions on the back before filling in this page) The gate line drivers connected to the plurality of gate lines, and sequentially scanning the gate line drivers; and the LCD panel, the source line driver, and the gate The line driver is connected to supply a power supply circuit that should supply the driving power potential of the liquid crystal panel, the source line driver, and the gate line driver; and the source line driver and the gate line driver are connected to the source line. When the driver supplies the display data, and at the same time supplies the source and electrode line drivers and the gate line driver Controller for machine control signals; and terminals for supplying the reference potential to the source line driver and the gate line driver; the controller supplies the above-mentioned display data in a differential form to the source line driver, the Intellectual Property Bureau of the Ministry of Economic Affairs The employee consumer cooperative printed the above-mentioned source line driver with a differential input circuit that accepts the above-mentioned differential data display; and a data latch circuit that latches the output of the differential input circuit; and that generates the driving signal. Output circuit; the power supply potential of the differential input circuit of the source line driver uses the power supply potential selected by the drive power supply potential, and the power supply potential of the data latch circuit of the source line driver uses the power supply potential selected by the terminals Supply reference potential. Item 16. The liquid crystal 15 described in the application range of the display system of the patent, wherein the differential input circuit of the power supply potential line than the above-described private information sheet latch circuit scale applies China National Standard (CNS) A4 size (210X297 PCT Si) - 5- 580673 ABCD 6. The scope of patent application is still high. (Please read the precautions on the back before filling this page) 17 · If the liquid crystal display system described in item 16 of the scope of patent application, the above differential input circuit has: a gate and A pair of common MOS transistors; and a source having a drain connected to the common source and a source supplied with a power supply potential selected by the driving power supply potential and a source supplied with a bias potential Gate current source MOS transistor. 18 · The liquid crystal display system described in item 17 of the scope of the patent application, wherein the source line driver further has a standby control circuit, and the gate of the current source MOS transistor is controlled by the standby control circuit, and is selectively The ground is supplied with the above-mentioned bias potential. 19 · The liquid crystal display system described in item 18 of the scope of patent application, wherein the standby control circuit is within the timing signal supplied from the controller, and is activated based on a signal indicating a level period of the liquid crystal panel. The bias potential is supplied to the gate of the current source MOS transistor. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 20. A liquid crystal display system, which is characterized by: A liquid crystal panel having a plurality of source lines and a plurality of gate lines, and a plurality of source lines connected to the plurality of source lines, which are used to selectively drive the source lines according to display data to be displayed on the liquid crystal panel. a plurality of drive signals of the source line driver; and connected to the gate line of the plurality of sequentially scanning the gate lines of the gate of the paper sheet suitable for China national standard scale (CNS) A4 size (210 X 297 mm) - 6-580673 A8 B8 C8 D8 VI. Patent application polar line driver; and (Please read the precautions on the back before filling this page) Connect with the above LCD panel, the above multiple source line driver and the above gate line driver, Supply a power supply circuit that supplies the liquid crystal panel, the plurality of source line drivers, and the driving line potential of the gate line driver; and the plurality of source line drivers and the gate line driver connected to the plurality of sources The electrode line driver supplies the display data, and simultaneously drives the plurality of source line drivers and the gate line driver. A controller for supplying timing control signals; and a terminal for supplying a reference potential to the plurality of source line drivers and the gate line driver; the controller supplying the display data in a differential form to the plurality of source line drivers, Each of the plurality of source line drivers has a differential input circuit that receives the differential form. Display data; and a data latch circuit that latches the output of the differential input circuit; and an output circuit that generates the drive signal. f The power supply potential of the differential input circuit printed by the plurality of source line drivers of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs uses a power source potential selected by the driving power source potential. The power supply potential of the data latch circuit uses a reference potential supplied from the terminal. 21. The liquid crystal display system according to item 20 of the scope of patent application, wherein the power supply potential of the differential input circuit is higher than the power supply potential of the data latch circuit. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 580673 A8 B8 C8 D8 6. Application for patent scope 22. For the liquid crystal display system described in item 21 of the scope of patent application, the above differential input circuit has: A differential MOS transistor having a pair of a gate and a common source that respectively receive the display data in the differential form; and a drain connected to the common source and a source selected to be selected by the driving power source potential A source potential of a power source potential and a current source MOS transistor supplied with a bias potential potential gate. 23. The liquid crystal display system described in item 22 of the scope of patent application, wherein each of the plurality of source line drivers further has a standby control circuit, the gate of the current source MOS transistor is controlled by the standby control circuit, The bias potential is selectively supplied. 24. The liquid crystal display system described in item 23 of the scope of patent application, wherein the standby control circuit is among the above-mentioned timing signals provided by the controller, and responds to activation of signals indicating a level of the liquid crystal panel, The bias voltage is supplied to the gate of the current source MOS transistor, and the activation of the start signal in the timing signal supplied by the controller is activated to block the gate of the current source MOS transistor. The above-mentioned bias potential is supplied. 25. The liquid crystal display system described in item 23 of the scope of the patent application, wherein the standby control circuit is among the above-mentioned timing signals provided by the controller, and responds to activation of the corresponding start signal to the current source M. The gate of the S transistor supplies the above-mentioned bias potential, and within the above-mentioned timing signal provided by the above-mentioned controller, responds to the next paper standard applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) ( please read the back of the precautions to fill out this page), π Qin · Ministry of economic Affairs intellectual property Office employees consumer cooperatives printed -8--580673 Ministry of economic Affairs intellectual property Office employees consumer cooperatives printed A8 B8 C8 D8 six patented range segment The activation of the start signal of the source line driver blocks the supply of the bias potential to the gate of the current source MOS transistor. 26. A liquid crystal driving device, which is characterized by having two clock input circuits for inputting differential external clocks. In the differential input circuit in one of these clock input circuits, Yu Zheng The phase input terminal inputs the positive phase signal of the external clock, and the negative phase input terminal inputs the negative phase signal. In the differential input circuit of the other clock input circuit, the positive phase input terminal inputs the negative of the external clock. Phase signal, input the positive phase signal at the negative phase input terminal, and on the other hand a differential type that is set to receive the differential amplification of the differential signal and generate an output signal based on the output of the differential amplification section. In the input circuit, two input signals are input in series for each of the external clocks described above, and the processing time of these two input signals lies in the differential input circuit in one of the clock input circuits. The output and the differential input circuit in the other clock input circuit are separately provided and constituted. 27. For example, the liquid crystal driving device in the scope of application for patent No. 26, wherein the first latch and the latch having one of the above two input signals serially input and output are provided for each external clock. each time latches one of the second latch, these first and second latches of the latch, by 2 to the clock signal input of the two input signals of the clock, wherein the clock in accordance with one of the The clock signal output from the differential input circuit in the input circuit and the clock signal output from the differential input circuit in the other clock input circuit are provided separately. 28. If you apply for a liquid crystal driving device in the scope of the patent application No. 26 or No. 27, this paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) -9 -580673 A8 B8 C8 ___ D8 6. The scope of patent application Among them, the two clock signals inputted by the two clock input circuits mentioned above are constituted by supplying either of the rising or falling signals to the above time. . 29. - kind of liquid crystal display system having a system is provided wherein receiving the differential signals from the differential amplifier section and the input circuit of the output stage of the differential output signals, and the processing from the input of the differential amplification circuit according to the generating section A data register for output signals. The above data registers are provided with two clock input circuits for inputting differential external clocks. Among the differential input circuits in one of these clock input circuits, Yu Zheng The phase input terminal inputs the positive phase signal of the external clock, and the negative phase input terminal inputs the negative phase signal. In the differential input circuit of the other clock input circuit, the positive phase input terminal inputs the negative of the external clock. Phase signal, input the positive phase signal at the negative phase input terminal, and the processing time of the output signal is processed according to the two clock signals input through the two clock input circuits, and temporarily stored according to the data. display data input, an output for driving the above-described liquid crystal drive apparatus of the liquid crystal driving output liquid crystal drive-output information according to the display, the liquid crystal display panel And the control device for outputting the liquid crystal driving device as a signal for displaying operation data or motion control. 30. A liquid crystal display system, which is characterized by having a liquid crystal panel having a plurality of source lines and a plurality of gate lines, and a combination of the plurality of source lines, based on display data to be displayed on the liquid crystal panel. Become a source line driver that selectively drives the driving signals of the source lines, and a gate line driver that scans the gate lines sequentially in combination with the plurality of gate lines. This paper standard applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page), printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -10-580673 ABCD VI. Patent Application Scope (Please read the notes on the back first Please fill in this page again) and a power supply circuit that combines the liquid crystal panel, the source line driver, and the smell line driver to supply the driving power supply potential to the liquid crystal panel, the source line driver, and the gate line driver. And combined with the source line driver and the gate line driver, and supplying the display to the source line driver. At the same time as the data, the controller that supplies a time control signal to the source line driver and the gate line driver and the time signal includes a differential clock for supplying the source line driver and the gate line driver. Reference potential terminal; The controller is to supply the display data in the differential form to the source line driver, and the source line driver has a differential input circuit that receives the display data in the differential form, and a latch. The data latch circuit that locks the output of the differential input circuit, and the output circuit that generates the drive signal described above, printed by the Qin. Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economic Affairs, the data latch circuit has the clock to input the differential Of the two clock input circuits, in the differential input circuits of one of the clock input circuits, the positive phase signal of the external clock is input to the positive phase input terminal, and the negative phase signal is input to the negative phase input terminal. In the differential input circuit in the other clock input circuit, an external clock is input to the non-inverting input terminal Negative-phase signals. Positive-phase signals are input to the negative-phase input terminals. The processing time of the output signals is processed according to the two clock signals input through the two clock input circuits. According to the clock control signals, display data to the output circuit, this paper scale applicable Chinese national standard (CNS) A4 size (210X297 mm) -11--580673 Ministry of economic Affairs intellectual property Office staff consumer cooperatives printed A8 B8 C8 D8 six patented range The power supply circuit of the data latch circuit of the source line driver uses a reference potential supplied from the terminal. 31. Patent application range of the liquid crystal display system of 30, wherein, in the above-described data latch circuit comprising a latch wherein one of the two external input signals for each one of the clock, of the serial input and output of the The first latch and the second latch on the other side. The latch times of the first latch and the second latch are at the two clocks input by the two clock input signals. The signal is based on the clock signal output from the differential input circuit in one of the clock input circuits and the clock signal output from the differential input circuit / circuit in the other clock input circuit. Supply. 32. If the liquid crystal display system of the 30th or 31st scope of the patent application is applied for, the two clock signals inputted by the two clock input circuits mentioned above are both by rising or falling, It is constituted by supplying the above time. 33. A liquid crystal display system, comprising a liquid crystal panel having a plurality of source lines and a plurality of gate lines, and a combination of the plurality of source lines, based on display data to be displayed on the liquid crystal panel. Becoming a source line driver for selectively driving the source line driving signal, and a gate line driver combined with the plurality of gate lines, sequentially scanning the gate line driver, and combining the liquid crystal panel and the source line driver means and the gate line driver supplies required to the liquid crystal panel, the source line driver and said gate line driver power supply circuit of the drive power supply potential, and binding to a source of the plurality of line drivers and said gate line this paper applies the drive-scale Chinese national standard (CNS) A4 size (210X297 mm) (please read the back of the precautions to fill out this page) -12- 580673 A8 B8 C8 _ D8 six patented device range, to the source While the polar line driver supplies the display data, it also supplies time control signals to the source line driver and the gate line driver. The controller and the time signal include a differential clock, which is a terminal for supplying a reference potential supplied to the plurality of source line drivers and the gate line driver; the controller is a display data of a differential form, supplied to the source line driver of the complex, the source line driver of the train of the complex having a differential input circuit receives the differential forms of display data, and the output of the latch circuit of the differential data input latch circuit, and In order to generate an output circuit of the driving signal, the data latch circuit is provided with two clock input circuits for inputting the differential clock. Among the differential input circuits in one of the clock input circuits, the The positive phase input terminal inputs the positive phase signal of the external clock, and the negative phase input terminal inputs the negative phase signal. In the differential input circuit of the other clock input circuit, the positive phase input terminal inputs the external clock signal. Negative-phase signal, input the positive-phase signal at the negative-phase input terminal, and the processing time of the above output signal is based on the above two times The two clock signals input by the pulse input circuit are processed. According to the clock control signal, display data is output to the output circuit. The power source circuit of the data latch circuit of the plurality of source line drivers is used by the above. Reference potential supplied by the terminal. 34. If you apply for a liquid crystal display system in the scope of patent application No. 33, in which the Chinese national standard (CNS) A4 specification (210X297 mm) applies to this paper size (please read the precautions on the back before filling this page) Order the Ministry of Economic Affairs Printed by the Consumer Property Cooperative of the Intellectual Property Bureau-13- 580673 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 ____ D8 I. Patent Application Scope External clock, serially output the first latch of one of the above two input signals and the second latch of the other, and each latch time of the first latch and the second latch, The two clock signals input by the two clock input signals are based on the clock signal output from the differential input circuit in one clock input circuit and the clock input circuit in the other. The clock signal output from the differential input circuit is provided separately. 35. If the liquid crystal display system of the 33rd or 34th in the scope of application for a patent, wherein the two clocks · signals input through the two clock input circuits described above are both by rising or falling , To provide the above time. This paper suitable for China's national scale quasi-knead (CNS) A4 size (210 X 297 mm) (Please read the back of the precautions to fill out this page) -14 ·